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/rtl/verilog/lib/BCDMath.v
0,0 → 1,291
`timescale 1ns / 1ps |
//============================================================================= |
// __ |
// \\__/ o\ (C) 2012 Robert Finch |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@opencores.org |
// || |
// |
// BCDMath.v |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// |
//============================================================================= |
// |
module BCDAdd(ci,a,b,o,c); |
input ci; // carry input |
input [7:0] a; |
input [7:0] b; |
output [7:0] o; |
output c; |
|
wire c0,c1; |
|
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci; |
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0; |
|
BCDAddAdjust u1 (hsN0,o[3:0],c0); |
BCDAddAdjust u2 (hsN1,o[7:4],c); |
|
endmodule |
|
module BCDAdd4(ci,a,b,o,c); |
input ci; // carry input |
input [15:0] a; |
input [15:0] b; |
output [15:0] o; |
output c; |
|
wire c0,c1,c2; |
|
wire [4:0] hsN0 = a[3:0] + b[3:0] + ci; |
wire [4:0] hsN1 = a[7:4] + b[7:4] + c0; |
wire [4:0] hsN2 = a[11:8] + b[11:8] + c1; |
wire [4:0] hsN3 = a[15:12] + b[15:12] + c2; |
|
BCDAddAdjust u1 (hsN0,o[3:0],c0); |
BCDAddAdjust u2 (hsN1,o[7:4],c1); |
BCDAddAdjust u3 (hsN2,o[11:8],c2); |
BCDAddAdjust u4 (hsN3,o[15:12],c); |
|
endmodule |
|
module BCDSub(ci,a,b,o,c); |
input ci; // carry input |
input [7:0] a; |
input [7:0] b; |
output [7:0] o; |
output c; |
|
wire c0,c1; |
|
wire [4:0] hdN0 = a[3:0] - b[3:0] - ci; |
wire [4:0] hdN1 = a[7:4] - b[7:4] - c0; |
|
BCDSubAdjust u1 (hdN0,o[3:0],c0); |
BCDSubAdjust u2 (hdN1,o[7:4],c); |
|
endmodule |
|
module BCDAddAdjust(i,o,c); |
input [4:0] i; |
output [3:0] o; |
reg [3:0] o; |
output c; |
reg c; |
always @(i) |
case(i) |
5'h0: begin o = 4'h0; c = 1'b0; end |
5'h1: begin o = 4'h1; c = 1'b0; end |
5'h2: begin o = 4'h2; c = 1'b0; end |
5'h3: begin o = 4'h3; c = 1'b0; end |
5'h4: begin o = 4'h4; c = 1'b0; end |
5'h5: begin o = 4'h5; c = 1'b0; end |
5'h6: begin o = 4'h6; c = 1'b0; end |
5'h7: begin o = 4'h7; c = 1'b0; end |
5'h8: begin o = 4'h8; c = 1'b0; end |
5'h9: begin o = 4'h9; c = 1'b0; end |
5'hA: begin o = 4'h0; c = 1'b1; end |
5'hB: begin o = 4'h1; c = 1'b1; end |
5'hC: begin o = 4'h2; c = 1'b1; end |
5'hD: begin o = 4'h3; c = 1'b1; end |
5'hE: begin o = 4'h4; c = 1'b1; end |
5'hF: begin o = 4'h5; c = 1'b1; end |
5'h10: begin o = 4'h6; c = 1'b1; end |
5'h11: begin o = 4'h7; c = 1'b1; end |
5'h12: begin o = 4'h8; c = 1'b1; end |
5'h13: begin o = 4'h9; c = 1'b1; end |
default: begin o = 4'h9; c = 1'b1; end |
endcase |
endmodule |
|
module BCDSubAdjust(i,o,c); |
input [4:0] i; |
output [3:0] o; |
reg [3:0] o; |
output c; |
reg c; |
always @(i) |
case(i) |
5'h0: begin o = 4'h0; c = 1'b0; end |
5'h1: begin o = 4'h1; c = 1'b0; end |
5'h2: begin o = 4'h2; c = 1'b0; end |
5'h3: begin o = 4'h3; c = 1'b0; end |
5'h4: begin o = 4'h4; c = 1'b0; end |
5'h5: begin o = 4'h5; c = 1'b0; end |
5'h6: begin o = 4'h6; c = 1'b0; end |
5'h7: begin o = 4'h7; c = 1'b0; end |
5'h8: begin o = 4'h8; c = 1'b0; end |
5'h9: begin o = 4'h9; c = 1'b0; end |
5'h16: begin o = 4'h0; c = 1'b1; end |
5'h17: begin o = 4'h1; c = 1'b1; end |
5'h18: begin o = 4'h2; c = 1'b1; end |
5'h19: begin o = 4'h3; c = 1'b1; end |
5'h1A: begin o = 4'h4; c = 1'b1; end |
5'h1B: begin o = 4'h5; c = 1'b1; end |
5'h1C: begin o = 4'h6; c = 1'b1; end |
5'h1D: begin o = 4'h7; c = 1'b1; end |
5'h1E: begin o = 4'h8; c = 1'b1; end |
5'h1F: begin o = 4'h9; c = 1'b1; end |
default: begin o = 4'h9; c = 1'b1; end |
endcase |
endmodule |
|
// Multiply two BCD digits |
// Method used is table lookup |
module BCDMul1(a,b,o); |
input [3:0] a; |
input [3:0] b; |
output [7:0] o; |
reg [7:0] o; |
|
always @(a or b) |
casex({a,b}) |
8'h00: o = 8'h00; |
8'h01: o = 8'h00; |
8'h02: o = 8'h00; |
8'h03: o = 8'h00; |
8'h04: o = 8'h00; |
8'h05: o = 8'h00; |
8'h06: o = 8'h00; |
8'h07: o = 8'h00; |
8'h08: o = 8'h00; |
8'h09: o = 8'h00; |
8'h10: o = 8'h00; |
8'h11: o = 8'h01; |
8'h12: o = 8'h02; |
8'h13: o = 8'h03; |
8'h14: o = 8'h04; |
8'h15: o = 8'h05; |
8'h16: o = 8'h06; |
8'h17: o = 8'h07; |
8'h18: o = 8'h08; |
8'h19: o = 8'h09; |
8'h20: o = 8'h00; |
8'h21: o = 8'h02; |
8'h22: o = 8'h04; |
8'h23: o = 8'h06; |
8'h24: o = 8'h08; |
8'h25: o = 8'h10; |
8'h26: o = 8'h12; |
8'h27: o = 8'h14; |
8'h28: o = 8'h16; |
8'h29: o = 8'h18; |
8'h30: o = 8'h00; |
8'h31: o = 8'h03; |
8'h32: o = 8'h06; |
8'h33: o = 8'h09; |
8'h34: o = 8'h12; |
8'h35: o = 8'h15; |
8'h36: o = 8'h18; |
8'h37: o = 8'h21; |
8'h38: o = 8'h24; |
8'h39: o = 8'h27; |
8'h40: o = 8'h00; |
8'h41: o = 8'h04; |
8'h42: o = 8'h08; |
8'h43: o = 8'h12; |
8'h44: o = 8'h16; |
8'h45: o = 8'h20; |
8'h46: o = 8'h24; |
8'h47: o = 8'h28; |
8'h48: o = 8'h32; |
8'h49: o = 8'h36; |
8'h50: o = 8'h00; |
8'h51: o = 8'h05; |
8'h52: o = 8'h10; |
8'h53: o = 8'h15; |
8'h54: o = 8'h20; |
8'h55: o = 8'h25; |
8'h56: o = 8'h30; |
8'h57: o = 8'h35; |
8'h58: o = 8'h40; |
8'h59: o = 8'h45; |
8'h60: o = 8'h00; |
8'h61: o = 8'h06; |
8'h62: o = 8'h12; |
8'h63: o = 8'h18; |
8'h64: o = 8'h24; |
8'h65: o = 8'h30; |
8'h66: o = 8'h36; |
8'h67: o = 8'h42; |
8'h68: o = 8'h48; |
8'h69: o = 8'h54; |
8'h70: o = 8'h00; |
8'h71: o = 8'h07; |
8'h72: o = 8'h14; |
8'h73: o = 8'h21; |
8'h74: o = 8'h28; |
8'h75: o = 8'h35; |
8'h76: o = 8'h42; |
8'h77: o = 8'h49; |
8'h78: o = 8'h56; |
8'h79: o = 8'h63; |
8'h80: o = 8'h00; |
8'h81: o = 8'h08; |
8'h82: o = 8'h16; |
8'h83: o = 8'h24; |
8'h84: o = 8'h32; |
8'h85: o = 8'h40; |
8'h86: o = 8'h48; |
8'h87: o = 8'h56; |
8'h88: o = 8'h64; |
8'h89: o = 8'h72; |
8'h90: o = 8'h00; |
8'h91: o = 8'h09; |
8'h92: o = 8'h18; |
8'h93: o = 8'h27; |
8'h94: o = 8'h36; |
8'h95: o = 8'h45; |
8'h96: o = 8'h54; |
8'h97: o = 8'h63; |
8'h98: o = 8'h72; |
8'h99: o = 8'h81; |
default: o = 8'h00; |
endcase |
endmodule |
|
|
// Multiply two pairs of BCD digits |
// handles from 0x0 to 99x99 |
module BCDMul2(a,b,o); |
input [7:0] a; |
input [7:0] b; |
output [15:0] o; |
|
wire [7:0] p1,p2,p3,p4; |
wire [15:0] s1; |
|
BCDMul1 u1 (a[3:0],b[3:0],p1); |
BCDMul1 u2 (a[7:4],b[3:0],p2); |
BCDMul1 u3 (a[3:0],b[7:4],p3); |
BCDMul1 u4 (a[7:4],b[7:4],p4); |
|
BCDAdd4 u5 (1'b0,{p4,p1},{4'h0,p2,4'h0},s1); |
BCDAdd4 u6 (1'b0,s1,{4'h0,p3,4'h0},o); |
|
endmodule |
|
module BCDMul_tb(); |
|
wire [15:0] o1,o2,o3,o4; |
|
BCDMul2 u1 (8'h00,8'h00,o1); |
BCDMul2 u2 (8'h99,8'h99,o2); |
BCDMul2 u3 (8'h25,8'h18,o3); |
BCDMul2 u4 (8'h37,8'h21,o4); |
|
endmodule |
/rtl/verilog/lib/cntpop.v
0,0 → 1,381
/* =============================================================== |
(C) 2006 Robert Finch |
All rights reserved. |
rob@birdcomputer.ca |
|
cntpop.v |
- count number of one bits in a byte |
- simple fast approach - lookup table |
|
This source code is free for use and modification for |
non-commercial or evaluation purposes, provided this |
copyright statement and disclaimer remains present in |
the file. |
|
If the code is modified, please state the origin and |
note that the code has been modified. |
|
NO WARRANTY. |
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF |
ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume |
the entire risk of using the Work. |
|
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR |
ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES |
WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR |
RELATIONSHIP WITH THE AUTHOR. |
|
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU |
TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE |
WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED |
TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS |
OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, |
AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS |
FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED |
USE. |
|
Ref: Webpack 8.1i Spartan3-4 xc3s1000-4ft256 |
11 LUTs / 6 slices / 12.2 ns |
|
=============================================================== */ |
|
module cntpop8( |
input [7:0] i, |
output reg [3:0] o |
); |
|
always @(i) |
case (i) |
8'b00000000: o = 0; |
8'b00000001: o = 1; |
8'b00000010: o = 1; |
8'b00000011: o = 2; |
8'b00000100: o = 1; |
8'b00000101: o = 2; |
8'b00000110: o = 2; |
8'b00000111: o = 3; |
8'b00001000: o = 1; |
8'b00001001: o = 2; |
8'b00001010: o = 2; |
8'b00001011: o = 3; |
8'b00001100: o = 2; |
8'b00001101: o = 3; |
8'b00001110: o = 3; |
8'b00001111: o = 4; |
|
8'b00010000: o = 1; |
8'b00010001: o = 2; |
8'b00010010: o = 2; |
8'b00010011: o = 3; |
8'b00010100: o = 2; |
8'b00010101: o = 3; |
8'b00010110: o = 3; |
8'b00010111: o = 4; |
8'b00011000: o = 2; |
8'b00011001: o = 3; |
8'b00011010: o = 3; |
8'b00011011: o = 4; |
8'b00011100: o = 3; |
8'b00011101: o = 4; |
8'b00011110: o = 4; |
8'b00011111: o = 5; |
|
8'b00100000: o = 1; |
8'b00100001: o = 2; |
8'b00100010: o = 2; |
8'b00100011: o = 3; |
8'b00100100: o = 2; |
8'b00100101: o = 3; |
8'b00100110: o = 3; |
8'b00100111: o = 4; |
8'b00101000: o = 2; |
8'b00101001: o = 3; |
8'b00101010: o = 3; |
8'b00101011: o = 4; |
8'b00101100: o = 3; |
8'b00101101: o = 4; |
8'b00101110: o = 4; |
8'b00101111: o = 5; |
|
8'b00110000: o = 2; |
8'b00110001: o = 3; |
8'b00110010: o = 3; |
8'b00110011: o = 4; |
8'b00110100: o = 3; |
8'b00110101: o = 4; |
8'b00110110: o = 4; |
8'b00110111: o = 5; |
8'b00111000: o = 3; |
8'b00111001: o = 4; |
8'b00111010: o = 4; |
8'b00111011: o = 5; |
8'b00111100: o = 4; |
8'b00111101: o = 5; |
8'b00111110: o = 5; |
8'b00111111: o = 6; |
|
// 44 - 1 |
8'b01000000: o = 1; |
8'b01000001: o = 2; |
8'b01000010: o = 2; |
8'b01000011: o = 3; |
8'b01000100: o = 2; |
8'b01000101: o = 3; |
8'b01000110: o = 3; |
8'b01000111: o = 4; |
8'b01001000: o = 2; |
8'b01001001: o = 3; |
8'b01001010: o = 3; |
8'b01001011: o = 4; |
8'b01001100: o = 3; |
8'b01001101: o = 4; |
8'b01001110: o = 4; |
8'b01001111: o = 5; |
|
8'b01010000: o = 2; |
8'b01010001: o = 3; |
8'b01010010: o = 3; |
8'b01010011: o = 4; |
8'b01010100: o = 3; |
8'b01010101: o = 4; |
8'b01010110: o = 4; |
8'b01010111: o = 5; |
8'b01011000: o = 3; |
8'b01011001: o = 4; |
8'b01011010: o = 4; |
8'b01011011: o = 5; |
8'b01011100: o = 4; |
8'b01011101: o = 5; |
8'b01011110: o = 5; |
8'b01011111: o = 6; |
|
8'b01100000: o = 2; |
8'b01100001: o = 3; |
8'b01100010: o = 3; |
8'b01100011: o = 4; |
8'b01100100: o = 3; |
8'b01100101: o = 4; |
8'b01100110: o = 4; |
8'b01100111: o = 5; |
8'b01101000: o = 3; |
8'b01101001: o = 4; |
8'b01101010: o = 4; |
8'b01101011: o = 5; |
8'b01101100: o = 4; |
8'b01101101: o = 5; |
8'b01101110: o = 5; |
8'b01101111: o = 6; |
|
8'b01110000: o = 3; |
8'b01110001: o = 4; |
8'b01110010: o = 4; |
8'b01110011: o = 5; |
8'b01110100: o = 4; |
8'b01110101: o = 5; |
8'b01110110: o = 5; |
8'b01110111: o = 6; |
8'b01111000: o = 4; |
8'b01111001: o = 5; |
8'b01111010: o = 5; |
8'b01111011: o = 6; |
8'b01111100: o = 5; |
8'b01111101: o = 6; |
8'b01111110: o = 6; |
8'b01111111: o = 7; |
|
// - 2 |
8'b10000000: o = 1; |
8'b10000001: o = 2; |
8'b10000010: o = 2; |
8'b10000011: o = 3; |
8'b10000100: o = 2; |
8'b10000101: o = 3; |
8'b10000110: o = 3; |
8'b10000111: o = 4; |
8'b10001000: o = 2; |
8'b10001001: o = 3; |
8'b10001010: o = 3; |
8'b10001011: o = 4; |
8'b10001100: o = 3; |
8'b10001101: o = 4; |
8'b10001110: o = 4; |
8'b10001111: o = 5; |
|
8'b10010000: o = 2; |
8'b10010001: o = 3; |
8'b10010010: o = 3; |
8'b10010011: o = 4; |
8'b10010100: o = 3; |
8'b10010101: o = 4; |
8'b10010110: o = 4; |
8'b10010111: o = 5; |
8'b10011000: o = 3; |
8'b10011001: o = 4; |
8'b10011010: o = 4; |
8'b10011011: o = 5; |
8'b10011100: o = 4; |
8'b10011101: o = 5; |
8'b10011110: o = 5; |
8'b10011111: o = 6; |
|
8'b10100000: o = 2; |
8'b10100001: o = 3; |
8'b10100010: o = 3; |
8'b10100011: o = 4; |
8'b10100100: o = 3; |
8'b10100101: o = 4; |
8'b10100110: o = 4; |
8'b10100111: o = 5; |
8'b10101000: o = 3; |
8'b10101001: o = 4; |
8'b10101010: o = 4; |
8'b10101011: o = 5; |
8'b10101100: o = 4; |
8'b10101101: o = 5; |
8'b10101110: o = 5; |
8'b10101111: o = 6; |
|
8'b10110000: o = 3; |
8'b10110001: o = 4; |
8'b10110010: o = 4; |
8'b10110011: o = 5; |
8'b10110100: o = 4; |
8'b10110101: o = 5; |
8'b10110110: o = 5; |
8'b10110111: o = 6; |
8'b10111000: o = 4; |
8'b10111001: o = 5; |
8'b10111010: o = 5; |
8'b10111011: o = 6; |
8'b10111100: o = 5; |
8'b10111101: o = 6; |
8'b10111110: o = 6; |
8'b10111111: o = 7; |
|
// 44 - 3 |
8'b11000000: o = 2; |
8'b11000001: o = 3; |
8'b11000010: o = 3; |
8'b11000011: o = 4; |
8'b11000100: o = 3; |
8'b11000101: o = 4; |
8'b11000110: o = 4; |
8'b11000111: o = 5; |
8'b11001000: o = 3; |
8'b11001001: o = 4; |
8'b11001010: o = 4; |
8'b11001011: o = 5; |
8'b11001100: o = 4; |
8'b11001101: o = 5; |
8'b11001110: o = 5; |
8'b11001111: o = 6; |
|
8'b11010000: o = 3; |
8'b11010001: o = 4; |
8'b11010010: o = 4; |
8'b11010011: o = 5; |
8'b11010100: o = 4; |
8'b11010101: o = 5; |
8'b11010110: o = 5; |
8'b11010111: o = 6; |
8'b11011000: o = 4; |
8'b11011001: o = 5; |
8'b11011010: o = 5; |
8'b11011011: o = 6; |
8'b11011100: o = 5; |
8'b11011101: o = 6; |
8'b11011110: o = 6; |
8'b11011111: o = 7; |
|
8'b11100000: o = 3; |
8'b11100001: o = 4; |
8'b11100010: o = 4; |
8'b11100011: o = 5; |
8'b11100100: o = 4; |
8'b11100101: o = 5; |
8'b11100110: o = 5; |
8'b11100111: o = 6; |
8'b11101000: o = 4; |
8'b11101001: o = 5; |
8'b11101010: o = 5; |
8'b11101011: o = 6; |
8'b11101100: o = 5; |
8'b11101101: o = 6; |
8'b11101110: o = 6; |
8'b11101111: o = 7; |
|
8'b11110000: o = 4; |
8'b11110001: o = 5; |
8'b11110010: o = 5; |
8'b11110011: o = 6; |
8'b11110100: o = 5; |
8'b11110101: o = 6; |
8'b11110110: o = 6; |
8'b11110111: o = 7; |
8'b11111000: o = 5; |
8'b11111001: o = 6; |
8'b11111010: o = 6; |
8'b11111011: o = 7; |
8'b11111100: o = 6; |
8'b11111101: o = 7; |
8'b11111110: o = 7; |
8'b11111111: o = 8; |
|
endcase |
|
|
endmodule |
|
|
module cntpop16( |
input [15:0] i, |
output [4:0] o |
); |
|
wire [3:0] cnt1, cnt2; |
|
cntpop8 u1 (i[ 7:0],cnt1); |
cntpop8 u2 (i[15:8],cnt2); |
|
assign o = cnt1 + cnt2; |
|
endmodule |
|
|
// 76 slices / 147 LUTs / 19 ns |
module cntpop32( |
input [31:0] i, |
output [5:0] o |
); |
|
wire [3:0] cnt1, cnt2, cnt3, cnt4; |
|
// cntpop8 results in faster result than cntpop16 |
cntpop8 u1 (i[ 7: 0],cnt1); |
cntpop8 u2 (i[15: 8],cnt2); |
cntpop8 u3 (i[23:16],cnt3); |
cntpop8 u4 (i[31:24],cnt4); |
|
assign o = cnt1+cnt2+cnt3+cnt4; |
|
endmodule |
|
|
// 156 slices / 300 LUTs / 22.2 ns |
module cntpop64( |
input [63:0] i, |
output [6:0] o |
); |
|
wire [4:0] cnt1, cnt2, cnt3, cnt4; |
|
cntpop16 u1 (i[15: 0],cnt1); |
cntpop16 u2 (i[31:16],cnt2); |
cntpop16 u3 (i[47:32],cnt3); |
cntpop16 u4 (i[63:48],cnt4); |
|
assign o = cnt1+cnt2+cnt3+cnt4; |
|
endmodule |
|
|
/rtl/verilog/lib/cntlz.v
0,0 → 1,511
/* =============================================================== |
(C) 2006 Robert Finch |
All rights reserved. |
rob@birdcomputer.ca |
|
cntlz.v |
- count number of leading zeros in a byte |
- count number of leading ones in a byte |
- simple fast approach - lookup table |
|
This source code is free for use and modification for |
non-commercial or evaluation purposes, provided this |
copyright statement and disclaimer remains present in |
the file. |
|
If the code is modified, please state the origin and |
note that the code has been modified. |
|
NO WARRANTY. |
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF |
ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume |
the entire risk of using the Work. |
|
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR |
ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES |
WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR |
RELATIONSHIP WITH THE AUTHOR. |
|
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU |
TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE |
WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED |
TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS |
OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, |
AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS |
FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED |
USE. |
|
Ref: Webpack 8.1i Spartan3-4 xc3s1000-4ft256 |
11 LUTs / 6 slices / 12.2 ns |
|
=============================================================== */ |
|
module cntlz8( |
input [7:0] i, |
output reg [3:0] o |
); |
|
always @(i) |
case (i) |
8'b00000000: o = 8; |
8'b00000001: o = 7; |
8'b00000010: o = 6; |
8'b00000011: o = 6; |
8'b00000100: o = 5; |
8'b00000101: o = 5; |
8'b00000110: o = 5; |
8'b00000111: o = 5; |
8'b00001000: o = 4; |
8'b00001001: o = 4; |
8'b00001010: o = 4; |
8'b00001011: o = 4; |
8'b00001100: o = 4; |
8'b00001101: o = 4; |
8'b00001110: o = 4; |
8'b00001111: o = 4; |
|
8'b00010000: o = 3; |
8'b00010001: o = 3; |
8'b00010010: o = 3; |
8'b00010011: o = 3; |
8'b00010100: o = 3; |
8'b00010101: o = 3; |
8'b00010110: o = 3; |
8'b00010111: o = 3; |
8'b00011000: o = 3; |
8'b00011001: o = 3; |
8'b00011010: o = 3; |
8'b00011011: o = 3; |
8'b00011100: o = 3; |
8'b00011101: o = 3; |
8'b00011110: o = 3; |
8'b00011111: o = 3; |
|
8'b00100000: o = 2; |
8'b00100001: o = 2; |
8'b00100010: o = 2; |
8'b00100011: o = 2; |
8'b00100100: o = 2; |
8'b00100101: o = 2; |
8'b00100110: o = 2; |
8'b00100111: o = 2; |
8'b00101000: o = 2; |
8'b00101001: o = 2; |
8'b00101010: o = 2; |
8'b00101011: o = 2; |
8'b00101100: o = 2; |
8'b00101101: o = 2; |
8'b00101110: o = 2; |
8'b00101111: o = 2; |
|
8'b00110000: o = 2; |
8'b00110001: o = 2; |
8'b00110010: o = 2; |
8'b00110011: o = 2; |
8'b00110100: o = 2; |
8'b00110101: o = 2; |
8'b00110110: o = 2; |
8'b00110111: o = 2; |
8'b00111000: o = 2; |
8'b00111001: o = 2; |
8'b00111010: o = 2; |
8'b00111011: o = 2; |
8'b00111100: o = 2; |
8'b00111101: o = 2; |
8'b00111110: o = 2; |
8'b00111111: o = 2; |
|
// 44 - 1 |
8'b01000000: o = 1; |
8'b01000001: o = 1; |
8'b01000010: o = 1; |
8'b01000011: o = 1; |
8'b01000100: o = 1; |
8'b01000101: o = 1; |
8'b01000110: o = 1; |
8'b01000111: o = 1; |
8'b01001000: o = 1; |
8'b01001001: o = 1; |
8'b01001010: o = 1; |
8'b01001011: o = 1; |
8'b01001100: o = 1; |
8'b01001101: o = 1; |
8'b01001110: o = 1; |
8'b01001111: o = 1; |
|
8'b01010000: o = 1; |
8'b01010001: o = 1; |
8'b01010010: o = 1; |
8'b01010011: o = 1; |
8'b01010100: o = 1; |
8'b01010101: o = 1; |
8'b01010110: o = 1; |
8'b01010111: o = 1; |
8'b01011000: o = 1; |
8'b01011001: o = 1; |
8'b01011010: o = 1; |
8'b01011011: o = 1; |
8'b01011100: o = 1; |
8'b01011101: o = 1; |
8'b01011110: o = 1; |
8'b01011111: o = 1; |
|
8'b01100000: o = 1; |
8'b01100001: o = 1; |
8'b01100010: o = 1; |
8'b01100011: o = 1; |
8'b01100100: o = 1; |
8'b01100101: o = 1; |
8'b01100110: o = 1; |
8'b01100111: o = 1; |
8'b01101000: o = 1; |
8'b01101001: o = 1; |
8'b01101010: o = 1; |
8'b01101011: o = 1; |
8'b01101100: o = 1; |
8'b01101101: o = 1; |
8'b01101110: o = 1; |
8'b01101111: o = 1; |
|
8'b01110000: o = 1; |
8'b01110001: o = 1; |
8'b01110010: o = 1; |
8'b01110011: o = 1; |
8'b01110100: o = 1; |
8'b01110101: o = 1; |
8'b01110110: o = 1; |
8'b01110111: o = 1; |
8'b01111000: o = 1; |
8'b01111001: o = 1; |
8'b01111010: o = 1; |
8'b01111011: o = 1; |
8'b01111100: o = 1; |
8'b01111101: o = 1; |
8'b01111110: o = 1; |
8'b01111111: o = 1; |
|
// - 2 |
8'b10000000: o = 0; |
8'b10000001: o = 0; |
8'b10000010: o = 0; |
8'b10000011: o = 0; |
8'b10000100: o = 0; |
8'b10000101: o = 0; |
8'b10000110: o = 0; |
8'b10000111: o = 0; |
8'b10001000: o = 0; |
8'b10001001: o = 0; |
8'b10001010: o = 0; |
8'b10001011: o = 0; |
8'b10001100: o = 0; |
8'b10001101: o = 0; |
8'b10001110: o = 0; |
8'b10001111: o = 0; |
|
8'b10010000: o = 0; |
8'b10010001: o = 0; |
8'b10010010: o = 0; |
8'b10010011: o = 0; |
8'b10010100: o = 0; |
8'b10010101: o = 0; |
8'b10010110: o = 0; |
8'b10010111: o = 0; |
8'b10011000: o = 0; |
8'b10011001: o = 0; |
8'b10011010: o = 0; |
8'b10011011: o = 0; |
8'b10011100: o = 0; |
8'b10011101: o = 0; |
8'b10011110: o = 0; |
8'b10011111: o = 0; |
|
8'b10100000: o = 0; |
8'b10100001: o = 0; |
8'b10100010: o = 0; |
8'b10100011: o = 0; |
8'b10100100: o = 0; |
8'b10100101: o = 0; |
8'b10100110: o = 0; |
8'b10100111: o = 0; |
8'b10101000: o = 0; |
8'b10101001: o = 0; |
8'b10101010: o = 0; |
8'b10101011: o = 0; |
8'b10101100: o = 0; |
8'b10101101: o = 0; |
8'b10101110: o = 0; |
8'b10101111: o = 0; |
|
8'b10110000: o = 0; |
8'b10110001: o = 0; |
8'b10110010: o = 0; |
8'b10110011: o = 0; |
8'b10110100: o = 0; |
8'b10110101: o = 0; |
8'b10110110: o = 0; |
8'b10110111: o = 0; |
8'b10111000: o = 0; |
8'b10111001: o = 0; |
8'b10111010: o = 0; |
8'b10111011: o = 0; |
8'b10111100: o = 0; |
8'b10111101: o = 0; |
8'b10111110: o = 0; |
8'b10111111: o = 0; |
|
// 44 - 3 |
8'b11000000: o = 0; |
8'b11000001: o = 0; |
8'b11000010: o = 0; |
8'b11000011: o = 0; |
8'b11000100: o = 0; |
8'b11000101: o = 0; |
8'b11000110: o = 0; |
8'b11000111: o = 0; |
8'b11001000: o = 0; |
8'b11001001: o = 0; |
8'b11001010: o = 0; |
8'b11001011: o = 0; |
8'b11001100: o = 0; |
8'b11001101: o = 0; |
8'b11001110: o = 0; |
8'b11001111: o = 0; |
|
8'b11010000: o = 0; |
8'b11010001: o = 0; |
8'b11010010: o = 0; |
8'b11010011: o = 0; |
8'b11010100: o = 0; |
8'b11010101: o = 0; |
8'b11010110: o = 0; |
8'b11010111: o = 0; |
8'b11011000: o = 0; |
8'b11011001: o = 0; |
8'b11011010: o = 0; |
8'b11011011: o = 0; |
8'b11011100: o = 0; |
8'b11011101: o = 0; |
8'b11011110: o = 0; |
8'b11011111: o = 0; |
|
8'b11100000: o = 0; |
8'b11100001: o = 0; |
8'b11100010: o = 0; |
8'b11100011: o = 0; |
8'b11100100: o = 0; |
8'b11100101: o = 0; |
8'b11100110: o = 0; |
8'b11100111: o = 0; |
8'b11101000: o = 0; |
8'b11101001: o = 0; |
8'b11101010: o = 0; |
8'b11101011: o = 0; |
8'b11101100: o = 0; |
8'b11101101: o = 0; |
8'b11101110: o = 0; |
8'b11101111: o = 0; |
|
8'b11110000: o = 0; |
8'b11110001: o = 0; |
8'b11110010: o = 0; |
8'b11110011: o = 0; |
8'b11110100: o = 0; |
8'b11110101: o = 0; |
8'b11110110: o = 0; |
8'b11110111: o = 0; |
8'b11111000: o = 0; |
8'b11111001: o = 0; |
8'b11111010: o = 0; |
8'b11111011: o = 0; |
8'b11111100: o = 0; |
8'b11111101: o = 0; |
8'b11111110: o = 0; |
8'b11111111: o = 0; |
|
endcase |
|
|
endmodule |
|
|
module cntlz16( |
input [15:0] i, |
output [4:0] o |
); |
|
wire [3:0] cnt1, cnt2; |
|
cntlz8 u1 (i[ 7:0],cnt1); |
cntlz8 u2 (i[15:8],cnt2); |
|
assign o = cnt2[3] ? cnt1 + 4'h8 : cnt2; |
|
endmodule |
|
|
// 39 slices / 67 LUTs / 19.3ns |
module cntlz24( |
input [23:0] i, |
output [4:0] o |
); |
|
wire [3:0] cnt1, cnt2, cnt3; |
|
// cntlz8 results in faster result than cntlz16 |
cntlz8 u1 (i[ 7: 0],cnt1); |
cntlz8 u2 (i[15: 8],cnt2); |
cntlz8 u3 (i[23:16],cnt3); |
|
assign o = |
!cnt3[3] ? cnt3 : |
!cnt2[3] ? cnt2 + 5'd8 : |
cnt1 + 5'd16; |
|
endmodule |
|
// 39 slices / 67 LUTs / 19.3ns |
module cntlz32( |
input [31:0] i, |
output [5:0] o |
); |
|
wire [3:0] cnt1, cnt2, cnt3, cnt4; |
|
// cntlz8 results in faster result than cntlz16 |
cntlz8 u1 (i[ 7: 0],cnt1); |
cntlz8 u2 (i[15: 8],cnt2); |
cntlz8 u3 (i[23:16],cnt3); |
cntlz8 u4 (i[31:24],cnt4); |
|
assign o = |
!cnt4[3] ? cnt4 : |
!cnt3[3] ? cnt3 + 6'd8 : |
!cnt2[3] ? cnt2 + 6'd16 : |
cnt1 + 6'd24; |
|
endmodule |
|
|
// 88 slices / 154 LUTs / 22.5 ns |
module cntlz48( |
input [47:0] i, |
output [5:0] o |
); |
|
wire [4:0] cnt1, cnt2, cnt3; |
|
cntlz16 u1 (i[15: 0],cnt1); |
cntlz16 u2 (i[31:16],cnt2); |
cntlz16 u3 (i[47:32],cnt3); |
|
assign o = |
!cnt3[4] ? cnt3 : |
!cnt2[4] ? cnt2 + 7'd16 : |
cnt1 + 7'd32; |
|
endmodule |
|
|
// 88 slices / 154 LUTs / 22.5 ns |
module cntlz64( |
input [63:0] i, |
output [6:0] o |
); |
|
wire [4:0] cnt1, cnt2, cnt3, cnt4; |
|
cntlz16 u1 (i[15: 0],cnt1); |
cntlz16 u2 (i[31:16],cnt2); |
cntlz16 u3 (i[47:32],cnt3); |
cntlz16 u4 (i[63:48],cnt4); |
|
assign o = |
!cnt4[4] ? cnt4 : |
!cnt3[4] ? cnt3 + 7'd16 : |
!cnt2[4] ? cnt2 + 7'd32 : |
cnt1 + 7'd48; |
|
endmodule |
|
|
module cntlz32Reg( |
input clk, |
input ce, |
input [31:0] i, |
output reg [5:0] o |
); |
|
wire [5:0] o1; |
cntlz32 u1 (i,o1); |
always @(posedge clk) |
if (ce) o <= o1; |
|
endmodule |
|
|
module cntlz64Reg( |
input clk, |
input ce, |
input [63:0] i, |
output reg [6:0] o |
); |
|
wire [6:0] o1; |
cntlz64 u1 (i,o1); |
always @(posedge clk) |
if (ce) o <= o1; |
|
endmodule |
|
// 5 slices / 10 LUTs / 7.702 ns |
module cntlo8( |
input [7:0] i, |
output [3:0] o |
); |
|
cntlz8 u1 (~i,o); |
|
endmodule |
|
|
module cntlo16( |
input [15:0] i, |
output [4:0] o |
); |
|
cntlz16 u1 (~i,o); |
|
endmodule |
|
|
module cntlo32( |
input [31:0] i, |
output [5:0] o |
); |
|
cntlz32 u1 (~i,o); |
|
endmodule |
|
|
module cntlo48( |
input [47:0] i, |
output [5:0] o |
); |
|
cntlz48 u1 (~i,o); |
|
endmodule |
|
|
// 59 slices / 99 LUTs / 14.065 ns |
module cntlo64( |
input [63:0] i, |
output [6:0] o |
); |
|
cntlz64 u1 (~i,o); |
|
endmodule |
|
|