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https://opencores.org/ocsvn/thor/thor/trunk
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- This comparison shows the changes necessary to convert path
/thor/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/rtl/verilog/memory/syncRam2kx32_1w1r.v
0,0 → 1,57
module syncRam2kx32_1w1r (wclk, wce, wr, wa, wd, rclk, rce, ra, o); |
input wclk; |
input wce; |
input [3:0] wr; |
input [10:0] wa; |
input [31:0] wd; |
input rclk; |
input rce; |
input [10:0] ra; |
output [31:0] o; |
|
syncRam2kx8_1rw1r um0 ( |
.wclk(wclk), |
.wce(wce), |
.wr(wr[0]), |
.wa(wa), |
.wd(wd[7:0]), |
.rclk(rclk), |
.rce(1'b1), |
.ra(ra), |
.o(o[7:0]) |
); |
syncRam2kx8_1rw1r um1 ( |
.wclk(wclk), |
.wce(wce), |
.wr(wr[1]), |
.wa(wa), |
.wd(wd[15:8]), |
.rclk(rclk), |
.rce(1'b1), |
.ra(ra), |
.o(o[15:8]) |
); |
syncRam2kx8_1rw1r um2 ( |
.wclk(wclk), |
.wce(wce), |
.wr(wr[2]), |
.wa(wa), |
.wd(wd[23:16]), |
.rclk(rclk), |
.rce(1'b1), |
.ra(ra), |
.o(o[23:16]) |
); |
syncRam2kx8_1rw1r um3 ( |
.wclk(wclk), |
.wce(wce), |
.wr(wr[3]), |
.wa(wa), |
.wd(wd[31:24]), |
.rclk(rclk), |
.rce(1'b1), |
.ra(ra), |
.o(o[31:24]) |
); |
|
endmodule |
/rtl/verilog/memory/syncRam2kx8_1rw2r.v
0,0 → 1,75
/* =============================================================== |
(C) 2006 Robert Finch |
All rights reserved. |
rob@birdcomputer.ca |
|
syncRam2kx8_1rw1r.v |
|
This source code is free for use and modification for |
non-commercial or evaluation purposes, provided this |
copyright statement and disclaimer remains present in |
the file. |
|
If you do modify the code, please state the origin and |
note that you have modified the code. |
|
NO WARRANTY. |
THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF |
ANY KIND, WHETHER EXPRESS OR IMPLIED. The user must assume |
the entire risk of using the Work. |
|
IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR |
ANY INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES |
WHATSOEVER RELATING TO THE USE OF THIS WORK, OR YOUR |
RELATIONSHIP WITH THE AUTHOR. |
|
IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU |
TO USE THE WORK IN APPLICATIONS OR SYSTEMS WHERE THE |
WORK'S FAILURE TO PERFORM CAN REASONABLY BE EXPECTED |
TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN LOSS |
OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, |
AND YOU AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS |
FROM ANY CLAIMS OR LOSSES RELATING TO SUCH UNAUTHORIZED |
USE. |
|
|
=============================================================== */ |
|
`define SYNTHESIS |
`define VENDOR_XILINX |
`define SPARTAN3 |
|
module syncRam2kx8_1rw2r( |
input wrst, |
input wclk, |
input wce, |
input we, |
input [10:0] wadr, |
input [7:0] i, |
output [7:0] wo, |
input rrst, |
input rclk, |
input rce, |
input [10:0] radr0, |
output [7:0] o0, |
input [10:0] radr1, |
output [7:0] o1 |
); |
|
`ifdef SYNTHESIS |
`ifdef VENDOR_XILINX |
|
`ifdef SPARTAN3 |
RAMB16_S9_S9 ram0( |
.CLKA(wclk), .ADDRA(wadr), .DIA(i), .DIPA(^i), .DOA(wo), .ENA(wce), .WEA(we), .SSRA(wrst), |
.CLKB(rclk), .ADDRB(radr0), .DIB(8'hFF), .DIPB(1'b1), .DOB(o0), .ENB(rce), .WEB(1'b0), .SSRB(rrst) ); |
RAMB16_S9_S9 ram0( |
.CLKA(wclk), .ADDRA(wadr), .DIA(i), .DIPA(^i), .DOA(wo), .ENA(wce), .WEA(we), .SSRA(wrst), |
.CLKB(rclk), .ADDRB(radr1), .DIB(8'hFF), .DIPB(1'b1), .DOB(o1), .ENB(rce), .WEB(1'b0), .SSRB(rrst) ); |
`endif |
|
`endif |
|
`endif |
|
endmodule |