URL
https://opencores.org/ocsvn/threeaesc/threeaesc/trunk
Subversion Repositories threeaesc
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/threeaesc
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/trunk/key_schedule/scripts/sim.do
0,0 → 1,39
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/key_schedule.vhd" |
vcom -explicit -93 "src/tb_key_schedule.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_key_schedule |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_key_schedule/uut/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_key_schedule/uut/s_box_dual_2 |
|
add wave \ |
{sim:/tb_key_schedule/uut/count_5 } |
add wave \ |
{sim:/tb_key_schedule/uut/count_10 } |
|
add wave \ |
{sim:/tb_key_schedule/uut/g_sub_0_s } |
add wave \ |
{sim:/tb_key_schedule/uut/g_sub_1_s } |
add wave \ |
{sim:/tb_key_schedule/uut/g_sub_2_s } |
add wave \ |
{sim:/tb_key_schedule/uut/g_sub_3_s } |
|
run 10 us |
/trunk/key_schedule/src/dual_mem.vhd
0,0 → 1,57
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity dual_mem is |
generic (ADDR_LENGTH : integer := 8; |
DATA_LENGTH : integer := 8; |
N_ADDR : integer := 256); |
port (clk : in std_logic; |
we : in std_logic; |
a : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
di : in std_logic_vector(DATA_LENGTH - 1 downto 0); |
spo : out std_logic_vector(DATA_LENGTH - 1 downto 0); |
dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0)); |
end dual_mem; |
|
architecture rtl of dual_mem is |
type ram_type is array (N_ADDR - 1 downto 0) |
of std_logic_vector (DATA_LENGTH - 1 downto 0); |
signal RAM : ram_type; |
signal read_a : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
signal read_dpra : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
|
attribute ram_style: string; |
attribute ram_style of RAM: signal is "block"; |
|
begin |
process (clk) |
begin |
if rising_edge(clk) then |
if (we = '1') then |
RAM(conv_integer(a)) <= di; |
end if; |
read_a <= a; |
read_dpra <= dpra; |
end if; |
end process; |
|
spo <= RAM(conv_integer(read_a)); |
dpo <= RAM(conv_integer(read_dpra)); |
end rtl; |
/trunk/key_schedule/src/key_schedule.vhd
0,0 → 1,130
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
entity key_schedule is |
port(clk : in std_logic; |
rst : in std_logic; |
|
load : in std_logic; |
start : in std_logic; |
|
key_in : in std_logic_vector(127 downto 0); |
|
key_ready : out std_logic; |
key_out : out std_logic_vector(127 downto 0)); |
end key_schedule; |
|
architecture Behavioral of key_schedule is |
signal w_3_i_s : std_logic_vector(31 downto 0); |
|
signal g_sub_0_s : std_logic_vector(7 downto 0); |
signal g_sub_1_s : std_logic_vector(7 downto 0); |
signal g_sub_2_s : std_logic_vector(7 downto 0); |
signal g_sub_3_s : std_logic_vector(7 downto 0); |
|
signal count_5 : natural range 0 to 5; |
signal count_10 : natural range 0 to 10; |
|
type type_RCON is array (0 to 9) of std_logic_vector(7 downto 0); |
constant rcon : type_RCON := (x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36"); |
|
begin |
mod_5_cnt : process(clk, rst, start) |
begin |
if rising_edge(clk) then |
if (rst = '1') then |
count_5 <= 0; |
elsif(start = '1') then |
if (count_5 = 4) then |
count_5 <= 0; |
else |
count_5 <= count_5 + 1; |
end if; |
end if; |
end if; |
end process mod_5_cnt; |
|
mod_10_cnt : process(clk, rst, start, count_5) |
begin |
if rising_edge(clk) then |
if (rst = '1') then |
count_10 <= 0; |
elsif(start = '1' and count_5 = 4) then |
if (count_10 = 9) then |
count_10 <= 0; |
else |
count_10 <= count_10 + 1; |
end if; |
end if; |
end if; |
end process mod_10_cnt; |
|
gen_sub_keys : process(clk, rst, start, count_5, count_10, load) |
variable w_0_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0'); |
variable w_1_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0'); |
variable w_2_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0'); |
variable w_3_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0'); |
|
variable tmp_0 : std_logic_vector(31 downto 0) := (others => '0'); |
variable tmp_1 : std_logic_vector(31 downto 0) := (others => '0'); |
variable tmp_2 : std_logic_vector(31 downto 0) := (others => '0'); |
variable tmp_3 : std_logic_vector(31 downto 0) := (others => '0'); |
begin |
if rising_edge(clk) then |
if (rst = '1') then |
w_0_i_tmp_old := (others => '0'); |
w_1_i_tmp_old := (others => '0'); |
w_2_i_tmp_old := (others => '0'); |
w_3_i_tmp_old := (others => '0'); |
elsif (load = '1') then |
w_0_i_tmp_old := key_in(31 downto 0); |
w_1_i_tmp_old := key_in(63 downto 32); |
w_2_i_tmp_old := key_in(95 downto 64); |
w_3_i_tmp_old := key_in(127 downto 96); |
elsif (start = '1') then |
if (count_5 = 1) then |
tmp_0 := w_0_i_tmp_old xor (g_sub_3_s & g_sub_2_s & g_sub_1_s & (g_sub_0_s xor rcon(count_10))); |
w_0_i_tmp_old := tmp_0; |
elsif (count_5 = 2) then |
tmp_1 := w_1_i_tmp_old xor w_0_i_tmp_old; |
w_1_i_tmp_old := tmp_1; |
elsif (count_5 = 3) then |
tmp_2 := w_2_i_tmp_old xor w_1_i_tmp_old; |
w_2_i_tmp_old := tmp_2; |
elsif (count_5 = 4) then |
tmp_3 := w_3_i_tmp_old xor w_2_i_tmp_old; |
w_3_i_tmp_old := tmp_3; |
end if; |
end if; |
end if; |
|
w_3_i_s <= w_3_i_tmp_old; |
|
key_out <= tmp_3 & tmp_2 & tmp_1 & tmp_0; |
|
end process; |
|
key_ready <= '1' when (count_5 = 1 and start = '1') else '0'; |
|
S_BOX_DUAL_1: entity work.dual_mem(rtl) port map (clk, '0', w_3_i_s(7 downto 0), w_3_i_s(15 downto 8), (others=>'0'), g_sub_3_s, g_sub_0_s); |
S_BOX_DUAL_2: entity work.dual_mem(rtl) port map (clk, '0', w_3_i_s(23 downto 16), w_3_i_s(31 downto 24), (others=>'0'), g_sub_1_s, g_sub_2_s); |
|
end Behavioral; |
/trunk/key_schedule/src/tb_key_schedule.vhd
0,0 → 1,117
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY tb_key_schedule IS |
END tb_key_schedule; |
|
ARCHITECTURE behavior OF tb_key_schedule IS |
|
COMPONENT key_schedule |
port(clk : in std_logic; |
rst : in std_logic; |
|
load : in std_logic; |
start : in std_logic; |
|
key_in : in std_logic_vector(127 downto 0); |
|
key_ready : out std_logic; |
key_out : out std_logic_vector(127 downto 0)); |
|
END COMPONENT; |
|
|
--Inputs |
|
signal clk : std_logic := '0'; |
signal rst : std_logic := '0'; |
signal load : std_logic := '0'; |
signal start : std_logic := '0'; |
signal key_in : std_logic_vector(127 downto 0); |
|
--Outputs |
|
signal key_ready : std_logic; |
signal key_out : std_logic_vector(127 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: key_schedule PORT MAP ( |
clk => clk, |
rst => rst, |
load => load, |
start => start, |
key_in => key_in, |
key_ready => key_ready, |
key_out => key_out); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
-- Stimulus process |
stim_proc: process |
begin |
|
wait for clk_period/2 + clk_period*2; |
rst <= '1'; |
|
wait for clk_period; |
rst <= '0'; |
load <= '1'; |
|
key_in <= X"0f0e0d0c0b0a09080706050403020100"; |
wait for clk_period; |
|
load <= '0'; |
start <= '1'; |
|
wait for 0.55 us; |
|
start <= '0'; |
|
wait for 1 us; |
rst <= '1'; |
|
wait for clk_period; |
rst <= '0'; |
key_in <= (others => '0'); |
load <= '1'; |
|
wait for clk_period + clk_period/2; |
|
load <= '0'; |
start <= '1'; |
|
wait for 0.55 us; |
start <= '0'; |
|
wait; |
end process; |
|
END; |
/trunk/key_schedule/synthesis/key_schedule.prj
0,0 → 1,2
../src/dual_mem.vhd |
../src/key_schedule.vhd |
/trunk/key_schedule/Makefile
0,0 → 1,14
DEVICE=xc6slx75-3csg484 |
|
all: sim |
|
sim_key: scripts/sim.do |
vsim -do scripts/sim.do |
syn_key: |
echo "run -ifn synthesis/key_schedule.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
clean: |
rm -rf transcript work vsim.wlf *.rlf *.vstf *~ *.xrpt *.ngc _xmsgs xst .lso |
|
|
|
/trunk/key_schedule/mem/key.mem
0,0 → 1,10
fe76abd6f178a6dafa72afd2fd74aad6 |
feb3306800c59bbef1bd3d640bcf92b6 |
41bf6904bf0c596cbfc9c2d24e74ffb6 |
fd8d05fdbc326cf9033e3595bcf7f747 |
aa22f6ad57aff350eb9d9fa9e8a3aa3c |
6b1fa30ac13d55a79692a6f77d0f395e |
26c0a94e4ddf0a448ce25fe31a70f914 |
d27abfaef4ba16e0b9651ca435874347 |
4e972cbe9ced9310685785f0d1329954 |
c5302b4d8ba707f3174a94e37f1d1113 |
/trunk/key_schedule/mem/s_box.mem
0,0 → 1,256
63 |
7c |
77 |
7b |
f2 |
6b |
6f |
c5 |
30 |
01 |
67 |
2b |
fe |
d7 |
ab |
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ca |
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c9 |
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fa |
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f0 |
ad |
d4 |
a2 |
af |
9c |
a4 |
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c0 |
b7 |
fd |
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26 |
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3f |
f7 |
cc |
34 |
a5 |
e5 |
f1 |
71 |
d8 |
31 |
15 |
04 |
c7 |
23 |
c3 |
18 |
96 |
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12 |
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e2 |
eb |
27 |
b2 |
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2c |
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1b |
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a0 |
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d6 |
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d1 |
00 |
ed |
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fc |
b1 |
5b |
6a |
cb |
be |
39 |
4a |
4c |
58 |
cf |
d0 |
ef |
aa |
fb |
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45 |
f9 |
02 |
7f |
50 |
3c |
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a3 |
40 |
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38 |
f5 |
bc |
b6 |
da |
21 |
10 |
ff |
f3 |
d2 |
cd |
0c |
13 |
ec |
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44 |
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c4 |
a7 |
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3d |
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60 |
81 |
4f |
dc |
22 |
2a |
90 |
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46 |
ee |
b8 |
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de |
5e |
0b |
db |
e0 |
32 |
3a |
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06 |
24 |
5c |
c2 |
d3 |
ac |
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e4 |
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37 |
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d5 |
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ba |
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b4 |
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dd |
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bd |
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b5 |
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48 |
03 |
f6 |
0e |
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35 |
57 |
b9 |
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c1 |
1d |
9e |
e1 |
f8 |
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11 |
69 |
d9 |
8e |
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9b |
1e |
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e9 |
ce |
55 |
28 |
df |
8c |
a1 |
89 |
0d |
bf |
e6 |
42 |
68 |
41 |
99 |
2d |
0f |
b0 |
54 |
bb |
16 |
/trunk/aes_c_1/scripts/aes_fsm_enc.do
0,0 → 1,43
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
|
vcom -explicit -93 "src/aes_lib.vhd" |
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/aes_enc.vhd" |
vcom -explicit -93 "src/aes_fsm_enc.vhd" |
vcom -explicit -93 "src/tb_aes_fsm_enc.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_aes_fsm_enc |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_2 |
|
mem load -infile mem/key.mem -format hex tb_aes_fsm_enc/uut/sub_keys_dram |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/state } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/block_out_s } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/count } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/key_data_1 } \ |
{sim:/tb_aes_fsm_enc/uut/key_data_2 } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/aes_round_n/sub_key } |
|
run 10 us |
|
/trunk/aes_c_1/scripts/aes_enc.do
0,0 → 1,30
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
vcom -explicit -93 "src/aes_lib.vhd" |
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/tb_pr_dual_mem.vhd" |
vcom -explicit -93 "src/aes_enc.vhd" |
vcom -explicit -93 "src/tb_aes_enc.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_aes_enc |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_2 |
|
run 50 us |
|
add wave \ |
{sim:/tb_aes_enc/uut/key_reg } |
/trunk/aes_c_1/src/tb_aes_enc.vhd
0,0 → 1,117
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY tb_aes_enc IS |
END tb_aes_enc; |
|
ARCHITECTURE behavior OF tb_aes_enc IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT aes_enc |
PORT( |
clk : IN std_logic; |
rst : IN std_logic; |
block_in : IN std_logic_vector(127 downto 0); |
sub_key : IN std_logic_vector(127 downto 0); |
load : IN std_logic; |
enc : IN std_logic; |
last : IN std_logic; |
|
block_out : OUT std_logic_vector(127 downto 0)); |
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal rst : std_logic := '0'; |
signal block_in : std_logic_vector(127 downto 0) := (others => '0'); |
signal sub_key : std_logic_vector(127 downto 0) := (others=> '0'); |
signal load : std_logic := '0'; |
signal enc : std_logic := '0'; |
signal last : std_logic := '0'; |
|
--Outputs |
signal block_out : std_logic_vector(127 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: aes_enc PORT MAP ( |
clk => clk, |
rst => rst, |
block_in => block_in, |
sub_key => sub_key, |
load => load, |
enc => enc, |
last => last, |
block_out => block_out); |
|
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
|
wait for clk_period/2 + clk_period*2; |
rst <= '1'; |
|
wait for clk_period; |
rst <= '0'; |
load <= '1'; |
|
block_in <= X"5b75966825a9e32f5b7c424c37f6652b"; |
sub_key <= X"41bf6904bf0c596cbfc9c2d24e74ffb6"; |
|
wait for clk_period; |
|
load <= '0'; |
enc <= '1'; |
|
wait for clk_period; |
|
wait for clk_period; |
|
wait for clk_period; |
|
load <= '1'; |
|
block_in <= X"add6b976204688966765efb4cb5f01d1"; |
sub_key <= X"fd8d05fdbc326cf9033e3595bcf7f747"; |
|
wait for clk_period; |
|
load <= '0'; |
enc <= '1'; |
|
wait; |
end process; |
|
END; |
/trunk/aes_c_1/src/aes_fsm_enc.vhd
0,0 → 1,228
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library IEEE; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
use ieee.numeric_std.all; |
|
use work.aes_lib.all; |
|
entity aes_fsm_enc is |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
key : in std_logic_vector(127 downto 0); |
enc : in std_logic; |
|
block_out : out std_logic_vector(127 downto 0); |
block_ready : out std_logic); |
end aes_fsm_enc; |
|
architecture Behavioral of aes_fsm_enc is |
|
type state_type is (idle, n_round_1, n_round_2, n_round_3, n_round_4, n_round_5, n_round_6, last_round_1, |
last_round_2, last_round_3, last_round_4, last_round_5, last_round_6, pre); |
|
signal state, next_state: state_type ; |
signal block_in_s : std_logic_vector(127 downto 0); |
signal sub_key_s : std_logic_vector(127 downto 0); |
signal load_s : std_logic; |
signal enc_s : std_logic; |
signal last_s, rst_cnt : std_logic; |
signal block_out_s : std_logic_vector(127 downto 0); |
signal count: natural range 0 to 10; |
signal en_cnt : std_logic; |
|
signal key_addr_1, key_addr_2 : std_logic_vector(3 downto 0); |
signal key_data_1, key_data_delay_1, key_data_2, key_data_delay_2 : std_logic_vector(127 downto 0); |
|
begin |
|
process1: process (clk,rst) |
begin |
if (rst ='1') then |
state <= idle; |
elsif rising_edge(clk) then |
state <= next_state; |
end if; |
end process process1; |
|
process2 : process (state, enc, block_in, key, block_out_s) |
variable block_reg_v : std_logic_vector(127 downto 0); |
begin |
next_state <= state; |
|
block_reg_v := (others => '0'); |
block_in_s <= (others => '0'); |
|
sub_key_s <= (others => '0'); |
|
enc_s <= '0'; |
load_s <= '0'; |
last_s <= '0'; |
block_ready <= '0'; |
|
case state is |
when idle => |
if enc ='1' then |
next_state <= pre; |
else |
next_state <= idle; |
end if; |
when pre => |
rst_cnt <= '0'; |
|
for i in 0 to 127 loop |
block_reg_v(i) := block_in(i) xor key(i); |
end loop; |
|
load_s <= '1'; |
enc_s <= '0'; |
|
sub_key_s <= key_data_1; |
block_in_s <= block_reg_v; |
|
next_state <= n_round_1; |
when n_round_1 => |
enc_s <= '1'; |
load_s <= '0'; |
|
next_state <= n_round_2; |
|
when n_round_2 => |
enc_s <= '1'; |
load_s <= '0'; |
|
next_state <= n_round_3; |
when n_round_3 => |
enc_s <= '1'; |
load_s <= '0'; |
|
next_state <= n_round_4; |
when n_round_4 => |
|
enc_s <= '1'; |
load_s <= '0'; |
|
next_state <= n_round_5; |
when n_round_5 => |
enc_s <= '1'; |
load_s <= '0'; |
|
next_state <= n_round_6; |
when n_round_6 => |
enc_s <= '1'; |
load_s <= '1'; |
|
sub_key_s <= key_data_1; |
block_in_s <= block_out_s; |
|
if count = 9 then |
next_state <= last_round_1; |
else |
next_state <= n_round_1; |
end if; |
when last_round_1 => |
enc_s <= '1'; |
load_s <= '0'; |
last_s <= '1'; |
|
next_state <= last_round_2; |
when last_round_2 => |
enc_s <= '1'; |
load_s <= '0'; |
last_s <= '1'; |
|
next_state <= last_round_3; |
when last_round_3 => |
enc_s <= '1'; |
load_s <= '0'; |
last_s <= '1'; |
|
next_state <= last_round_4; |
when last_round_4 => |
enc_s <= '1'; |
load_s <= '0'; |
last_s <= '1'; |
|
next_state <= last_round_5; |
when last_round_5 => |
enc_s <= '1'; |
load_s <= '0'; |
last_s <= '1'; |
|
rst_cnt <= '1'; |
next_state <= last_round_6; |
when last_round_6 => |
enc_s <= '1'; |
load_s <= '0'; |
last_s <= '1'; |
|
block_ready <= '1'; |
|
rst_cnt <= '0'; |
next_state <= idle; |
end case; |
|
end process process2; |
|
mod_10_cnt : process(clk, rst_cnt) |
begin |
if rising_edge(clk) then |
if (rst_cnt = '1') then |
count <= 0; |
elsif(en_cnt = '1' and state = n_round_1) then |
if (count = 9) then |
count <= 0; |
else |
count <= count + 1; |
end if; |
end if; |
end if; |
end process mod_10_cnt; |
|
en_cnt <= '1'; |
|
AES_ROUND_N : entity work.aes_enc(Behavioral) port map (clk, |
rst, |
block_in_s, |
sub_key_s, |
load_s, |
enc_s, |
last_s, |
block_out_s); |
|
SUB_KEYS_DRAM : entity work.dual_mem(rtl) generic map (4, 128, 10) |
port map (clk, |
'0', |
key_addr_1, |
key_addr_2, |
(others => '0'), |
key_data_1, |
key_data_2); |
|
|
|
key_addr_1 <= std_logic_vector(to_unsigned(count, key_addr_1'length)); |
key_addr_2 <= std_logic_vector(to_unsigned(count, key_addr_2'length)); |
|
block_out <= block_out_s; |
|
end Behavioral; |
|
/trunk/aes_c_1/src/dual_mem.vhd
0,0 → 1,57
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity dual_mem is |
generic (ADDR_LENGTH : integer := 8; |
DATA_LENGTH : integer := 8; |
N_ADDR : integer := 256); |
port (clk : in std_logic; |
we : in std_logic; |
a : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
di : in std_logic_vector(DATA_LENGTH - 1 downto 0); |
spo : out std_logic_vector(DATA_LENGTH - 1 downto 0); |
dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0)); |
end dual_mem; |
|
architecture rtl of dual_mem is |
type ram_type is array (N_ADDR - 1 downto 0) |
of std_logic_vector (DATA_LENGTH - 1 downto 0); |
signal RAM : ram_type; |
signal read_a : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
signal read_dpra : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
|
attribute ram_style: string; |
attribute ram_style of RAM: signal is "block"; |
|
begin |
process (clk) |
begin |
if rising_edge(clk) then |
if (we = '1') then |
RAM(conv_integer(a)) <= di; |
end if; |
read_a <= a; |
read_dpra <= dpra; |
end if; |
end process; |
|
spo <= RAM(conv_integer(read_a)); |
dpo <= RAM(conv_integer(read_dpra)); |
end rtl; |
/trunk/aes_c_1/src/tb_aes_fsm_enc.vhd
0,0 → 1,113
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY tb_aes_fsm_enc IS |
END tb_aes_fsm_enc; |
|
ARCHITECTURE behavior OF tb_aes_fsm_enc IS |
|
COMPONENT aes_fsm_enc |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
key : in std_logic_vector(127 downto 0); |
enc : in std_logic; |
|
block_out : out std_logic_vector(127 downto 0); |
block_ready : out std_logic); |
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal rst : std_logic := '0'; |
signal block_in : std_logic_vector(127 downto 0) := (others => '0'); |
signal key : std_logic_vector(127 downto 0) := (others=> '0'); |
signal enc : std_logic := '0'; |
|
--Outputs |
signal block_out : std_logic_vector(127 downto 0); |
signal block_ready : std_logic; |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: aes_fsm_enc PORT MAP ( |
clk => clk, |
rst => rst, |
block_in => block_in, |
key => key, |
enc => enc, |
block_out => block_out, |
block_ready => block_ready); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
|
wait for clk_period/2 + clk_period*2; |
rst <= '1'; |
|
wait for clk_period; |
rst <= '0'; |
enc <= '1'; |
|
block_in <= X"0f0e0d0c0b0a09080706050403020100"; |
key <= X"0f0e0d0c0b0a09080706050403020100"; |
|
wait for 0.62*2 us; |
|
enc <= '0'; |
|
wait for 1.73 us; |
|
enc <= '1'; |
|
block_in <= X"0f0e0d0c0b0a09080706050403020100"; |
key <= X"0f0e0d0c0b0a09080706050403020100"; |
|
wait for 0.62 us; |
|
enc <= '0'; |
|
wait for 2.73 us; |
|
enc <= '1'; |
|
block_in <= X"0f0e0d0c0b0a09080706050403020100"; |
key <= X"0f0e0d0c0b0a09080706050403020100"; |
|
|
|
wait; |
end process; |
|
END; |
/trunk/aes_c_1/src/aes_enc.vhd
0,0 → 1,140
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library IEEE; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
use work.aes_lib.all; |
|
entity aes_enc is |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
sub_key : in std_logic_vector(127 downto 0); |
load : in std_logic; |
enc : in std_logic; |
last : in std_logic; |
|
block_out : out std_logic_vector(127 downto 0)); |
end aes_enc; |
|
architecture Behavioral of aes_enc is |
signal reg: std_logic_vector(127 downto 0); |
signal key_reg_delayed: std_logic_vector(127 downto 0); |
|
signal sub_tmp_0 : std_logic_vector(7 downto 0); |
signal sub_tmp_1 : std_logic_vector(7 downto 0); |
signal sub_tmp_2 : std_logic_vector(7 downto 0); |
signal sub_tmp_3 : std_logic_vector(7 downto 0); |
|
signal sub_tmp_mix_0 : std_logic_vector(7 downto 0); |
signal sub_tmp_mix_1 : std_logic_vector(7 downto 0); |
signal sub_tmp_mix_2 : std_logic_vector(7 downto 0); |
signal sub_tmp_mix_3 : std_logic_vector(7 downto 0); |
|
signal sub_tmp_key_0 : std_logic_vector(7 downto 0); |
signal sub_tmp_key_1 : std_logic_vector(7 downto 0); |
signal sub_tmp_key_2 : std_logic_vector(7 downto 0); |
signal sub_tmp_key_3 : std_logic_vector(7 downto 0); |
|
signal key_reg : std_logic_vector(127 downto 0); |
begin |
|
S_BOX_DUAL_1: entity work.dual_mem(rtl) port map (clk, '0', reg(7 downto 0), reg(15 downto 8), (others=>'0'), sub_tmp_0, sub_tmp_1); |
S_BOX_DUAL_2: entity work.dual_mem(rtl) port map (clk, '0', reg(23 downto 16), reg(31 downto 24), (others=>'0'), sub_tmp_2, sub_tmp_3); |
|
|
sum_proc_1: process(clk, rst, block_in, sub_key) |
variable reg_v : std_logic_vector(127 downto 0); |
variable key_reg_v : std_logic_vector(127 downto 0); |
begin |
if rising_edge(clk) then |
if rst = '1' then |
reg_v := (others=>'0'); |
key_reg_v := (others=>'0'); |
elsif load = '1' then |
|
|
-- The current state is arranged to: |
-- { 0,5,a,f; 4,9,e,3; 8,d,2,7; c,1,6,b; } as |
-- Gaj & Chodowiec describe in "FPGA and ASIC Implementations of AES" from |
-- Cryptographic Engineering, Çetin Kaya Koç, Springer, 2009. |
|
reg_v := block_in(95 downto 88) & block_in(55 downto 48) & block_in(15 downto 8) & block_in(103 downto 96) & -- (b,6,1,c) |
block_in(63 downto 56) & block_in(23 downto 16) & block_in(111 downto 104) & block_in(71 downto 64) & -- (7,2,d,8) |
block_in(31 downto 24) & block_in(119 downto 112) & block_in(79 downto 72) & block_in(39 downto 32) & -- (3,e,9,4) |
block_in(127 downto 120) & block_in(87 downto 80) & block_in(47 downto 40) & block_in(7 downto 0); -- (f,a,5,0) |
|
key_reg_v := sub_key; |
elsif enc = '1' then |
reg_v := to_stdlogicvector(to_bitvector(reg_v) ror 32); |
key_reg_v := to_stdlogicvector(to_bitvector(key_reg_v) ror 32); |
end if; |
end if; |
|
reg <= reg_v; |
key_reg <= key_reg_v; |
|
end process; |
|
MIX_COL: process(sub_tmp_0, sub_tmp_1, sub_tmp_2, sub_tmp_3, last) |
begin |
if last = '0' then |
sub_tmp_mix_0 <= gfmult2(sub_tmp_0) xor gfmult3(sub_tmp_1) xor sub_tmp_2 xor sub_tmp_3; |
sub_tmp_mix_1 <= sub_tmp_0 xor gfmult2(sub_tmp_1) xor gfmult3(sub_tmp_2) xor sub_tmp_3; |
sub_tmp_mix_2 <= sub_tmp_0 xor sub_tmp_1 xor gfmult2(sub_tmp_2) xor gfmult3(sub_tmp_3); |
sub_tmp_mix_3 <= gfmult3(sub_tmp_0) xor sub_tmp_1 xor sub_tmp_2 xor gfmult2(sub_tmp_3); |
else |
sub_tmp_mix_0 <= sub_tmp_0; |
sub_tmp_mix_1 <= sub_tmp_1; |
sub_tmp_mix_2 <= sub_tmp_2; |
sub_tmp_mix_3 <= sub_tmp_3; |
end if; |
end process; |
|
ADD_KEY: process(key_reg_delayed, sub_tmp_mix_0, sub_tmp_mix_1, sub_tmp_mix_2, sub_tmp_mix_3) |
begin |
sub_tmp_key_0 <= sub_tmp_mix_0 xor key_reg_delayed(7 downto 0); |
sub_tmp_key_1 <= sub_tmp_mix_1 xor key_reg_delayed(15 downto 8); |
sub_tmp_key_2 <= sub_tmp_mix_2 xor key_reg_delayed(23 downto 16); |
sub_tmp_key_3 <= sub_tmp_mix_3 xor key_reg_delayed(31 downto 24); |
end process; |
|
FF_DELAY: process(clk, key_reg) |
begin |
if rising_edge(clk) then |
key_reg_delayed <= key_reg; |
end if; |
end process; |
|
gen_output: process(enc, clk, sub_tmp_key_0, sub_tmp_key_1, sub_tmp_key_2, sub_tmp_key_3) |
variable out_buffer_v : std_logic_vector(127 downto 0); |
begin |
if rising_edge(clk) then |
if enc = '1' then |
out_buffer_v := out_buffer_v(127 downto 32) & sub_tmp_key_3 & sub_tmp_key_2 & sub_tmp_key_1 & sub_tmp_key_0; |
out_buffer_v := to_stdlogicvector(to_bitvector(out_buffer_v) ror 32); |
end if; |
end if; |
|
block_out <= out_buffer_v; |
|
end process; |
|
end Behavioral; |
|
/trunk/aes_c_1/src/aes_lib.vhd
0,0 → 1,45
|
-- Two Galois multiplication functions based on http://www.isaakian.com/VHDL/AES/. |
|
library ieee; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
|
package aes_lib is |
|
function gfmult2 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector; |
|
function gfmult3 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector; |
|
|
end aes_lib; |
|
|
package body aes_lib is |
|
function gfmult2 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector is |
variable result : std_logic_vector(7 downto 0); |
begin |
result := (I(6 downto 0) & '0') xor (x"1B" and ("000" & I(7)& I(7) & "0" & I(7)& I(7))); |
return result; |
end gfmult2; |
|
function gfmult3 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector is |
variable result : std_logic_vector(7 downto 0); |
begin |
result := gfmult2(I) xor I; |
return result; |
end gfmult3; |
|
end aes_lib; |
/trunk/aes_c_1/synthesis/aes_enc.prj
0,0 → 1,3
../src/aes_lib.vhd |
../src/dual_mem.vhd |
../src/aes_enc.vhd |
/trunk/aes_c_1/synthesis/aes_fsm_enc.prj
0,0 → 1,4
../src/aes_lib.vhd |
../src/dual_mem.vhd |
../src/aes_enc.vhd |
../src/aes_fsm_enc.vhd |
/trunk/aes_c_1/Makefile
0,0 → 1,19
DEVICE=xc6slx75-3csg484 |
|
sim_aes: scripts/aes_enc.do |
vsim -do scripts/aes_enc.do |
|
sim_aes_fsm: scripts/aes_fsm_enc.do |
vsim -do scripts/aes_fsm_enc.do |
|
syn_aes: |
echo "run -ifn synthesis/aes_enc.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
syn_aes_fsm: |
echo "run -ifn synthesis/aes_fsm_enc.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
clean: |
rm -rf transcript work vsim.wlf *.rlf *.vstf *~ *.xrpt *.ngc _xmsgs xst .lso |
|
|
|
/trunk/aes_c_1/mem/key.mem
0,0 → 1,10
fe76abd6f178a6dafa72afd2fd74aad6 |
feb3306800c59bbef1bd3d640bcf92b6 |
41bf6904bf0c596cbfc9c2d24e74ffb6 |
fd8d05fdbc326cf9033e3595bcf7f747 |
aa22f6ad57aff350eb9d9fa9e8a3aa3c |
6b1fa30ac13d55a79692a6f77d0f395e |
26c0a94e4ddf0a448ce25fe31a70f914 |
d27abfaef4ba16e0b9651ca435874347 |
4e972cbe9ced9310685785f0d1329954 |
c5302b4d8ba707f3174a94e37f1d1113 |
/trunk/aes_c_1/mem/s_box.mem
0,0 → 1,256
63 |
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e4 |
79 |
e7 |
c8 |
37 |
6d |
8d |
d5 |
4e |
a9 |
6c |
56 |
f4 |
ea |
65 |
7a |
ae |
08 |
ba |
78 |
25 |
2e |
1c |
a6 |
b4 |
c6 |
e8 |
dd |
74 |
1f |
4b |
bd |
8b |
8a |
70 |
3e |
b5 |
66 |
48 |
03 |
f6 |
0e |
61 |
35 |
57 |
b9 |
86 |
c1 |
1d |
9e |
e1 |
f8 |
98 |
11 |
69 |
d9 |
8e |
94 |
9b |
1e |
87 |
e9 |
ce |
55 |
28 |
df |
8c |
a1 |
89 |
0d |
bf |
e6 |
42 |
68 |
41 |
99 |
2d |
0f |
b0 |
54 |
bb |
16 |
/trunk/aes_c_2/scripts/aes_fsm_enc.do
0,0 → 1,52
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
|
vcom -explicit -93 "src/aes_lib.vhd" |
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/aes_enc.vhd" |
vcom -explicit -93 "src/aes_fsm_enc.vhd" |
vcom -explicit -93 "src/tb_aes_fsm_enc.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_aes_fsm_enc |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_2 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_3 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_4 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_5 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_6 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_7 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_8 |
|
mem load -infile mem/key.mem -format hex tb_aes_fsm_enc/uut/sub_keys_dram |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/state } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/block_out_s } |
|
add wave sim:/tb_aes_fsm_enc/uut/aes_round_n/* |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/key_addr_1 } \ |
{sim:/tb_aes_fsm_enc/uut/key_data_1 } \ |
{sim:/tb_aes_fsm_enc/uut/key_data_2 } \ |
{sim:/tb_aes_fsm_enc/uut/count } |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/clk_div_2 } |
|
run 10 us |
|
/trunk/aes_c_2/scripts/aes_enc.do
0,0 → 1,39
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
vcom -explicit -93 "src/aes_lib.vhd" |
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/tb_pr_dual_mem.vhd" |
vcom -explicit -93 "src/aes_enc.vhd" |
vcom -explicit -93 "src/tb_aes_enc.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_aes_enc |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_2 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_3 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_4 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_5 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_6 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_7 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_8 |
|
add wave \ |
{sim:/tb_aes_enc/uut/sub_tmp_s } |
|
run 50 us |
|
add wave \ |
{sim:/tb_aes_enc/uut/key_reg } |
/trunk/aes_c_2/src/tb_aes_enc.vhd
0,0 → 1,94
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY tb_aes_enc IS |
END tb_aes_enc; |
|
ARCHITECTURE behavior OF tb_aes_enc IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT aes_enc |
PORT( |
clk : IN std_logic; |
block_in : IN std_logic_vector(127 downto 0); |
sub_key : IN std_logic_vector(127 downto 0); |
last : IN std_logic; |
|
block_out : OUT std_logic_vector(127 downto 0)); |
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal block_in : std_logic_vector(127 downto 0) := (others => '0'); |
signal sub_key : std_logic_vector(127 downto 0) := (others=> '0'); |
signal last : std_logic := '0'; |
|
--Outputs |
signal block_out : std_logic_vector(127 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: aes_enc PORT MAP ( |
clk => clk, |
block_in => block_in, |
sub_key => sub_key, |
last => last, |
block_out => block_out); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
|
wait for clk_period/2 + clk_period*2; |
|
block_in <= X"5b75966825a9e32f5b7c424c37f6652b"; |
sub_key <= X"41bf6904bf0c596cbfc9c2d24e74ffb6"; |
|
wait for clk_period; |
|
assert block_out = X"add6b976204688966765efb4cb5f01d1" |
report "Stage 1 encryption FAILED" severity FAILURE; |
|
block_in <= X"add6b976204688966765efb4cb5f01d1"; |
sub_key <= X"fd8d05fdbc326cf9033e3595bcf7f747"; |
|
wait for clk_period; |
|
assert block_out = X"f191a5f39fe59f7283a1352a4a06178e" |
report "Stage 2 encryption FAILED" severity FAILURE; |
|
wait; |
end process; |
|
END; |
/trunk/aes_c_2/src/aes_fsm_enc.vhd
0,0 → 1,184
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library IEEE; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
use ieee.numeric_std.all; |
|
use work.aes_lib.all; |
|
entity aes_fsm_enc is |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
key : in std_logic_vector(127 downto 0); |
enc : in std_logic; |
block_out : out std_logic_vector(127 downto 0); |
block_ready : out std_logic); |
end aes_fsm_enc; |
|
architecture Behavioral of aes_fsm_enc is |
|
attribute buffer_type: string; |
|
type state_type is (idle, n_round_1, n_round_2, reinit, pre, all_reset); |
|
signal state, next_state: state_type ; |
signal block_in_s : std_logic_vector(127 downto 0); |
signal sub_key_s : std_logic_vector(127 downto 0); |
signal last_s : std_logic; |
signal block_out_s : std_logic_vector(127 downto 0); |
|
signal key_addr_1, key_addr_2 : std_logic_vector(3 downto 0); |
signal key_data_1, key_data_delay_1, key_data_2, key_data_delay_2 : std_logic_vector(127 downto 0); |
|
signal count: natural range 0 to 10; |
signal en_cnt : std_logic; |
signal clk_div_2, rst_div, rst_cnt : std_logic; |
|
attribute buffer_type of clk_div_2: signal is "bufg"; |
|
begin |
|
process1: process (clk,rst) |
begin |
if (rst ='1') then |
state <= idle; |
elsif rising_edge(clk) then |
state <= next_state; |
end if; |
end process process1; |
|
process2 : process (state, enc, block_in, key) |
begin |
next_state <= state; |
|
last_s <= '0'; |
block_in_s <= (others => '0'); |
sub_key_s <= (others => '0'); |
block_ready <= '0'; |
|
rst_div <= '0'; |
rst_cnt <= '0'; |
|
en_cnt <= '0'; |
|
case state is |
when idle => |
if enc ='1' then |
rst_div <= '1'; |
rst_cnt <= '1'; |
|
next_state <= all_reset; |
else |
next_state <= idle; |
end if; |
when all_reset => |
rst_div <= '0'; |
rst_cnt <= '0'; |
|
en_cnt <= '1'; |
|
next_state <= pre; |
when pre => |
|
en_cnt <= '1'; |
|
sub_key_s <= key_data_1; |
block_in_s <= block_in xor key; |
|
next_state <= n_round_1; |
when n_round_1 => |
en_cnt <= '1'; |
|
sub_key_s <= key_data_1; |
last_s <= '0'; |
block_in_s <= block_out_s; |
|
next_state <= n_round_2; |
when n_round_2 => |
en_cnt <= '1'; |
|
sub_key_s <= key_data_1; |
block_in_s <= block_out_s; |
|
if count = 9 then |
last_s <= '1'; |
block_ready <= '1'; |
|
next_state <= reinit; |
else |
last_s <= '0'; |
next_state <= n_round_1; |
end if; |
when reinit => |
en_cnt <= '0'; |
|
next_state <= idle; |
end case; |
|
end process process2; |
|
|
mod_10_cnt : process(clk_div_2, rst_cnt) |
begin |
if rising_edge(clk_div_2) then |
if (rst_cnt = '1') then |
count <= 0; |
elsif(en_cnt = '1') then |
if (count = 9) then |
count <= 0; |
else |
count <= count + 1; |
end if; |
end if; |
end if; |
end process mod_10_cnt; |
|
key_addr_1 <= std_logic_vector(to_unsigned(count, key_addr_1'length)); |
key_addr_2 <= std_logic_vector(to_unsigned(count, key_addr_2'length)); |
|
AES_ROUND_N : entity work.aes_enc(Behavioral) port map (clk, |
block_in_s, |
sub_key_s, |
last_s, |
block_out_s); |
|
SUB_KEYS_DRAM : entity work.dual_mem(rtl) generic map (4, 128, 10) |
port map (clk, |
'0', |
key_addr_1, |
key_addr_2, |
(others => '0'), |
key_data_1, |
key_data_2); |
clk_div : process(clk, rst_div) |
begin |
if rising_edge(clk) then |
if rst_div = '1' then |
clk_div_2 <= '0'; |
else |
clk_div_2 <= not(clk_div_2); |
end if; |
end if; |
end process; |
|
block_out <= block_out_s; |
|
end Behavioral; |
|
/trunk/aes_c_2/src/dual_mem.vhd
0,0 → 1,57
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity dual_mem is |
generic (ADDR_LENGTH : integer := 8; |
DATA_LENGTH : integer := 8; |
N_ADDR : integer := 256); |
port (clk : in std_logic; |
we : in std_logic; |
a : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
di : in std_logic_vector(DATA_LENGTH - 1 downto 0); |
spo : out std_logic_vector(DATA_LENGTH - 1 downto 0); |
dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0)); |
end dual_mem; |
|
architecture rtl of dual_mem is |
type ram_type is array (N_ADDR - 1 downto 0) |
of std_logic_vector (DATA_LENGTH - 1 downto 0); |
signal RAM : ram_type; |
signal read_a : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
signal read_dpra : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
|
attribute ram_style: string; |
attribute ram_style of RAM: signal is "block"; |
|
begin |
process (clk) |
begin |
if rising_edge(clk) then |
if (we = '1') then |
RAM(conv_integer(a)) <= di; |
end if; |
read_a <= a; |
read_dpra <= dpra; |
end if; |
end process; |
|
spo <= RAM(conv_integer(read_a)); |
dpo <= RAM(conv_integer(read_dpra)); |
end rtl; |
/trunk/aes_c_2/src/tb_aes_fsm_enc.vhd
0,0 → 1,105
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
ENTITY tb_aes_fsm_enc IS |
END tb_aes_fsm_enc; |
|
ARCHITECTURE behavior OF tb_aes_fsm_enc IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT aes_fsm_enc |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
key : in std_logic_vector(127 downto 0); |
enc : in std_logic; |
block_out : out std_logic_vector(127 downto 0); |
block_ready : out std_logic); |
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal rst : std_logic := '0'; |
signal block_in : std_logic_vector(127 downto 0) := (others => '0'); |
signal key : std_logic_vector(127 downto 0) := (others=> '0'); |
signal enc : std_logic := '0'; |
|
--Outputs |
signal block_out : std_logic_vector(127 downto 0); |
signal block_ready : std_logic; |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: aes_fsm_enc PORT MAP ( |
clk => clk, |
rst => rst, |
block_in => block_in, |
key => key, |
enc => enc, |
block_out => block_out, |
block_ready => block_ready); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
|
wait for clk_period/2 + clk_period*2; |
rst <= '1'; |
|
wait for clk_period; |
rst <= '0'; |
enc <= '1'; |
|
block_in <= X"0f0e0d0c0b0a09080706050403020100"; |
key <= X"0f0e0d0c0b0a09080706050403020100"; |
|
wait for 0.815 us; |
enc <= '0'; |
|
wait for 2 us; |
|
enc <= '1'; |
|
wait for 0.195 us; |
|
enc <= '0'; |
|
wait for 1.23 us; |
|
enc <= '1'; |
|
wait; |
end process; |
|
END; |
/trunk/aes_c_2/src/aes_enc.vhd
0,0 → 1,81
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library IEEE; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
use work.aes_lib.all; |
|
entity aes_enc is |
port( clk: in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
sub_key : in std_logic_vector(127 downto 0); |
last : in std_logic; |
block_out : out std_logic_vector(127 downto 0)); |
end aes_enc; |
|
architecture Behavioral of aes_enc is |
|
signal sub_tmp_s : std_logic_vector(127 downto 0); |
signal sub_tmp_mix : std_logic_vector(127 downto 0); |
|
begin |
|
S_BOX_DUAL_1: entity work.dual_mem(rtl) port map (clk, '0', block_in(7 downto 0), block_in(47 downto 40), (others=>'0'), sub_tmp_s(7 downto 0), sub_tmp_s(15 downto 8)); |
S_BOX_DUAL_2: entity work.dual_mem(rtl) port map (clk, '0', block_in(87 downto 80), block_in(127 downto 120), (others=>'0'), sub_tmp_s(23 downto 16), sub_tmp_s(31 downto 24)); |
S_BOX_DUAL_3: entity work.dual_mem(rtl) port map (clk, '0', block_in(39 downto 32), block_in(79 downto 72), (others=>'0'), sub_tmp_s(39 downto 32), sub_tmp_s(47 downto 40)); |
S_BOX_DUAL_4: entity work.dual_mem(rtl) port map (clk, '0', block_in(119 downto 112), block_in(31 downto 24), (others=>'0'), sub_tmp_s(55 downto 48), sub_tmp_s(63 downto 56)); |
S_BOX_DUAL_5: entity work.dual_mem(rtl) port map (clk, '0', block_in(71 downto 64), block_in(111 downto 104), (others=>'0'), sub_tmp_s(71 downto 64), sub_tmp_s(79 downto 72)); |
S_BOX_DUAL_6: entity work.dual_mem(rtl) port map (clk, '0', block_in(23 downto 16), block_in(63 downto 56), (others=>'0'), sub_tmp_s(87 downto 80), sub_tmp_s(95 downto 88)); |
S_BOX_DUAL_7: entity work.dual_mem(rtl) port map (clk, '0', block_in(103 downto 96), block_in(15 downto 8), (others=>'0'), sub_tmp_s(103 downto 96), sub_tmp_s(111 downto 104)); |
S_BOX_DUAL_8: entity work.dual_mem(rtl) port map (clk, '0', block_in(55 downto 48), block_in(95 downto 88), (others=>'0'), sub_tmp_s(119 downto 112), sub_tmp_s(127 downto 120)); |
|
MIX_COL: process(sub_tmp_s, last) |
begin |
if last = '0' then |
|
sub_tmp_mix(7 downto 0) <= gfmult2(sub_tmp_s(7 downto 0)) xor gfmult3(sub_tmp_s(15 downto 8)) xor sub_tmp_s(23 downto 16) xor sub_tmp_s(31 downto 24); |
sub_tmp_mix(15 downto 8) <= sub_tmp_s(7 downto 0) xor gfmult2(sub_tmp_s(15 downto 8)) xor gfmult3(sub_tmp_s(23 downto 16)) xor sub_tmp_s(31 downto 24); |
sub_tmp_mix(23 downto 16) <= sub_tmp_s(7 downto 0) xor sub_tmp_s(15 downto 8) xor gfmult2(sub_tmp_s(23 downto 16)) xor gfmult3(sub_tmp_s(31 downto 24)); |
sub_tmp_mix(31 downto 24) <= gfmult3(sub_tmp_s(7 downto 0)) xor sub_tmp_s(15 downto 8) xor sub_tmp_s(23 downto 16) xor gfmult2(sub_tmp_s(31 downto 24)); |
|
sub_tmp_mix(39 downto 32) <= gfmult2(sub_tmp_s(39 downto 32)) xor gfmult3(sub_tmp_s(47 downto 40)) xor sub_tmp_s(55 downto 48) xor sub_tmp_s(63 downto 56); |
sub_tmp_mix(47 downto 40) <= sub_tmp_s(39 downto 32) xor gfmult2(sub_tmp_s(47 downto 40)) xor gfmult3(sub_tmp_s(55 downto 48)) xor sub_tmp_s(63 downto 56); |
sub_tmp_mix(55 downto 48) <= sub_tmp_s(39 downto 32) xor sub_tmp_s(47 downto 40) xor gfmult2(sub_tmp_s(55 downto 48)) xor gfmult3(sub_tmp_s(63 downto 56)); |
sub_tmp_mix(63 downto 56) <= gfmult3(sub_tmp_s(39 downto 32)) xor sub_tmp_s(47 downto 40) xor sub_tmp_s(55 downto 48) xor gfmult2(sub_tmp_s(63 downto 56)); |
|
sub_tmp_mix(71 downto 64) <= gfmult2(sub_tmp_s(71 downto 64)) xor gfmult3(sub_tmp_s(79 downto 72)) xor sub_tmp_s(87 downto 80) xor sub_tmp_s(95 downto 88); |
sub_tmp_mix(79 downto 72) <= sub_tmp_s(71 downto 64) xor gfmult2(sub_tmp_s(79 downto 72)) xor gfmult3(sub_tmp_s(87 downto 80)) xor sub_tmp_s(95 downto 88); |
sub_tmp_mix(87 downto 80) <= sub_tmp_s(71 downto 64) xor sub_tmp_s(79 downto 72) xor gfmult2(sub_tmp_s(87 downto 80)) xor gfmult3(sub_tmp_s(95 downto 88)); |
sub_tmp_mix(95 downto 88) <= gfmult3(sub_tmp_s(71 downto 64)) xor sub_tmp_s(79 downto 72) xor sub_tmp_s(87 downto 80) xor gfmult2(sub_tmp_s(95 downto 88)); |
|
sub_tmp_mix(103 downto 96) <= gfmult2(sub_tmp_s(103 downto 96)) xor gfmult3(sub_tmp_s(111 downto 104)) xor sub_tmp_s(119 downto 112) xor sub_tmp_s(127 downto 120); |
sub_tmp_mix(111 downto 104) <= sub_tmp_s(103 downto 96) xor gfmult2(sub_tmp_s(111 downto 104)) xor gfmult3(sub_tmp_s(119 downto 112)) xor sub_tmp_s(127 downto 120); |
sub_tmp_mix(119 downto 112) <= sub_tmp_s(103 downto 96) xor sub_tmp_s(111 downto 104) xor gfmult2(sub_tmp_s(119 downto 112)) xor gfmult3(sub_tmp_s(127 downto 120)); |
sub_tmp_mix(127 downto 120) <= gfmult3(sub_tmp_s(103 downto 96)) xor sub_tmp_s(111 downto 104) xor sub_tmp_s(119 downto 112) xor gfmult2(sub_tmp_s(127 downto 120)); |
|
else |
sub_tmp_mix <= sub_tmp_s; |
|
end if; |
end process; |
|
block_out <= sub_tmp_mix xor sub_key; |
|
end Behavioral; |
|
/trunk/aes_c_2/src/aes_lib.vhd
0,0 → 1,46
|
-- Two Galois multiplication functions based on http://www.isaakian.com/VHDL/AES/. |
|
library ieee; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
|
package aes_lib is |
|
function gfmult2 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector; |
|
function gfmult3 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector; |
|
|
end aes_lib; |
|
|
package body aes_lib is |
|
function gfmult2 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector is |
variable result : std_logic_vector(7 downto 0); |
begin |
|
result := (I(6 downto 0) & '0') xor (x"1B" and ("000" & I(7)& I(7) & "0" & I(7)& I(7))); |
return result; |
end gfmult2; |
|
function gfmult3 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector is |
variable result : std_logic_vector(7 downto 0); |
begin |
result := gfmult2(I) xor I; |
return result; |
end gfmult3; |
|
end aes_lib; |
/trunk/aes_c_2/synthesis/aes_enc.prj
0,0 → 1,3
../src/aes_lib.vhd |
../src/dual_mem.vhd |
../src/aes_enc.vhd |
/trunk/aes_c_2/synthesis/aes_fsm_enc.prj
0,0 → 1,4
../src/aes_lib.vhd |
../src/dual_mem.vhd |
../src/aes_enc.vhd |
../src/aes_fsm_enc.vhd |
/trunk/aes_c_2/Makefile
0,0 → 1,20
DEVICE=xc6slx75-3csg484 |
|
sim_aes: scripts/aes_enc.do |
vsim -do scripts/aes_enc.do |
|
sim_aes_fsm: scripts/aes_fsm_enc.do |
vsim -do scripts/aes_fsm_enc.do |
|
syn_aes: |
echo "run -ifn synthesis/aes_enc.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
syn_aes_fsm: |
echo "run -ifn synthesis/aes_fsm_enc.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
|
clean: |
rm -rf transcript work vsim.wlf *.rlf *.vstf *~ *.xrpt *.ngc _xmsgs xst .lso |
|
|
|
/trunk/aes_c_2/mem/key.mem
0,0 → 1,10
fe76abd6f178a6dafa72afd2fd74aad6 |
feb3306800c59bbef1bd3d640bcf92b6 |
41bf6904bf0c596cbfc9c2d24e74ffb6 |
fd8d05fdbc326cf9033e3595bcf7f747 |
aa22f6ad57aff350eb9d9fa9e8a3aa3c |
6b1fa30ac13d55a79692a6f77d0f395e |
26c0a94e4ddf0a448ce25fe31a70f914 |
d27abfaef4ba16e0b9651ca435874347 |
4e972cbe9ced9310685785f0d1329954 |
c5302b4d8ba707f3174a94e37f1d1113 |
/trunk/aes_c_2/mem/s_box.mem
0,0 → 1,256
63 |
7c |
77 |
7b |
f2 |
6b |
6f |
c5 |
30 |
01 |
67 |
2b |
fe |
d7 |
ab |
76 |
ca |
82 |
c9 |
7d |
fa |
59 |
47 |
f0 |
ad |
d4 |
a2 |
af |
9c |
a4 |
72 |
c0 |
b7 |
fd |
93 |
26 |
36 |
3f |
f7 |
cc |
34 |
a5 |
e5 |
f1 |
71 |
d8 |
31 |
15 |
04 |
c7 |
23 |
c3 |
18 |
96 |
05 |
9a |
07 |
12 |
80 |
e2 |
eb |
27 |
b2 |
75 |
09 |
83 |
2c |
1a |
1b |
6e |
5a |
a0 |
52 |
3b |
d6 |
b3 |
29 |
e3 |
2f |
84 |
53 |
d1 |
00 |
ed |
20 |
fc |
b1 |
5b |
6a |
cb |
be |
39 |
4a |
4c |
58 |
cf |
d0 |
ef |
aa |
fb |
43 |
4d |
33 |
85 |
45 |
f9 |
02 |
7f |
50 |
3c |
9f |
a8 |
51 |
a3 |
40 |
8f |
92 |
9d |
38 |
f5 |
bc |
b6 |
da |
21 |
10 |
ff |
f3 |
d2 |
cd |
0c |
13 |
ec |
5f |
97 |
44 |
17 |
c4 |
a7 |
7e |
3d |
64 |
5d |
19 |
73 |
60 |
81 |
4f |
dc |
22 |
2a |
90 |
88 |
46 |
ee |
b8 |
14 |
de |
5e |
0b |
db |
e0 |
32 |
3a |
0a |
49 |
06 |
24 |
5c |
c2 |
d3 |
ac |
62 |
91 |
95 |
e4 |
79 |
e7 |
c8 |
37 |
6d |
8d |
d5 |
4e |
a9 |
6c |
56 |
f4 |
ea |
65 |
7a |
ae |
08 |
ba |
78 |
25 |
2e |
1c |
a6 |
b4 |
c6 |
e8 |
dd |
74 |
1f |
4b |
bd |
8b |
8a |
70 |
3e |
b5 |
66 |
48 |
03 |
f6 |
0e |
61 |
35 |
57 |
b9 |
86 |
c1 |
1d |
9e |
e1 |
f8 |
98 |
11 |
69 |
d9 |
8e |
94 |
9b |
1e |
87 |
e9 |
ce |
55 |
28 |
df |
8c |
a1 |
89 |
0d |
bf |
e6 |
42 |
68 |
41 |
99 |
2d |
0f |
b0 |
54 |
bb |
16 |
/trunk/aes_c_2/mem/gfmult_2.mem
0,0 → 1,256
00000000 |
00000010 |
00000100 |
00000110 |
00001000 |
00001010 |
00001100 |
00001110 |
00010000 |
00010010 |
00010100 |
00010110 |
00011000 |
00011010 |
00011100 |
00011110 |
00100000 |
00100010 |
00100100 |
00100110 |
00101000 |
00101010 |
00101100 |
00101110 |
00110000 |
00110010 |
00110100 |
00110110 |
00111000 |
00111010 |
00111100 |
00111110 |
01000000 |
01000010 |
01000100 |
01000110 |
01001000 |
01001010 |
01001100 |
01001110 |
01010000 |
01010010 |
01010100 |
01010110 |
01011000 |
01011010 |
01011100 |
01011110 |
01100000 |
01100010 |
01100100 |
01100110 |
01101000 |
01101010 |
01101100 |
01101110 |
01110000 |
01110010 |
01110100 |
01110110 |
01111000 |
01111010 |
01111100 |
01111110 |
10000000 |
10000010 |
10000100 |
10000110 |
10001000 |
10001010 |
10001100 |
10001110 |
10010000 |
10010010 |
10010100 |
10010110 |
10011000 |
10011010 |
10011100 |
10011110 |
10100000 |
10100010 |
10100100 |
10100110 |
10101000 |
10101010 |
10101100 |
10101110 |
10110000 |
10110010 |
10110100 |
10110110 |
10111000 |
10111010 |
10111100 |
10111110 |
11000000 |
11000010 |
11000100 |
11000110 |
11001000 |
11001010 |
11001100 |
11001110 |
11010000 |
11010010 |
11010100 |
11010110 |
11011000 |
11011010 |
11011100 |
11011110 |
11100000 |
11100010 |
11100100 |
11100110 |
11101000 |
11101010 |
11101100 |
11101110 |
11110000 |
11110010 |
11110100 |
11110110 |
11111000 |
11111010 |
11111100 |
11111110 |
00011011 |
00011001 |
00011111 |
00011101 |
00010011 |
00010001 |
00010111 |
00010101 |
00001011 |
00001001 |
00001111 |
00001101 |
00000011 |
00000001 |
00000111 |
00000101 |
00111011 |
00111001 |
00111111 |
00111101 |
00110011 |
00110001 |
00110111 |
00110101 |
00101011 |
00101001 |
00101111 |
00101101 |
00100011 |
00100001 |
00100111 |
00100101 |
01011011 |
01011001 |
01011111 |
01011101 |
01010011 |
01010001 |
01010111 |
01010101 |
01001011 |
01001001 |
01001111 |
01001101 |
01000011 |
01000001 |
01000111 |
01000101 |
01111011 |
01111001 |
01111111 |
01111101 |
01110011 |
01110001 |
01110111 |
01110101 |
01101011 |
01101001 |
01101111 |
01101101 |
01100011 |
01100001 |
01100111 |
01100101 |
10011011 |
10011001 |
10011111 |
10011101 |
10010011 |
10010001 |
10010111 |
10010101 |
10001011 |
10001001 |
10001111 |
10001101 |
10000011 |
10000001 |
10000111 |
10000101 |
10111011 |
10111001 |
10111111 |
10111101 |
10110011 |
10110001 |
10110111 |
10110101 |
10101011 |
10101001 |
10101111 |
10101101 |
10100011 |
10100001 |
10100111 |
10100101 |
11011011 |
11011001 |
11011111 |
11011101 |
11010011 |
11010001 |
11010111 |
11010101 |
11001011 |
11001001 |
11001111 |
11001101 |
11000011 |
11000001 |
11000111 |
11000101 |
11111011 |
11111001 |
11111111 |
11111101 |
11110011 |
11110001 |
11110111 |
11110101 |
11101011 |
11101001 |
11101111 |
11101101 |
11100011 |
11100001 |
11100111 |
11100101 |
/trunk/aes_c_2/mem/gfmult_3.mem
0,0 → 1,256
00000000 |
00000011 |
00000110 |
00000101 |
00001100 |
00001111 |
00001010 |
00001001 |
00011000 |
00011011 |
00011110 |
00011101 |
00010100 |
00010111 |
00010010 |
00010001 |
00110000 |
00110011 |
00110110 |
00110101 |
00111100 |
00111111 |
00111010 |
00111001 |
00101000 |
00101011 |
00101110 |
00101101 |
00100100 |
00100111 |
00100010 |
00100001 |
01100000 |
01100011 |
01100110 |
01100101 |
01101100 |
01101111 |
01101010 |
01101001 |
01111000 |
01111011 |
01111110 |
01111101 |
01110100 |
01110111 |
01110010 |
01110001 |
01010000 |
01010011 |
01010110 |
01010101 |
01011100 |
01011111 |
01011010 |
01011001 |
01001000 |
01001011 |
01001110 |
01001101 |
01000100 |
01000111 |
01000010 |
01000001 |
11000000 |
11000011 |
11000110 |
11000101 |
11001100 |
11001111 |
11001010 |
11001001 |
11011000 |
11011011 |
11011110 |
11011101 |
11010100 |
11010111 |
11010010 |
11010001 |
11110000 |
11110011 |
11110110 |
11110101 |
11111100 |
11111111 |
11111010 |
11111001 |
11101000 |
11101011 |
11101110 |
11101101 |
11100100 |
11100111 |
11100010 |
11100001 |
10100000 |
10100011 |
10100110 |
10100101 |
10101100 |
10101111 |
10101010 |
10101001 |
10111000 |
10111011 |
10111110 |
10111101 |
10110100 |
10110111 |
10110010 |
10110001 |
10010000 |
10010011 |
10010110 |
10010101 |
10011100 |
10011111 |
10011010 |
10011001 |
10001000 |
10001011 |
10001110 |
10001101 |
10000100 |
10000111 |
10000010 |
10000001 |
10011011 |
10011000 |
10011101 |
10011110 |
10010111 |
10010100 |
10010001 |
10010010 |
10000011 |
10000000 |
10000101 |
10000110 |
10001111 |
10001100 |
10001001 |
10001010 |
10101011 |
10101000 |
10101101 |
10101110 |
10100111 |
10100100 |
10100001 |
10100010 |
10110011 |
10110000 |
10110101 |
10110110 |
10111111 |
10111100 |
10111001 |
10111010 |
11111011 |
11111000 |
11111101 |
11111110 |
11110111 |
11110100 |
11110001 |
11110010 |
11100011 |
11100000 |
11100101 |
11100110 |
11101111 |
11101100 |
11101001 |
11101010 |
11001011 |
11001000 |
11001101 |
11001110 |
11000111 |
11000100 |
11000001 |
11000010 |
11010011 |
11010000 |
11010101 |
11010110 |
11011111 |
11011100 |
11011001 |
11011010 |
01011011 |
01011000 |
01011101 |
01011110 |
01010111 |
01010100 |
01010001 |
01010010 |
01000011 |
01000000 |
01000101 |
01000110 |
01001111 |
01001100 |
01001001 |
01001010 |
01101011 |
01101000 |
01101101 |
01101110 |
01100111 |
01100100 |
01100001 |
01100010 |
01110011 |
01110000 |
01110101 |
01110110 |
01111111 |
01111100 |
01111001 |
01111010 |
00111011 |
00111000 |
00111101 |
00111110 |
00110111 |
00110100 |
00110001 |
00110010 |
00100011 |
00100000 |
00100101 |
00100110 |
00101111 |
00101100 |
00101001 |
00101010 |
00001011 |
00001000 |
00001101 |
00001110 |
00000111 |
00000100 |
00000001 |
00000010 |
00010011 |
00010000 |
00010101 |
00010110 |
00011111 |
00011100 |
00011001 |
00011010 |
/trunk/aes_c_3/scripts/aes_fsm_enc.do
0,0 → 1,78
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
|
vcom -explicit -93 "src/aes_lib.vhd" |
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/aes_enc.vhd" |
vcom -explicit -93 "src/aes_fsm_enc.vhd" |
vcom -explicit -93 "src/tb_aes_fsm_enc.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_aes_fsm_enc |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_2 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_3 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_4 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_5 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_6 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_7 |
mem load -infile mem/s_box.mem -format hex tb_aes_fsm_enc/uut/aes_round_n/s_box_dual_8 |
|
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_1 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_2 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_3 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_4 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_5 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_6 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_7 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_2_8 |
|
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_1 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_2 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_3 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_4 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_5 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_6 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_7 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_fsm_enc/uut/aes_round_n/gf_mult_3_8 |
|
mem load -infile mem/key.mem -format hex tb_aes_fsm_enc/uut/sub_keys_dram |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/state } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/block_out_s } |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/key_addr_1 } \ |
{sim:/tb_aes_fsm_enc/uut/key_data_1 } \ |
{sim:/tb_aes_fsm_enc/uut/key_data_2 } \ |
{sim:/tb_aes_fsm_enc/uut/count } |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/clk_3 } |
add wave \ |
{sim:/tb_aes_fsm_enc/uut/clk_tmp } |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/sub_key_s } |
|
add wave \ |
{sim:/tb_aes_fsm_enc/uut/pos_cnt } \ |
{sim:/tb_aes_fsm_enc/uut/neg_cnt } |
|
run 10 us |
|
/trunk/aes_c_3/scripts/aes_enc.do
0,0 → 1,59
# script general de simulacion |
# questa v6 |
|
vlib work |
|
# libs |
|
vcom -explicit -93 "src/aes_lib.vhd" |
vcom -explicit -93 "src/dual_mem.vhd" |
vcom -explicit -93 "src/aes_enc.vhd" |
vcom -explicit -93 "src/tb_aes_enc.vhd" |
|
# Sim |
|
vsim -lib work -t 1ps tb_aes_enc |
|
view wave |
view source |
view structure |
view signals |
add wave * |
|
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_1 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_2 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_3 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_4 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_5 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_6 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_7 |
mem load -infile mem/s_box.mem -format hex tb_aes_enc/uut/s_box_dual_8 |
|
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_1 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_2 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_3 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_4 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_5 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_6 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_7 |
mem load -infile mem/gfmult_2.mem -format bin tb_aes_enc/uut/gf_mult_2_8 |
|
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_1 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_2 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_3 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_4 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_5 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_6 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_7 |
mem load -infile mem/gfmult_3.mem -format bin tb_aes_enc/uut/gf_mult_3_8 |
|
add wave \ |
{sim:/tb_aes_enc/uut/sub_tmp_s } |
add wave \ |
{sim:/tb_aes_enc/uut/sub_tmp_mix } |
|
|
run 50 us |
|
add wave \ |
{sim:/tb_aes_enc/uut/key_reg } |
/trunk/aes_c_3/src/tb_aes_enc.vhd
0,0 → 1,86
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
-- Uncomment the following library declaration if using |
-- arithmetic functions with Signed or Unsigned values |
--USE ieee.numeric_std.ALL; |
|
ENTITY tb_aes_enc IS |
END tb_aes_enc; |
|
ARCHITECTURE behavior OF tb_aes_enc IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT aes_enc |
PORT( |
clk : IN std_logic; |
block_in : IN std_logic_vector(127 downto 0); |
sub_key : IN std_logic_vector(127 downto 0); |
last : IN std_logic; |
|
block_out : OUT std_logic_vector(127 downto 0)); |
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal block_in : std_logic_vector(127 downto 0) := (others => '0'); |
signal sub_key : std_logic_vector(127 downto 0) := (others=> '0'); |
signal last : std_logic := '0'; |
|
--Outputs |
signal block_out : std_logic_vector(127 downto 0); |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: aes_enc PORT MAP ( |
clk => clk, |
block_in => block_in, |
sub_key => sub_key, |
last => last, |
block_out => block_out); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
|
block_in <= X"0f0e0d0c0b0a09080706050403020100"; |
|
sub_key <= X"0f0e0d0c0b0a09080706050403020100"; |
|
wait for clk_period*2; |
|
wait; |
end process; |
|
END; |
/trunk/aes_c_3/src/aes_fsm_enc.vhd
0,0 → 1,215
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
---------------------------------------------------------------------------------- |
library IEEE; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
use ieee.numeric_std.all; |
|
use work.aes_lib.all; |
|
entity aes_fsm_enc is |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
key : in std_logic_vector(127 downto 0); |
enc : in std_logic; |
block_out : out std_logic_vector(127 downto 0); |
block_ready : out std_logic); |
end aes_fsm_enc; |
|
architecture Behavioral of aes_fsm_enc is |
|
attribute buffer_type: string; |
|
type state_type is (idle, n_round_1, n_round_2, n_round_3, reinit, reinit2, pre, all_reset); |
|
signal state, next_state: state_type ; |
signal block_in_s : std_logic_vector(127 downto 0); |
signal sub_key_s : std_logic_vector(127 downto 0); |
signal last_s : std_logic; |
signal block_out_s, tmp : std_logic_vector(127 downto 0); |
|
signal key_addr_1, key_addr_2 : std_logic_vector(3 downto 0); |
signal key_data_1, key_data_delay_1, key_data_2, key_data_delay_2 : std_logic_vector(127 downto 0); |
|
signal count: natural range 0 to 10; |
signal en_cnt : std_logic; |
signal clk_3, clk_tmp : std_logic; |
|
signal pos_cnt :std_logic_vector (1 downto 0); |
signal neg_cnt :std_logic_vector (1 downto 0); |
|
signal rst_div, rst_cnt : std_logic; |
|
attribute buffer_type of clk_3: signal is "bufg"; |
|
begin |
|
process1: process (clk,rst) |
begin |
if (rst ='1') then |
state <= idle; |
elsif rising_edge(clk) then |
state <= next_state; |
end if; |
end process process1; |
|
process2 : process (state, enc, block_in, key) |
begin |
next_state <= state; |
|
last_s <= '0'; |
block_in_s <= (others => '0'); |
sub_key_s <= (others => '0'); |
block_ready <= '0'; |
en_cnt <= '0'; |
|
rst_div <= '0'; |
rst_cnt <= '0'; |
|
case state is |
when idle => |
if enc ='1' then |
next_state <= all_reset; |
else |
en_cnt <= '0'; |
next_state <= idle; |
end if; |
when all_reset => |
rst_div <= '1'; |
rst_cnt <= '1'; |
|
next_state <= pre; |
when pre => |
rst_cnt <= '0'; |
rst_div <= '0'; |
|
sub_key_s <= key_data_1; |
block_in_s <= block_in xor key; |
en_cnt <= '1'; |
|
next_state <= n_round_1; |
when n_round_1 => |
en_cnt <= '1'; |
block_in_s <= tmp; |
sub_key_s <= key_data_1; |
next_state <= n_round_2; |
when n_round_2 => |
en_cnt <= '1'; |
sub_key_s <= key_data_1; |
block_in_s <= tmp; |
next_state <= n_round_3; |
when n_round_3 => |
en_cnt <= '1'; |
sub_key_s <= key_data_1; |
|
block_in_s <= tmp; |
|
if count = 9 then |
last_s <= '1'; |
block_ready <= '1'; |
sub_key_s <= key_data_1; |
block_in_s <= tmp; |
next_state <= reinit; |
else |
next_state <= n_round_1; |
end if; |
when reinit => |
en_cnt <= '1'; |
next_state <= idle; |
when reinit2 => |
en_cnt <= '1'; |
next_state <= idle; |
end case; |
|
end process process2; |
|
get_output : process(clk, state) |
begin |
if rising_edge(clk) then |
if state = n_round_1 then |
tmp <= block_out_s; |
end if; |
end if; |
end process; |
|
mod_10_cnt : process(clk_3, rst_cnt) |
begin |
if rising_edge(clk_3) then |
if (rst_cnt = '1') then |
count <= 0; |
elsif(en_cnt = '1') then |
if (count = 9) then |
count <= 0; |
else |
count <= count + 1; |
end if; |
end if; |
end if; |
end process mod_10_cnt; |
|
key_addr_1 <= std_logic_vector(to_unsigned(count, key_addr_1'length)); |
key_addr_2 <= std_logic_vector(to_unsigned(count, key_addr_2'length)); |
|
AES_ROUND_N : entity work.aes_enc(Behavioral) port map (clk, |
block_in_s, |
sub_key_s, |
last_s, |
block_out_s); |
|
SUB_KEYS_DRAM : entity work.dual_mem(rtl) generic map (4, 128, 10) |
port map (clk, |
'0', |
key_addr_1, |
key_addr_2, |
(others => '0'), |
key_data_1, |
key_data_2); |
|
block_out <= block_out_s; |
|
div_3_p_1: process (clk, rst_div) begin |
if (rst_div = '1') then |
pos_cnt <= (others=>'0'); |
elsif (rising_edge(clk)) then |
pos_cnt <= pos_cnt + 1; |
if (pos_cnt = 2) then |
pos_cnt <= (others => '0'); |
end if; |
end if; |
end process; |
|
div_3_p_2: process (clk, rst_div) begin |
if (rst_div = '1') then |
neg_cnt <= (others=>'0'); |
elsif (falling_edge(clk)) then |
neg_cnt <= neg_cnt + 1; |
if (neg_cnt = 2) then |
neg_cnt <= (others => '0'); |
end if; |
end if; |
end process; |
|
block_out <= block_out_s; |
|
|
clk_3 <= '0' when ((pos_cnt /= 2) and (neg_cnt /= 2)) else |
'1'; |
|
end Behavioral; |
|
/trunk/aes_c_3/src/dual_mem.vhd
0,0 → 1,57
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
entity dual_mem is |
generic (ADDR_LENGTH : integer := 8; |
DATA_LENGTH : integer := 8; |
N_ADDR : integer := 256); |
port (clk : in std_logic; |
we : in std_logic; |
a : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0); |
di : in std_logic_vector(DATA_LENGTH - 1 downto 0); |
spo : out std_logic_vector(DATA_LENGTH - 1 downto 0); |
dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0)); |
end dual_mem; |
|
architecture rtl of dual_mem is |
type ram_type is array (N_ADDR - 1 downto 0) |
of std_logic_vector (DATA_LENGTH - 1 downto 0); |
signal RAM : ram_type; |
signal read_a : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
signal read_dpra : std_logic_vector(ADDR_LENGTH - 1 downto 0); |
|
attribute ram_style: string; |
attribute ram_style of RAM: signal is "block"; |
|
begin |
process (clk) |
begin |
if rising_edge(clk) then |
if (we = '1') then |
RAM(conv_integer(a)) <= di; |
end if; |
read_a <= a; |
read_dpra <= dpra; |
end if; |
end process; |
|
spo <= RAM(conv_integer(read_a)); |
dpo <= RAM(conv_integer(read_dpra)); |
end rtl; |
/trunk/aes_c_3/src/tb_aes_fsm_enc.vhd
0,0 → 1,108
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
|
|
ENTITY tb_aes_fsm_enc IS |
END tb_aes_fsm_enc; |
|
ARCHITECTURE behavior OF tb_aes_fsm_enc IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT aes_fsm_enc |
port( clk: in std_logic; |
rst : in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
key : in std_logic_vector(127 downto 0); |
enc : in std_logic; |
block_out : out std_logic_vector(127 downto 0); |
block_ready : out std_logic); |
|
END COMPONENT; |
|
|
--Inputs |
signal clk : std_logic := '0'; |
signal rst : std_logic := '0'; |
signal block_in : std_logic_vector(127 downto 0) := (others => '0'); |
signal key : std_logic_vector(127 downto 0) := (others=> '0'); |
signal enc : std_logic := '0'; |
|
--Outputs |
signal block_out : std_logic_vector(127 downto 0); |
signal block_ready : std_logic; |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: aes_fsm_enc PORT MAP ( |
clk => clk, |
rst => rst, |
block_in => block_in, |
key => key, |
enc => enc, |
block_out => block_out, |
block_ready => block_ready); |
|
-- Clock process definitions |
clk_process :process |
begin |
clk <= '0'; |
wait for clk_period/2; |
clk <= '1'; |
wait for clk_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
|
wait for clk_period/2 + clk_period*2; |
rst <= '1'; |
|
wait for clk_period; |
rst <= '0'; |
enc <= '1'; |
|
block_in <= X"0f0e0d0c0b0a09080706050403020100"; |
key <= X"0f0e0d0c0b0a09080706050403020100"; |
|
wait for 0.28 us; |
|
enc <= '0'; |
|
wait for 2 us; |
|
enc <= '1'; |
|
wait for 0.580 us; |
|
enc <= '0'; |
|
wait for 3 us; |
|
enc <= '1'; |
|
wait; |
end process; |
|
END; |
/trunk/aes_c_3/src/aes_enc.vhd
0,0 → 1,138
-- Copyright (c) 2011 Antonio de la Piedra |
|
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or |
-- (at your option) any later version. |
|
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
|
-- You should have received a copy of the GNU General Public License |
-- along with this program. If not, see <http://www.gnu.org/licenses/>. |
|
library IEEE; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
use work.aes_lib.all; |
|
entity aes_enc is |
port( clk: in std_logic; |
block_in : in std_logic_vector(127 downto 0); |
sub_key : in std_logic_vector(127 downto 0); |
last : in std_logic; |
block_out : out std_logic_vector(127 downto 0)); |
end aes_enc; |
|
architecture Behavioral of aes_enc is |
|
signal sub_tmp_s : std_logic_vector(127 downto 0); |
signal sub_tmp_mix : std_logic_vector(127 downto 0); |
|
signal test_2_1, test_2_2, test_2_3, test_2_4, test_2_5, test_2_6, test_2_7, test_2_8 : std_logic_vector(7 downto 0); |
signal test_2_9, test_2_10, test_2_11, test_2_12, test_2_13, test_2_14, test_2_15, test_2_16 : std_logic_vector(7 downto 0); |
signal test_3_1, test_3_2, test_3_3, test_3_4, test_3_5, test_3_6, test_3_7, test_3_8 : std_logic_vector(7 downto 0); |
signal test_3_9, test_3_10, test_3_11, test_3_12, test_3_13, test_3_14, test_3_15, test_3_16 : std_logic_vector(7 downto 0); |
|
signal sub_key_delay, sub_tmp_s_delay, sub_tmp_s_delay_1, sub_tmp_mix_delay : std_logic_vector(127 downto 0); |
begin |
|
S_BOX_DUAL_1: entity work.dual_mem(rtl) port map (clk, '0', block_in(7 downto 0), block_in(47 downto 40), (others=>'0'), sub_tmp_s(7 downto 0), sub_tmp_s(15 downto 8)); |
S_BOX_DUAL_2: entity work.dual_mem(rtl) port map (clk, '0', block_in(87 downto 80), block_in(127 downto 120), (others=>'0'), sub_tmp_s(23 downto 16), sub_tmp_s(31 downto 24)); |
S_BOX_DUAL_3: entity work.dual_mem(rtl) port map (clk, '0', block_in(39 downto 32), block_in(79 downto 72), (others=>'0'), sub_tmp_s(39 downto 32), sub_tmp_s(47 downto 40)); |
S_BOX_DUAL_4: entity work.dual_mem(rtl) port map (clk, '0', block_in(119 downto 112), block_in(31 downto 24), (others=>'0'), sub_tmp_s(55 downto 48), sub_tmp_s(63 downto 56)); |
S_BOX_DUAL_5: entity work.dual_mem(rtl) port map (clk, '0', block_in(71 downto 64), block_in(111 downto 104), (others=>'0'), sub_tmp_s(71 downto 64), sub_tmp_s(79 downto 72)); |
S_BOX_DUAL_6: entity work.dual_mem(rtl) port map (clk, '0', block_in(23 downto 16), block_in(63 downto 56), (others=>'0'), sub_tmp_s(87 downto 80), sub_tmp_s(95 downto 88)); |
S_BOX_DUAL_7: entity work.dual_mem(rtl) port map (clk, '0', block_in(103 downto 96), block_in(15 downto 8), (others=>'0'), sub_tmp_s(103 downto 96), sub_tmp_s(111 downto 104)); |
S_BOX_DUAL_8: entity work.dual_mem(rtl) port map (clk, '0', block_in(55 downto 48), block_in(95 downto 88), (others=>'0'), sub_tmp_s(119 downto 112), sub_tmp_s(127 downto 120)); |
|
GF_MULT_2_1: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(7 downto 0), sub_tmp_s(15 downto 8), (others=>'0'), test_2_1, test_2_2); |
GF_MULT_2_2: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(23 downto 16), sub_tmp_s(31 downto 24), (others=>'0'), test_2_3, test_2_4); |
GF_MULT_2_3: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(39 downto 32), sub_tmp_s(47 downto 40), (others=>'0'), test_2_5, test_2_6); |
GF_MULT_2_4: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(55 downto 48), sub_tmp_s(63 downto 56), (others=>'0'), test_2_7, test_2_8); |
GF_MULT_2_5: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(71 downto 64), sub_tmp_s(79 downto 72), (others=>'0'), test_2_9, test_2_10); |
GF_MULT_2_6: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(87 downto 80), sub_tmp_s(95 downto 88), (others=>'0'), test_2_11, test_2_12); |
GF_MULT_2_7: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(103 downto 96), sub_tmp_s(111 downto 104), (others=>'0'), test_2_13, test_2_14); |
GF_MULT_2_8: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(119 downto 112), sub_tmp_s(127 downto 120), (others=>'0'), test_2_15, test_2_16); |
|
GF_MULT_3_1: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(7 downto 0), sub_tmp_s(15 downto 8), (others=>'0'), test_3_4, test_3_1); |
GF_MULT_3_2: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(23 downto 16), sub_tmp_s(31 downto 24), (others=>'0'), test_3_2, test_3_3); |
GF_MULT_3_3: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(39 downto 32), sub_tmp_s(47 downto 40), (others=>'0'), test_3_8, test_3_5); |
GF_MULT_3_4: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(55 downto 48), sub_tmp_s(63 downto 56), (others=>'0'), test_3_6, test_3_7); |
GF_MULT_3_5: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(71 downto 64), sub_tmp_s(79 downto 72), (others=>'0'), test_3_12, test_3_9); |
GF_MULT_3_6: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(87 downto 80), sub_tmp_s(95 downto 88), (others=>'0'), test_3_10, test_3_11); |
GF_MULT_3_7: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(103 downto 96), sub_tmp_s(111 downto 104), (others=>'0'), test_3_16, test_3_13); |
GF_MULT_3_8: entity work.dual_mem(rtl) port map (clk, '0', sub_tmp_s(119 downto 112), sub_tmp_s(127 downto 120), (others=>'0'), test_3_14, test_3_15); |
|
MIX_COL: process(test_2_1, |
test_2_2, |
test_2_3, |
test_2_4, |
test_2_5, |
test_2_6, |
test_2_7, |
test_2_8, |
test_2_9, |
test_2_10, |
test_2_11, |
test_2_12, |
test_2_13, |
test_2_14, |
test_2_15, |
test_2_16, |
test_3_1, |
test_3_2, |
test_3_3, |
test_3_4, |
test_3_5, |
test_3_6, |
test_3_7, |
test_3_8, |
test_3_9, |
test_3_10, |
test_3_11, |
test_3_12, |
test_3_13, |
test_3_14, |
test_3_15, |
test_3_16, |
sub_tmp_s, |
last) |
begin |
if last = '0' then |
|
sub_tmp_mix(7 downto 0) <= test_2_1 xor test_3_1 xor sub_tmp_s(23 downto 16) xor sub_tmp_s(31 downto 24); |
sub_tmp_mix(15 downto 8) <= sub_tmp_s(7 downto 0) xor test_2_2 xor test_3_2 xor sub_tmp_s(31 downto 24); |
sub_tmp_mix(23 downto 16) <= sub_tmp_s(7 downto 0) xor sub_tmp_s(15 downto 8) xor test_2_3 xor test_3_3; |
sub_tmp_mix(31 downto 24) <= test_3_4 xor sub_tmp_s(15 downto 8) xor sub_tmp_s(23 downto 16) xor test_2_4; |
|
sub_tmp_mix(39 downto 32) <= test_2_5 xor test_3_5 xor sub_tmp_s(55 downto 48) xor sub_tmp_s(63 downto 56); |
sub_tmp_mix(47 downto 40) <= sub_tmp_s(39 downto 32) xor test_2_6 xor test_3_6 xor sub_tmp_s(63 downto 56); |
sub_tmp_mix(55 downto 48) <= sub_tmp_s(39 downto 32) xor sub_tmp_s(47 downto 40) xor test_2_7 xor test_3_7; |
sub_tmp_mix(63 downto 56) <= test_3_8 xor sub_tmp_s(47 downto 40) xor sub_tmp_s(55 downto 48) xor test_2_8; |
|
sub_tmp_mix(71 downto 64) <= test_2_9 xor test_3_9 xor sub_tmp_s(87 downto 80) xor sub_tmp_s(95 downto 88); |
sub_tmp_mix(79 downto 72) <= sub_tmp_s(71 downto 64) xor test_2_10 xor test_3_10 xor sub_tmp_s(95 downto 88); |
sub_tmp_mix(87 downto 80) <= sub_tmp_s(71 downto 64) xor sub_tmp_s(79 downto 72) xor test_2_11 xor test_3_11; |
sub_tmp_mix(95 downto 88) <= test_3_12 xor sub_tmp_s(79 downto 72) xor sub_tmp_s(87 downto 80) xor test_2_12; |
|
sub_tmp_mix(103 downto 96) <= test_2_13 xor test_3_13 xor sub_tmp_s(119 downto 112) xor sub_tmp_s(127 downto 120); |
sub_tmp_mix(111 downto 104) <= sub_tmp_s(103 downto 96) xor test_2_14 xor test_3_14 xor sub_tmp_s(127 downto 120); |
sub_tmp_mix(119 downto 112) <= sub_tmp_s(103 downto 96) xor sub_tmp_s(111 downto 104) xor test_2_15 xor test_3_15; |
sub_tmp_mix(127 downto 120) <= test_3_16 xor sub_tmp_s(111 downto 104) xor sub_tmp_s(119 downto 112) xor test_2_16; |
|
else |
sub_tmp_mix <= sub_tmp_s; |
|
end if; |
end process; |
|
block_out <= sub_tmp_mix xor sub_key; |
|
end Behavioral; |
|
/trunk/aes_c_3/src/aes_lib.vhd
0,0 → 1,46
|
-- Two Galois multiplication functions based on http://www.isaakian.com/VHDL/AES/. |
|
library ieee; |
|
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.std_logic_ARITH.ALL; |
use IEEE.std_logic_UNSIGNED.ALL; |
|
|
package aes_lib is |
|
function gfmult2 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector; |
|
function gfmult3 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector; |
|
|
end aes_lib; |
|
|
package body aes_lib is |
|
function gfmult2 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector is |
variable result : std_logic_vector(7 downto 0); |
begin |
|
result := (I(6 downto 0) & '0') xor (x"1B" and ("000" & I(7)& I(7) & "0" & I(7)& I(7))); |
return result; |
end gfmult2; |
|
function gfmult3 ( |
I : std_logic_vector(7 downto 0)) |
return std_logic_vector is |
variable result : std_logic_vector(7 downto 0); |
begin |
result := gfmult2(I) xor I; |
return result; |
end gfmult3; |
|
end aes_lib; |
/trunk/aes_c_3/synthesis/aes_enc.prj
0,0 → 1,3
../src/aes_lib.vhd |
../src/dual_mem.vhd |
../src/aes_enc.vhd |
/trunk/aes_c_3/synthesis/aes_fsm_enc.prj
0,0 → 1,4
../src/aes_lib.vhd |
../src/dual_mem.vhd |
../src/aes_enc.vhd |
../src/aes_fsm_enc.vhd |
/trunk/aes_c_3/Makefile
0,0 → 1,20
DEVICE=xc6slx75-3csg484 |
|
sim_aes: scripts/aes_enc.do |
vsim -do scripts/aes_enc.do |
|
sim_aes_fsm: scripts/aes_fsm_enc.do |
vsim -do scripts/aes_fsm_enc.do |
|
syn_aes: |
echo "run -ifn synthesis/aes_enc.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
syn_aes_fsm: |
echo "run -ifn synthesis/aes_fsm_enc.prj -ifmt VHDL -ofn aes_enc -p \ |
$(DEVICE) -opt_mode Speed -opt_level 1" | xst |
|
clean: |
rm -rf transcript work vsim.wlf *.rlf *.vstf *~ *.xrpt *.ngc _xmsgs xst .lso |
|
|
|
/trunk/aes_c_3/mem/key.mem
0,0 → 1,10
fe76abd6f178a6dafa72afd2fd74aad6 |
feb3306800c59bbef1bd3d640bcf92b6 |
41bf6904bf0c596cbfc9c2d24e74ffb6 |
fd8d05fdbc326cf9033e3595bcf7f747 |
aa22f6ad57aff350eb9d9fa9e8a3aa3c |
6b1fa30ac13d55a79692a6f77d0f395e |
26c0a94e4ddf0a448ce25fe31a70f914 |
d27abfaef4ba16e0b9651ca435874347 |
4e972cbe9ced9310685785f0d1329954 |
c5302b4d8ba707f3174a94e37f1d1113 |
/trunk/aes_c_3/mem/s_box.mem
0,0 → 1,256
63 |
7c |
77 |
7b |
f2 |
6b |
6f |
c5 |
30 |
01 |
67 |
2b |
fe |
d7 |
ab |
76 |
ca |
82 |
c9 |
7d |
fa |
59 |
47 |
f0 |
ad |
d4 |
a2 |
af |
9c |
a4 |
72 |
c0 |
b7 |
fd |
93 |
26 |
36 |
3f |
f7 |
cc |
34 |
a5 |
e5 |
f1 |
71 |
d8 |
31 |
15 |
04 |
c7 |
23 |
c3 |
18 |
96 |
05 |
9a |
07 |
12 |
80 |
e2 |
eb |
27 |
b2 |
75 |
09 |
83 |
2c |
1a |
1b |
6e |
5a |
a0 |
52 |
3b |
d6 |
b3 |
29 |
e3 |
2f |
84 |
53 |
d1 |
00 |
ed |
20 |
fc |
b1 |
5b |
6a |
cb |
be |
39 |
4a |
4c |
58 |
cf |
d0 |
ef |
aa |
fb |
43 |
4d |
33 |
85 |
45 |
f9 |
02 |
7f |
50 |
3c |
9f |
a8 |
51 |
a3 |
40 |
8f |
92 |
9d |
38 |
f5 |
bc |
b6 |
da |
21 |
10 |
ff |
f3 |
d2 |
cd |
0c |
13 |
ec |
5f |
97 |
44 |
17 |
c4 |
a7 |
7e |
3d |
64 |
5d |
19 |
73 |
60 |
81 |
4f |
dc |
22 |
2a |
90 |
88 |
46 |
ee |
b8 |
14 |
de |
5e |
0b |
db |
e0 |
32 |
3a |
0a |
49 |
06 |
24 |
5c |
c2 |
d3 |
ac |
62 |
91 |
95 |
e4 |
79 |
e7 |
c8 |
37 |
6d |
8d |
d5 |
4e |
a9 |
6c |
56 |
f4 |
ea |
65 |
7a |
ae |
08 |
ba |
78 |
25 |
2e |
1c |
a6 |
b4 |
c6 |
e8 |
dd |
74 |
1f |
4b |
bd |
8b |
8a |
70 |
3e |
b5 |
66 |
48 |
03 |
f6 |
0e |
61 |
35 |
57 |
b9 |
86 |
c1 |
1d |
9e |
e1 |
f8 |
98 |
11 |
69 |
d9 |
8e |
94 |
9b |
1e |
87 |
e9 |
ce |
55 |
28 |
df |
8c |
a1 |
89 |
0d |
bf |
e6 |
42 |
68 |
41 |
99 |
2d |
0f |
b0 |
54 |
bb |
16 |
/trunk/aes_c_3/mem/gfmult_2.mem
0,0 → 1,256
00000000 |
00000010 |
00000100 |
00000110 |
00001000 |
00001010 |
00001100 |
00001110 |
00010000 |
00010010 |
00010100 |
00010110 |
00011000 |
00011010 |
00011100 |
00011110 |
00100000 |
00100010 |
00100100 |
00100110 |
00101000 |
00101010 |
00101100 |
00101110 |
00110000 |
00110010 |
00110100 |
00110110 |
00111000 |
00111010 |
00111100 |
00111110 |
01000000 |
01000010 |
01000100 |
01000110 |
01001000 |
01001010 |
01001100 |
01001110 |
01010000 |
01010010 |
01010100 |
01010110 |
01011000 |
01011010 |
01011100 |
01011110 |
01100000 |
01100010 |
01100100 |
01100110 |
01101000 |
01101010 |
01101100 |
01101110 |
01110000 |
01110010 |
01110100 |
01110110 |
01111000 |
01111010 |
01111100 |
01111110 |
10000000 |
10000010 |
10000100 |
10000110 |
10001000 |
10001010 |
10001100 |
10001110 |
10010000 |
10010010 |
10010100 |
10010110 |
10011000 |
10011010 |
10011100 |
10011110 |
10100000 |
10100010 |
10100100 |
10100110 |
10101000 |
10101010 |
10101100 |
10101110 |
10110000 |
10110010 |
10110100 |
10110110 |
10111000 |
10111010 |
10111100 |
10111110 |
11000000 |
11000010 |
11000100 |
11000110 |
11001000 |
11001010 |
11001100 |
11001110 |
11010000 |
11010010 |
11010100 |
11010110 |
11011000 |
11011010 |
11011100 |
11011110 |
11100000 |
11100010 |
11100100 |
11100110 |
11101000 |
11101010 |
11101100 |
11101110 |
11110000 |
11110010 |
11110100 |
11110110 |
11111000 |
11111010 |
11111100 |
11111110 |
00011011 |
00011001 |
00011111 |
00011101 |
00010011 |
00010001 |
00010111 |
00010101 |
00001011 |
00001001 |
00001111 |
00001101 |
00000011 |
00000001 |
00000111 |
00000101 |
00111011 |
00111001 |
00111111 |
00111101 |
00110011 |
00110001 |
00110111 |
00110101 |
00101011 |
00101001 |
00101111 |
00101101 |
00100011 |
00100001 |
00100111 |
00100101 |
01011011 |
01011001 |
01011111 |
01011101 |
01010011 |
01010001 |
01010111 |
01010101 |
01001011 |
01001001 |
01001111 |
01001101 |
01000011 |
01000001 |
01000111 |
01000101 |
01111011 |
01111001 |
01111111 |
01111101 |
01110011 |
01110001 |
01110111 |
01110101 |
01101011 |
01101001 |
01101111 |
01101101 |
01100011 |
01100001 |
01100111 |
01100101 |
10011011 |
10011001 |
10011111 |
10011101 |
10010011 |
10010001 |
10010111 |
10010101 |
10001011 |
10001001 |
10001111 |
10001101 |
10000011 |
10000001 |
10000111 |
10000101 |
10111011 |
10111001 |
10111111 |
10111101 |
10110011 |
10110001 |
10110111 |
10110101 |
10101011 |
10101001 |
10101111 |
10101101 |
10100011 |
10100001 |
10100111 |
10100101 |
11011011 |
11011001 |
11011111 |
11011101 |
11010011 |
11010001 |
11010111 |
11010101 |
11001011 |
11001001 |
11001111 |
11001101 |
11000011 |
11000001 |
11000111 |
11000101 |
11111011 |
11111001 |
11111111 |
11111101 |
11110011 |
11110001 |
11110111 |
11110101 |
11101011 |
11101001 |
11101111 |
11101101 |
11100011 |
11100001 |
11100111 |
11100101 |
/trunk/aes_c_3/mem/gfmult_3.mem
0,0 → 1,256
00000000 |
00000011 |
00000110 |
00000101 |
00001100 |
00001111 |
00001010 |
00001001 |
00011000 |
00011011 |
00011110 |
00011101 |
00010100 |
00010111 |
00010010 |
00010001 |
00110000 |
00110011 |
00110110 |
00110101 |
00111100 |
00111111 |
00111010 |
00111001 |
00101000 |
00101011 |
00101110 |
00101101 |
00100100 |
00100111 |
00100010 |
00100001 |
01100000 |
01100011 |
01100110 |
01100101 |
01101100 |
01101111 |
01101010 |
01101001 |
01111000 |
01111011 |
01111110 |
01111101 |
01110100 |
01110111 |
01110010 |
01110001 |
01010000 |
01010011 |
01010110 |
01010101 |
01011100 |
01011111 |
01011010 |
01011001 |
01001000 |
01001011 |
01001110 |
01001101 |
01000100 |
01000111 |
01000010 |
01000001 |
11000000 |
11000011 |
11000110 |
11000101 |
11001100 |
11001111 |
11001010 |
11001001 |
11011000 |
11011011 |
11011110 |
11011101 |
11010100 |
11010111 |
11010010 |
11010001 |
11110000 |
11110011 |
11110110 |
11110101 |
11111100 |
11111111 |
11111010 |
11111001 |
11101000 |
11101011 |
11101110 |
11101101 |
11100100 |
11100111 |
11100010 |
11100001 |
10100000 |
10100011 |
10100110 |
10100101 |
10101100 |
10101111 |
10101010 |
10101001 |
10111000 |
10111011 |
10111110 |
10111101 |
10110100 |
10110111 |
10110010 |
10110001 |
10010000 |
10010011 |
10010110 |
10010101 |
10011100 |
10011111 |
10011010 |
10011001 |
10001000 |
10001011 |
10001110 |
10001101 |
10000100 |
10000111 |
10000010 |
10000001 |
10011011 |
10011000 |
10011101 |
10011110 |
10010111 |
10010100 |
10010001 |
10010010 |
10000011 |
10000000 |
10000101 |
10000110 |
10001111 |
10001100 |
10001001 |
10001010 |
10101011 |
10101000 |
10101101 |
10101110 |
10100111 |
10100100 |
10100001 |
10100010 |
10110011 |
10110000 |
10110101 |
10110110 |
10111111 |
10111100 |
10111001 |
10111010 |
11111011 |
11111000 |
11111101 |
11111110 |
11110111 |
11110100 |
11110001 |
11110010 |
11100011 |
11100000 |
11100101 |
11100110 |
11101111 |
11101100 |
11101001 |
11101010 |
11001011 |
11001000 |
11001101 |
11001110 |
11000111 |
11000100 |
11000001 |
11000010 |
11010011 |
11010000 |
11010101 |
11010110 |
11011111 |
11011100 |
11011001 |
11011010 |
01011011 |
01011000 |
01011101 |
01011110 |
01010111 |
01010100 |
01010001 |
01010010 |
01000011 |
01000000 |
01000101 |
01000110 |
01001111 |
01001100 |
01001001 |
01001010 |
01101011 |
01101000 |
01101101 |
01101110 |
01100111 |
01100100 |
01100001 |
01100010 |
01110011 |
01110000 |
01110101 |
01110110 |
01111111 |
01111100 |
01111001 |
01111010 |
00111011 |
00111000 |
00111101 |
00111110 |
00110111 |
00110100 |
00110001 |
00110010 |
00100011 |
00100000 |
00100101 |
00100110 |
00101111 |
00101100 |
00101001 |
00101010 |
00001011 |
00001000 |
00001101 |
00001110 |
00000111 |
00000100 |
00000001 |
00000010 |
00010011 |
00010000 |
00010101 |
00010110 |
00011111 |
00011100 |
00011001 |
00011010 |