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Rev 2 → Rev 3

/testbench/test_rom.v
0,0 → 1,39
`timescale 1ns / 1ps
`define P 20
 
 
module test_rom;
 
// Inputs
reg clk;
reg [9:0] addr;
 
// Outputs
wire [31:0] out;
 
// Instantiate the Unit Under Test (UUT)
rom uut (
.clk(clk),
.addr(addr),
.out(out)
);
 
initial begin
// Initialize Inputs
clk = 0;
addr = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#`P;
@ (negedge clk);
addr = 2; #`P;
#`P;
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
endmodule
 
/testbench/test_ram.v
0,0 → 1,55
`timescale 1ns / 1ps
`define P 20
 
module test_ram;
 
// Inputs
reg clk;
reg a_wr;
reg [6:0] a_addr;
reg [197:0] a_din;
reg b_wr;
reg [6:0] b_addr;
reg [197:0] b_din;
 
// Outputs
wire [197:0] a_dout;
wire [197:0] b_dout;
 
// Instantiate the Unit Under Test (UUT)
ram uut (
.clk(clk),
.a_wr(a_wr),
.a_addr(a_addr),
.a_din(a_din),
.a_dout(a_dout),
.b_wr(b_wr),
.b_addr(b_addr),
.b_din(b_din),
.b_dout(b_dout)
);
 
initial begin
// Initialize Inputs
clk = 0;
a_wr = 0;
a_addr = 0;
a_din = 0;
b_wr = 0;
b_addr = 0;
b_din = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
a_addr = 1;
#(`P*2);
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
endmodule
 
/testbench/test_tiny_ram.v
0,0 → 1,78
`timescale 1ns / 1ps
 
`define P 20 // clock period
 
module test_tiny_ram;
 
// Inputs
reg clk;
reg reset;
reg sel;
reg [6:0] addr;
reg w;
reg [197:0] data;
 
// Outputs
wire [197:0] out;
wire done;
 
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// write
sel = 1; w = 1;
data = 198'h115a25886512165251569195908560596a6695612620504191;
addr = 0;
#(`P);
data = 198'h1559546442405a181195655549614540592955a15a26984015;
addr = 3;
#(`P);
// not write
w = 0;
data = 198'h12222222222222222222222222222222222222222222222222;
addr = 3;
#(`P);
// read
sel = 1; w = 0;
addr = 0;
#(`P);
if (out !== 198'h115a25886512165251569195908560596a6695612620504191)
$display("E");
 
addr = 3;
#(`P);
if (out !== 198'h1559546442405a181195655549614540592955a15a26984015)
$display("E");
 
#(`P);
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
endmodule
 
/testbench/test_pe.v
0,0 → 1,99
`timescale 1ns / 1ps
`define P 20
 
module test_PE;
 
// Inputs
reg clk;
reg reset;
reg [10:0] ctrl;
reg [197:0] d0;
reg [193:0] d1;
reg [193:0] d2;
reg [193:0] wish;
 
// Outputs
wire [193:0] out;
 
// Instantiate the Unit Under Test (UUT)
PE uut (
.clk(clk),
.reset(reset),
.ctrl(ctrl),
.d0(d0),
.d1(d1),
.d2(d2),
.out(out)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
ctrl = 0;
d0 = 0;
d1 = 0;
d2 = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// test mult
d0 = 194'h15a25886512165251569195908560596a6695612620504191;
d1 = 194'h159546442405a181195655549614540592955a15a26984015;
d2 = d1;
wish = 194'h21019120440545215a1462a194a24a6019441081402410969;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b00000_111111; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
// test cubic
d0 = {6'b10101, 192'd0};
d1 = 194'h0894286a45940549565566512aa04a15558406850485454a4;
d2 = d1;
wish = 194'h1049480a48a0855a494855810160a90956659914560616652;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=1; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
// test add
d0 = {6'b101, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h16954a129284915a928a9916a4954141659a96092a11a2165;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
 
// test sub
d0 = {6'b1001, 192'd0};
d1 = 194'h0994544a41588446516618a14691a545542521a4158868428;
d2 = 194'h1901269451681914415481656104980811a5a555155546949;
wish = 194'h209661a62020aa6210125a481599194946404852006625aa2;
@(negedge clk);
reset=1;#`P reset=0;
ctrl=11'b11111_000000; #`P;
ctrl=11'b10001; #(33*`P);
ctrl=0; #`P;
if(out !== wish) $display("E");
 
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
endmodule
 
/testbench/test_fsm.v
0,0 → 1,64
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_FSM;
 
// Inputs
reg clk;
reg reset;
reg [25:0] rom_q;
 
// Outputs
wire [8:0] rom_addr;
wire [5:0] ram_a_addr;
wire [5:0] ram_b_addr;
wire ram_b_w;
wire [10:0] pe;
wire done;
 
// Instantiate the Unit Under Test (UUT)
FSM uut (
.clk(clk),
.reset(reset),
.rom_addr(rom_addr),
.rom_q(rom_q),
.ram_a_addr(ram_a_addr),
.ram_b_addr(ram_b_addr),
.ram_b_w(ram_b_w),
.pe(pe),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#(`P/2); reset = 1; #(`P); reset = 0;
@(posedge done);
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
/* rom code format
* wire [5:0] dest, src1, src2, times; wire [1:0] op;
* assign {dest, src1, op, times, src2} = rom_q;
*/
parameter ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
 
always @ (posedge clk)
case(rom_addr)
0: rom_q <= {6'd10, 6'd11, ADD, 6'd1, 6'd12};
1: rom_q <= {6'd20, 6'd21, SUB, 6'd1, 6'd22};
2: rom_q <= {6'd30, 6'd31, CUBIC, 6'd5, 6'd32};
3: rom_q <= {6'd40, 6'd41, MULT, 6'd33, 6'd42};
default: rom_q <= 0;
endcase
endmodule
 
/testbench/test_const.v
0,0 → 1,57
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_const;
 
// Inputs
reg clk;
reg [4:0] addr;
 
// Outputs
wire [197:0] out;
wire effective;
reg [197:0] w_out;
reg w_effective;
// Instantiate the Unit Under Test (UUT)
const uut (
.clk(clk),
.addr(addr),
.out(out),
.effective(effective)
);
 
initial begin
// Initialize Inputs
addr = 0; clk = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
addr = 1; w_out = 0; w_effective = 1;
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {4'b0101, 194'd0};
#(`P); check;
addr = 8; w_out = {4'b0110, 194'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 192'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
 
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E");
end
endtask
endmodule
 
/testbench/test_tiny_cmd.v
0,0 → 1,98
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_tiny_cmd;
 
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [197:0] data;
 
// Outputs
wire [197:0] out;
wire done;
 
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// init x, y
#(`P/2); #(`P);
// addr[3] = x
sel = 1; w = 1;
addr = 0;
data = 0;
#(`P); // without this write, next write will fail. bug ? :(
addr = 3;
data = 194'h288162298554054820552a05426081a1842886a58916a6249;
#(`P);
// addr[6] = x
addr = 6;
#(`P);
// addr[5] = y
data = 194'h2895955069089214054596a189a4420556589054140941695;
addr = 5;
#(`P);
// addr[7] = y
addr = 7;
#(`P);
sel = 0;
@(posedge clk);
reset = 1; #(`P*3); reset = 0; // shorter reset signal makes FSM direct done. bug :(
@(posedge done);
sel = 1; w = 0;
addr = 0; #(`P); // first read fails. bug ?
addr = 3; #(`P);
$display("xp = %h", out);
addr = 5; #(`P);
$display("yp = %h", out);
addr = 6; #(`P);
$display("xq = %h", out);
addr = 7; #(`P);
$display("yq = %h", out);
addr = 9; #(`P);
$display("t0 = %h", out);
addr = 10; #(`P);
$display("t1 = %h", out);
addr = 11; #(`P);
$display("t2 = %h", out);
addr = 12; #(`P);
$display("t3 = %h", out);
addr = 13; #(`P);
$display("t4 = %h", out);
addr = 14; #(`P);
$display("t5 = %h", out);
$finish;
end
 
initial #100 forever #(`P/2) clk = ~clk;
endmodule
 
/testbench/test_tiny_cubic.v
0,0 → 1,84
`timescale 1ns / 1ps
`define P 20 // clock period
 
module test_tiny_cubic;
 
// Inputs
reg clk;
reg reset;
reg sel;
reg [6:0] addr;
reg w;
reg [197:0] data;
 
// Outputs
wire [197:0] out;
wire done;
 
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
write(0, {6'b010101, 192'd0}); // cmd for cubic
write(1, {6'b000101, 192'd0}); // cmd for addition
write(2, {6'b001001, 192'd0}); // cmd for subtraction
write(3, 0); // the data of zero
write(4, 1); // the data of one
read(0);
read(1);
read(2);
read(3);
read(4);
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [6:0] adr;
input [197:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
 
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask;
endmodule
 
/rtl/rom.v
17,25 → 17,431
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
/*
* the $ctrl$ field in the first cmd is the running number of the second command.
* 0: rom_q <= {6'd1, 1'd0, 7'd0, 7'd0, 11'd0}; // repeat 1 time
* 1: rom_q <= {6'd2, 1'd1, 7'd2, 7'd3, 11'd4}; // repeat 1 times
* 2: rom_q <= {6'd3, 1'd0, 7'd5, 7'd6, 11'd7}; // repeat 2 times
* 3: rom_q <= {6'd1, 1'd1, 7'd8, 7'd9, 11'ha}; // repeat 3 time
* the number one command runs two times. don't put valid command there :)
*/
module rom (clk, addr, out);
input clk;
input [9:0] addr;
output reg [31:0] out;
input [8:0] addr;
output reg [25:0] out;
always @(posedge clk)
case (addr) // test addr[3] = addr[2] + addr[2]
0: out <= {6'd1, 1'd0, 7'd0, 7'd0, 11'd0}; // blank
1: out <= {6'd1, 1'd0, 7'd0, 7'd2, 11'b0}; // read addr[2]
2: out <= {6'd2, 1'd0, 7'd4, 7'd2, 11'b11000000000}; // load d1, read addr[2], command_add
3: out <= {6'd1, 1'd1, 7'd3, 7'd0, 11'b00111010001}; // load d0, d2, d3
default: out <= 0;
endcase
case (addr)
0: out <= 26'h30c042;
1: out <= 26'h514045;
2: out <= 26'h61a041;
3: out <= 26'h71e041;
4: out <= 26'hc046;
5: out <= 26'h1603840;
6: out <= 26'h1702041;
7: out <= 26'h1717857;
8: out <= 26'h1817847;
9: out <= 26'h1963847;
10: out <= 26'hf5d059;
11: out <= 26'hf3d045;
12: out <= 26'h1763845;
13: out <= 26'h185f840;
14: out <= 26'h161f856;
15: out <= 26'h1160056;
16: out <= 26'h1144051;
17: out <= 26'h1214045;
18: out <= 26'h131f840;
19: out <= 26'h135d053;
20: out <= 26'h1404041;
21: out <= 26'h151c047;
22: out <= 26'h3e041;
23: out <= 26'h1646041;
24: out <= 26'h174a041;
25: out <= 26'h184e041;
26: out <= 26'h1952041;
27: out <= 26'h1a56041;
28: out <= 26'hf00057;
29: out <= 26'hf3c059;
30: out <= 26'h1158058;
31: out <= 26'h114405a;
32: out <= 26'h1144051;
33: out <= 26'h125d059;
34: out <= 26'h1369058;
35: out <= 26'h1464041;
36: out <= 26'h156805a;
37: out <= 26'h61a081;
38: out <= 26'h619042;
39: out <= 26'h71e081;
40: out <= 26'h71c047;
41: out <= 26'hc046;
42: out <= 26'h1600040;
43: out <= 26'h1717847;
44: out <= 26'h5b840;
45: out <= 26'h1800056;
46: out <= 26'h1901056;
47: out <= 26'h1a3c054;
48: out <= 26'h1b68052;
49: out <= 26'h1c69052;
50: out <= 26'h1d3d054;
51: out <= 26'h1e75053;
52: out <= 26'h1d74053;
53: out <= 26'h1f44055;
54: out <= 26'h207c053;
55: out <= 26'h217d053;
56: out <= 26'h225c056;
57: out <= 26'h165d056;
58: out <= 26'h2345055;
59: out <= 26'h248c052;
60: out <= 26'h238d052;
61: out <= 26'h2560057;
62: out <= 26'h266c060;
63: out <= 26'h2700062;
64: out <= 26'h2878064;
65: out <= 26'h2964057;
66: out <= 26'h2a70061;
67: out <= 26'h2b00056;
68: out <= 26'h2c74063;
69: out <= 26'h186385b;
70: out <= 26'h1b97866;
71: out <= 26'h205f860;
72: out <= 26'h1e0385e;
73: out <= 26'h259f868;
74: out <= 26'h228b864;
75: out <= 26'h196785c;
76: out <= 26'h1ca786a;
77: out <= 26'h175f861;
78: out <= 26'h385d;
79: out <= 26'h1daf86c;
80: out <= 26'h165b863;
81: out <= 26'h2160065;
82: out <= 26'h238005d;
83: out <= 26'h2481057;
84: out <= 26'h2665058;
85: out <= 26'h175c060;
86: out <= 26'h1789057;
87: out <= 26'h175c056;
88: out <= 26'h1864058;
89: out <= 26'h186105e;
90: out <= 26'h1861040;
91: out <= 26'h198d061;
92: out <= 26'h196505e;
93: out <= 26'h1664056;
94: out <= 26'h1984063;
95: out <= 26'h196505b;
96: out <= 26'h1964062;
97: out <= 26'h64040;
98: out <= 26'h1990066;
99: out <= 26'h1e91066;
100: out <= 26'h1e7805c;
101: out <= 26'h1e7905b;
102: out <= 26'h205c058;
103: out <= 26'h175d058;
104: out <= 26'h175c05c;
105: out <= 26'h175c05b;
106: out <= 26'h175d065;
107: out <= 26'h175d05d;
108: out <= 26'hf59052;
109: out <= 26'h1101053;
110: out <= 26'h65052;
111: out <= 26'h1054;
112: out <= 26'h1679053;
113: out <= 26'h1659055;
114: out <= 26'h148105a;
115: out <= 26'h155d05f;
116: out <= 26'h1201041;
117: out <= 26'h1359041;
118: out <= 26'h93e041;
119: out <= 26'h3c052;
120: out <= 26'h54;
121: out <= 26'h163f84f;
122: out <= 26'h173f852;
123: out <= 26'h184b854;
124: out <= 26'h1953854;
125: out <= 26'h3840;
126: out <= 26'h175c058;
127: out <= 26'h1859058;
128: out <= 26'h1965057;
129: out <= 26'h57;
130: out <= 26'h1056;
131: out <= 26'h1644053;
132: out <= 26'h1658055;
133: out <= 26'h1747851;
134: out <= 26'h1a47853;
135: out <= 26'h1b4f855;
136: out <= 26'h1c57855;
137: out <= 26'h165b856;
138: out <= 26'h1a6805b;
139: out <= 26'h1b5d05b;
140: out <= 26'h1c7105a;
141: out <= 26'h165805a;
142: out <= 26'h1659057;
143: out <= 26'h173c052;
144: out <= 26'h1a3c054;
145: out <= 26'h1d48054;
146: out <= 26'h1e44053;
147: out <= 26'h1f44055;
148: out <= 26'h204c055;
149: out <= 26'h213f851;
150: out <= 26'h224b853;
151: out <= 26'h2353855;
152: out <= 26'h175f85e;
153: out <= 26'h1a6b85f;
154: out <= 26'h1d77860;
155: out <= 26'h1e85062;
156: out <= 26'h1f79063;
157: out <= 26'h1f7c05d;
158: out <= 26'h175d05e;
159: out <= 26'h175c05d;
160: out <= 26'h1a6905e;
161: out <= 26'h1d6105b;
162: out <= 26'h1e6505c;
163: out <= 26'h2001056;
164: out <= 26'h186005b;
165: out <= 26'h196405c;
166: out <= 26'h56;
167: out <= 26'h1660059;
168: out <= 26'h1b61040;
169: out <= 26'h1c65058;
170: out <= 26'h210105c;
171: out <= 26'h2263858;
172: out <= 26'h2367859;
173: out <= 26'h2403840;
174: out <= 26'h1963859;
175: out <= 26'h1863840;
176: out <= 26'h3856;
177: out <= 26'h168b85b;
178: out <= 26'h1b8f85c;
179: out <= 26'h1c93861;
180: out <= 26'h165805b;
181: out <= 26'h165805c;
182: out <= 26'h1b58041;
183: out <= 26'h1c6e041;
184: out <= 26'h1b6f85c;
185: out <= 26'h1c6e081;
186: out <= 26'h1b6f85c;
187: out <= 26'h1c6e101;
188: out <= 26'h1b6f85c;
189: out <= 26'h1c6e201;
190: out <= 26'h1b6f85c;
191: out <= 26'h1c6e401;
192: out <= 26'h1b6f85c;
193: out <= 26'h1c6e801;
194: out <= 26'h1c6f85c;
195: out <= 26'h1c72801;
196: out <= 26'h1b6f85c;
197: out <= 26'h1b6e041;
198: out <= 26'h166f856;
199: out <= 26'h166f856;
200: out <= 26'h1b8d064;
201: out <= 26'h1c8905b;
202: out <= 26'h71040;
203: out <= 26'h1991059;
204: out <= 26'h186d058;
205: out <= 26'h5b840;
206: out <= 26'h195b859;
207: out <= 26'h165b858;
208: out <= 26'h187405e;
209: out <= 26'h1b74060;
210: out <= 26'h1c78060;
211: out <= 26'h2100059;
212: out <= 26'h2200056;
213: out <= 26'h2364056;
214: out <= 26'h1d77840;
215: out <= 26'h1e7b859;
216: out <= 26'h2083856;
217: out <= 26'h1863861;
218: out <= 26'h1b6f862;
219: out <= 26'h1c73863;
220: out <= 26'h1d7505e;
221: out <= 26'h1e75060;
222: out <= 26'h1e7805c;
223: out <= 26'h186105d;
224: out <= 26'h186005c;
225: out <= 26'h1b6d05d;
226: out <= 26'h1c7c057;
227: out <= 26'h1d7c05a;
228: out <= 26'h205c05a;
229: out <= 26'h2100059;
230: out <= 26'h2200056;
231: out <= 26'h2364056;
232: out <= 26'h7f840;
233: out <= 26'h175f859;
234: out <= 26'h166b856;
235: out <= 26'h1973861;
236: out <= 26'h1a77862;
237: out <= 26'h1c83863;
238: out <= 26'h1057;
239: out <= 26'h1601056;
240: out <= 26'h165805c;
241: out <= 26'h1765040;
242: out <= 26'h175c05c;
243: out <= 26'h69040;
244: out <= 26'h1978056;
245: out <= 26'h1a60057;
246: out <= 26'h1c6d040;
247: out <= 26'h1d7b85b;
248: out <= 26'h1f5b840;
249: out <= 26'h1b6385b;
250: out <= 26'h5f840;
251: out <= 26'h206785c;
252: out <= 26'h165b858;
253: out <= 26'h177b857;
254: out <= 26'h186785a;
255: out <= 26'h196b85c;
256: out <= 26'h1a58057;
257: out <= 26'h1869058;
258: out <= 26'h1a6c040;
259: out <= 26'h1a6805a;
260: out <= 26'h105b;
261: out <= 26'h1b7d05d;
262: out <= 26'h1b6c060;
263: out <= 26'h1c0805d;
264: out <= 26'h1c7005f;
265: out <= 26'h1c7005a;
266: out <= 26'h1659057;
267: out <= 26'h165805b;
268: out <= 26'h1769058;
269: out <= 26'h1d64040;
270: out <= 26'h1b7505b;
271: out <= 26'h1860058;
272: out <= 26'h186105a;
273: out <= 26'h64040;
274: out <= 26'h1972041;
275: out <= 26'h1a5a041;
276: out <= 26'h1d5e041;
277: out <= 26'h1e6e041;
278: out <= 26'h1f62041;
279: out <= 26'h2002041;
280: out <= 26'h196405d;
281: out <= 26'h196405f;
282: out <= 26'h1a6805a;
283: out <= 26'h1a6905e;
284: out <= 26'h1a69060;
285: out <= 26'h1d7505f;
286: out <= 26'h1e8105e;
287: out <= 26'h2080060;
288: out <= 26'h1966041;
289: out <= 26'h1a6a041;
290: out <= 26'h1d76041;
291: out <= 26'h1e7a041;
292: out <= 26'h1f7e041;
293: out <= 26'h2082041;
294: out <= 26'h196405d;
295: out <= 26'h196405f;
296: out <= 26'h1a6805a;
297: out <= 26'h1a6905e;
298: out <= 26'h1a69060;
299: out <= 26'h1d7505f;
300: out <= 26'h1e8105e;
301: out <= 26'h2080060;
302: out <= 26'h2170056;
303: out <= 26'h225c05b;
304: out <= 26'h2361040;
305: out <= 26'h2473858;
306: out <= 26'h255b840;
307: out <= 26'h185f858;
308: out <= 26'h6f840;
309: out <= 26'h2687863;
310: out <= 26'h165b857;
311: out <= 26'h177385b;
312: out <= 26'h1b87862;
313: out <= 26'h1c8b863;
314: out <= 26'h2158057;
315: out <= 26'h1b8505b;
316: out <= 26'h2160040;
317: out <= 26'h2184061;
318: out <= 26'h1058;
319: out <= 26'h1895064;
320: out <= 26'h1860066;
321: out <= 26'h2208064;
322: out <= 26'h2288065;
323: out <= 26'h2288061;
324: out <= 26'h1659057;
325: out <= 26'h1658058;
326: out <= 26'h178505b;
327: out <= 26'h2370040;
328: out <= 26'h188d058;
329: out <= 26'h1b6c05b;
330: out <= 26'h1b6d061;
331: out <= 26'h70040;
332: out <= 26'h1a6805a;
333: out <= 26'h1c7805e;
334: out <= 26'h1e80060;
335: out <= 26'h206405f;
336: out <= 26'h218005d;
337: out <= 26'h208105d;
338: out <= 26'h238805b;
339: out <= 26'h248c057;
340: out <= 26'h238d057;
341: out <= 26'h196505f;
342: out <= 26'h256505c;
343: out <= 26'h196405c;
344: out <= 26'h228905b;
345: out <= 26'h2689058;
346: out <= 26'h2288058;
347: out <= 26'h276805e;
348: out <= 26'h289c05c;
349: out <= 26'h1c9d05c;
350: out <= 26'h2758040;
351: out <= 26'h299c058;
352: out <= 26'h189d058;
353: out <= 26'h1a6905e;
354: out <= 26'h276805d;
355: out <= 26'h1a6905d;
356: out <= 26'h1659040;
357: out <= 26'h1d58057;
358: out <= 26'h1659057;
359: out <= 26'h1784068;
360: out <= 26'h2a90069;
361: out <= 26'h2b94067;
362: out <= 26'h2c9805d;
363: out <= 26'h2d8005c;
364: out <= 26'h2e8c058;
365: out <= 26'h2f6405a;
366: out <= 26'h3088056;
367: out <= 26'h317c05e;
368: out <= 26'h326c040;
369: out <= 26'h2187864;
370: out <= 26'h175f86a;
371: out <= 26'h24a3869;
372: out <= 26'h2597866;
373: out <= 26'h26af86c;
374: out <= 26'h1d9f85d;
375: out <= 26'h2083863;
376: out <= 26'h23b786e;
377: out <= 26'h1873858;
378: out <= 26'h1967862;
379: out <= 26'h1cbf870;
380: out <= 26'h166b856;
381: out <= 26'h1a7f85b;
382: out <= 26'h1bc7872;
383: out <= 26'h7b840;
384: out <= 26'h1e84066;
385: out <= 26'h1e7805a;
386: out <= 26'h1f9005c;
387: out <= 26'h1f7c040;
388: out <= 26'h1a8005a;
389: out <= 26'h60040;
390: out <= 26'h40;
391: out <= 26'h188c05b;
392: out <= 26'h2000064;
393: out <= 26'h2269061;
394: out <= 26'h1064;
395: out <= 26'h5d;
396: out <= 26'h56;
397: out <= 26'h1a68061;
398: out <= 26'h1a69065;
399: out <= 26'h1a69059;
400: out <= 26'h97d05e;
401: out <= 26'h925065;
402: out <= 26'h924056;
403: out <= 26'ha7805f;
404: out <= 26'ha29057;
405: out <= 26'ha2805d;
406: out <= 26'ha28059;
407: out <= 26'ha2905b;
408: out <= 26'hb80062;
409: out <= 26'hc81062;
410: out <= 26'hc30058;
411: out <= 26'hc31057;
412: out <= 26'hd0005a;
413: out <= 26'he0105a;
414: out <= 26'he38058;
415: out <= 26'he38057;
416: out <= 26'he39066;
417: out <= 26'he3905c;
default: out <= 0;
endcase
endmodule
/rtl/ram.v
17,48 → 17,48
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
module ram #(
parameter DATA = 198,
parameter ADDR = 7
) (
input clk,
module ram #(
parameter DATA = 198,
parameter ADDR = 6
) (
input clk,
 
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
 
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
 
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
 
initial begin : init
integer i;
for(i = 0; i < 2**ADDR; i = i + 1)
for(i = 0; i < (2**ADDR); i = i + 1)
mem[i] = 0;
end
 
// Port A
always @(posedge clk) begin
if(a_wr) begin
mem[a_addr] <= a_din;
end
a_dout <= mem[a_addr];
 
// Port A
always @(posedge clk) begin
if(a_wr) begin
mem[a_addr] <= a_din;
end
a_dout <= mem[a_addr];
end
 
// Port B
always @(posedge clk) begin
if(b_wr) begin
mem[b_addr] <= b_din;
end
b_dout <= mem[b_addr];
end
 
endmodule
// Port B
always @(posedge clk) begin
if(b_wr) begin
mem[b_addr] <= b_din;
end
b_dout <= mem[b_addr];
end
 
endmodule
/rtl/tiny.v
20,7 → 20,7
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [6:0] addr;
input [5:0] addr;
input w;
input [197:0] data;
output [197:0] out;
27,9 → 27,9
output done;
 
/* for FSM */
wire [6:0] fsm_addr;
wire [5:0] fsm_addr;
/* for RAM */
wire [6:0] ram_a_addr, ram_b_addr;
wire [5:0] ram_a_addr, ram_b_addr;
wire [197:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [197:0] ram_a_data_out, ram_b_data_out;
39,8 → 39,8
/* for mux */
wire [197:0] mux0_out, mux1_out;
/* for ROM */
wire [9:0] rom_addr;
wire [31:0] rom_q;
wire [8:0] rom_addr;
wire [25:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
56,7 → 56,7
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr, ram_b_data_in, ram_b_data_out);
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
mux
mux0 (ram_a_data_out, const0_out, const0_effective, mux0_out),
mux1 (ram_b_data_out, const1_out, const1_effective, mux1_out);
68,10 → 68,10
 
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [6:0] addr_in;
input [6:0] addr_fsm_in;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [6:0] addr_out;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
/rtl/pe.v
80,6 → 80,7
always @ (posedge clk)
if (reset) R3 <= 0;
else if (c10) R3 <= ad2;
else R3 <= 0; /* change */
assign out = R3;
endmodule
 
/rtl/fsm.v
1,75 → 1,158
/*
Copyright 2011,2012 City University of Hong Kong
Homer Hsing is the author.
Copyright 2012 Homer Hsing
This file is part of Tate Bilinear Pairing Core.
This file is part of Tiny Tate Bilinear Pairing Core.
 
Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
Tiny Tate Bilinear Pairing Core is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
Tiny Tate Bilinear Pairing Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
 
You should have received a copy of the GNU Lesser General Public License
along with Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
along with Tiny Tate Bilinear Pairing Core. If not, see http://www.gnu.org/licenses/lgpl.txt
*/
 
/* FSM: finite state machine
* halt if $ctrl == 0$
*/
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
input clk;
input reset;
output [9:0] rom_addr; /* command id */
input [31:0] rom_q; /* command value */
output done;
output [6:0] ram_a_addr; /* a field of $rom_q$ */
output [6:0] ram_b_addr; /* a field of $rom_q$ */
output ram_b_w; /* a field of $rom_q$ */
output [10:0] pe_ctrl; /* a field of $rom_q$ */
output reg [8:0] rom_addr; /* command id. extra bits? */
input [25:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [9:0] rom_addr;
reg [5:0] ctrl; /* in fact a counter */
reg done;
reg [4:0] state;
parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=3;
wire [5:0] dest, src1, src2, times; wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
 
/* I had attempted to avoid finite state machine for a whole day, but I conceded. :) */
parameter S0 = 3'b001, S1 = 3'b010, S2 = 3'b100;
reg [2:0] state;
reg [5:0] count;
always @ (posedge clk)
if (reset)
state<=START;
else
case (state)
START:
state<=READ_SRC1;
READ_SRC1:
state<=READ_SRC2;
READ_SRC2:
if (times==0) state<=DON; else state<=CALC;
CALC:
if (count==1) state<=WAIT;
WAIT:
state<=WRITE;
WRITE:
state<=READ_SRC1;
endcase
 
/* we support two loops with 48 loop times */
parameter LOOP1_START = 22,
LOOP1_END = 117,
LOOP2_START = 280,
LOOP2_END = 293;
reg [46:0] loop1, loop2;
always @ (posedge clk)
if (reset) rom_addr<=0;
else if (state==WAIT)
begin
if(rom_addr == LOOP1_END && loop1[0])
rom_addr <= LOOP1_START;
else if(rom_addr == LOOP2_END && loop2[0])
rom_addr <= LOOP2_START;
else
rom_addr <= rom_addr + 1;
end
always @ (posedge clk)
if (reset) loop1 <= ~0;
else if(state==WAIT && rom_addr==LOOP1_END)
loop1 <= loop1 >> 1;
always @ (posedge clk)
if (reset) loop2 <= ~0;
else if(state==WAIT && rom_addr==LOOP2_END)
loop2 <= loop2 >> 1;
 
always @ (posedge clk)
if (reset)
count<=0;
else if (state==READ_SRC1)
count<=times;
else if (state==CALC)
count<=count-1;
always @ (posedge clk)
if (reset) done<=0;
else if (state==DON) done<=1;
else done<=0;
always @ (state, src1, src2)
case (state)
READ_SRC1: ram_a_addr=src1;
READ_SRC2: ram_a_addr=src2;
default: ram_a_addr=0;
endcase
assign {ram_b_w, ram_b_addr, ram_a_addr, pe_ctrl} = rom_q[25:0];
parameter CMD_ADD=4, CMD_SUB=8, CMD_CUBIC=16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
 
always @ (posedge clk)
if (reset)
begin
state <= S0; rom_addr <= 0;
ctrl <= 0; done <= 0;
end
else
begin
done <= 0;
case (state)
S0:
begin
case (rom_q[31:26])
0: begin state <= S2; done <= 1; end
1: rom_addr <= rom_addr + 1;
default: begin state <= S1; ctrl <= rom_q[31:26]-1; end
endcase
end
S1:
begin
if (ctrl == 1)
begin
rom_addr <= rom_addr + 1;
state <= S0;
end
else
ctrl <= ctrl - 1;
end
endcase
end
case (state)
READ_SRC1:
case (op)
ADD: pe<=11'b11001000000;
SUB: pe<=11'b11001000000;
CUBIC: pe<=11'b11111000000;
MULT: pe<=11'b11110000000;
default: pe<=0;
endcase
READ_SRC2:
case (op)
ADD: pe<=11'b00110000000;
SUB: pe<=11'b00110000000;
CUBIC: pe<=0;
MULT: pe<=11'b00001000000;
default: pe<=0;
endcase
CALC:
case (op)
ADD: pe<=11'b00000010001;
SUB: pe<=11'b00000010001;
CUBIC: pe<=11'b01010000001;
MULT: pe<=11'b00000111111;
default: pe<=0;
endcase
default:
pe<=0;
endcase
 
always @ (state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr=CMD_ADD;
SUB: ram_b_addr=CMD_SUB;
CUBIC: ram_b_addr=CMD_CUBIC;
default: ram_b_addr=0;
endcase
READ_SRC2: ram_b_addr=src2;
WRITE: ram_b_addr=dest;
default: ram_b_addr=0;
endcase
 
assign ram_b_w = (state==WRITE) ? 1 : 0;
endmodule
/rtl/const.v
30,20 → 30,21
*/
module const (clk, addr, out, effective);
input clk;
input [6:0] addr;
input [5:0] addr;
output reg [197:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
7'b1: out <= 0;
7'b10: out <= 1;
7'b100: out <= {6'b000101, 192'd0};
7'b1000: out <= {6'b001001, 192'd0};
7'b10000: out <= {6'b010101, 192'd0};
default: begin out <= 0; effective <= 0; end
endcase
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101, 192'd0};
8: out <= {6'b001001, 192'd0};
16: out <= {6'b010101, 192'd0};
default:
begin out <= 0; effective <= 0; end
endcase
end
endmodule

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