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  • This comparison shows the changes necessary to convert path 
    /tinycpu/trunk/testbench
    from Rev 20 to Rev 21
    ↔ Reverse comparison
  •

Rev 20 → Rev 21

/carryover_tb.vhd
17,10 → 17,19
SegmentIn: in std_logic_vector(7 downto 0);
Addend: in std_logic_vector(7 downto 0); --How much to increase DataIn by (as a signed number). Believe it or not, that's the actual word for what we need.
DataOut: out std_logic_vector(7 downto 0);
SegmentOut: out std_logic_vector(7 downto 0)
SegmentOut: out std_logic_vector(7 downto 0);
Clock: in std_logic
-- Debug: out std_logic_vector(8 downto 0)
);
end component;
component registerfile is
port(
WriteEnable: in regwritetype;
DataIn: in regdatatype;
Clock: in std_logic;
DataOut: out regdatatype
);
end component;
 
--Inputs
32,6 → 41,10
signal DataOut: std_logic_vector(7 downto 0);
signal SegmentOut: std_logic_vector(7 downto 0);
-- signal Debug: std_logic_vector(8 downto 0);
signal regwe: regwritetype;
signal regin: regdatatype;
signal regout: regdatatype;
 
signal Clock: std_logic;
constant clock_period : time := 10 ns;
45,9 → 58,16
Addend => Addend,
SegmentIn => SegmentIn,
DataOut => DataOut,
SegmentOut => SegmentOut
SegmentOut => SegmentOut,
Clock => Clock
-- Debug => Debug
);
regfile: registerfile port map(
WriteEnable => regwe,
DataIn => regin,
Clock => Clock,
DataOut => regout
);
 
-- Clock process definitions
clock_process :process
98,6 → 118,25
SegmentIn <= x"00";
wait for 10 ns;
assert (SegmentOut=x"00" and DataOut = x"FE") report "Carryover when not appropriate case 1" severity error;
--practical register test
regin(0) <= x"10";
regwe(0) <= '1';
wait for 10 ns;
regwe(0) <= '0';
wait for 10 ns;
regwe(0) <= '1';
DataIn <= regout(0);
Addend <= x"02";
SegmentIn <= x"00";
wait for 10 ns;
regin(0) <= DataOut;
wait for 10 ns;
assert(DataOut = x"12") report "practical fail 1" severity error;
DataIn <= regout(0);
regin(0) <= DataOut;
wait for 10 ns;
assert(DataOut = x"14") report "practical fail 2" severity error;
 
-- summary of testbench
assert false
/core_tb.vhd
41,11 → 41,11
signal MemWW: std_logic; --memory writeword
signal MemWE: std_logic; --memory writeenable
signal MemOut: std_logic_vector(15 downto 0);
signal MemIn: std_logic_vector(15 downto 0);
signal MemIn: std_logic_vector(15 downto 0):=x"0000";
--general interface
signal Reset: std_logic; --When this is high, CPU will reset within 1 clock cycles.
signal Reset: std_logic:='0'; --When this is high, CPU will reset within 1 clock cycles.
--Enable: in std_logic; --When this is high, the CPU executes as normal, when low the CPU stops at the next clock cycle(maintaining all state)
signal Hold: std_logic; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
signal Hold: std_logic:='0'; --when high, CPU pauses execution and places Memory interfaces into high impendance state so the memory can be used by other components
signal HoldAck: std_logic; --when high, CPU acknowledged hold and buses are in high Z
--todo: port interface
 
111,7 → 111,7
Reset <= '0';
MemIn <= x"0012"; --mov r0, 0xFF
wait for 10 ns;
wait for 30 ns; --fetcher needs two clock cycles to catch up
assert(MemAddr = x"0100") report "Not fetching from correct start address" severity error;
MemIn <= x"00F1"; --mov r0, 0xF1
wait for 10 ns;
/fetch_tb.vhd
69,7 → 69,7
Enable <= '1';
AddressIn <= x"1234";
DataIn <= x"5321";
wait for 10 ns;
wait for 10 ns;
assert (IROut = x"5321" and AddressOut = x"1234") report "basic operation failure" severity error;
AddressIn <= x"5121";

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