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  • This comparison shows the changes necessary to convert path 
    /tinycpu/trunk
    from Rev 11 to Rev 12
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  •

Rev 11 → Rev 12

/testbench/registerfile_tb.vhd
1,7 → 1,8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.tinycpu.all;
 
ENTITY registerfile_tb IS
END registerfile_tb;
10,35 → 11,21
-- Component Declaration for the Unit Under Test (UUT)
component registerfile
port(
Write1:in std_logic_vector(7 downto 0); --what should be put into the write register
Write2: in std_logic_vector(7 downto 0);
SelRead1:in std_logic_vector(3 downto 0); --select which register to read
SelRead2: in std_logic_vector(3 downto 0); --select second register to read
SelWrite1:in std_logic_vector(3 downto 0); --select which register to write
SelWrite2:in std_logic_vector(3 downto 0);
UseWrite1:in std_logic; --if the register should actually be written to
UseWrite2: in std_logic;
Clock:in std_logic;
Read1:out std_logic_vector(7 downto 0); --register to be read output
Read2:out std_logic_vector(7 downto 0) --register to be read on second output
port(
WriteEnable: in regwritetype;
DataIn: in regdatatype;
Clock: in std_logic;
DataOut: out regdatatype
);
end component;
 
--Inputs
signal Write1 : std_logic_vector(7 downto 0) := (others => '0');
signal Write2 : std_logic_vector(7 downto 0) := (others => '0');
signal SelRead1: std_logic_vector(3 downto 0) := (others => '0');
signal SelRead2: std_logic_vector(3 downto 0) := (others => '0');
signal SelWrite1: std_logic_vector(3 downto 0) := (others => '0');
signal SelWrite2: std_logic_vector(3 downto 0) := (others => '0');
signal UseWrite1: std_logic := '0';
signal UseWrite2: std_logic := '0';
signal WriteEnable : regwritetype := (others => '0');
signal DataIn: regdatatype := (others => "00000000");
 
--Outputs
signal Read1 : std_logic_vector(7 downto 0);
signal Read2 : std_logic_vector(7 downto 0);
signal DataOut: regdatatype := (others => "00000000");
 
signal Clock: std_logic;
constant clock_period : time := 10 ns;
47,17 → 34,10
 
-- Instantiate the Unit Under Test (UUT)
uut: registerfile PORT MAP (
Write1 => Write1,
Write2 => Write2,
SelRead1 => SelRead1,
SelRead2 => SelRead2,
SelWrite1 => SelWrite1,
SelWrite2 => SelWrite2,
UseWrite1 => UseWrite1,
UseWrite2 => UseWrite2,
WriteEnable => WriteEnable,
DataIn => DataIn,
Clock => Clock,
Read1 => Read1,
Read2 => Read2
DataOut => DataOut
);
 
-- Clock process definitions
80,58 → 60,37
wait for clock_period*10;
 
-- case 1
SelWrite1 <= "0000";
Write1 <= "11110000";
UseWrite1 <= '1';
WriteEnable(1) <= '1';
DataIn(1) <= "11110000";
wait for 10 ns;
SelRead1 <= "0000";
UseWrite1 <= '0';
WriteEnable(1) <= '0';
wait for 10 ns;
assert (Read1="11110000") report "Storage error case 1" severity error;
assert (DataOut(1)="11110000") report "Storage error case 1" severity error;
 
-- case 2
SelWrite1 <= "1000";
Write1 <= "11110001";
UseWrite1 <= '1';
WriteEnable(5) <= '1';
DataIn(5) <= "11110001";
wait for 10 ns;
SelRead1 <= "1000";
UseWrite1 <= '0';
WriteEnable(5) <= '0';
wait for 10 ns;
assert (Read1="11110001") report "Storage selector error case 2" severity error;
assert (DataOut(5)="11110001") report "Storage selector error case 2" severity error;
 
-- case 3
SelRead1 <= "0000";
UseWrite1 <= '0';
-- case 3;
wait for 10 ns;
assert (Read1="11110000") report "Storage selector(remembering) error case 3" severity error;
assert (DataOut(1)="11110000") report "Storage selector(remembering) error case 3" severity error;
--case 4
SelWrite1 <= x"0";
SelWrite2 <= x"1";
Write1 <= x"12";
Write2 <= x"34";
UseWrite1 <= '1';
UseWrite2 <= '1';
DataIn(0) <= x"12";
DataIn(1) <= x"34";
WriteEnable(0) <= '1';
WriteEnable(1) <= '1';
wait for 10 ns;
UseWrite1 <= '0';
UseWrite2 <= '0';
SelRead1 <= x"0";
SelRead2 <= x"1";
DataIn(0) <= x"90";
WriteEnable(0) <= '0';
WriteEnable(1) <= '0';
wait for 10 ns;
assert (Read1=x"12" and Read2=x"34") report "simultaneous write and read error case 4" severity error;
assert (DataOut(0)=x"12" and DataOut(1)=x"34") report "simultaneous write and read error case 4" severity error;
 
SelWrite1 <= x"0";
SelWrite2 <= x"0";
Write1 <= x"ff";
Write2 <= x"00";
UseWrite1 <= '1';
UseWrite2 <= '1';
wait for 10 ns;
SelRead1 <= x"0";
UseWrite1 <= '0';
UseWrite2 <= '0';
wait for 10 ns;
assert (Read1=x"ff") report "dual-write error handling error case 5" severity error;
 
 
 
/src/registerfile.vhd
1,5 → 1,5
--registerfile module
--16 registers, dual port for both read and write
--16 registers, read/write port for all registers.
--8 bit registers
 
library IEEE;
6,40 → 6,35
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use work.tinycpu.all;
 
entity registerfile is
port(
Write1:in std_logic_vector(7 downto 0); --what should be put into the write register
Write2: in std_logic_vector(7 downto 0);
SelRead1:in std_logic_vector(3 downto 0); --select which register to read
SelRead2: in std_logic_vector(3 downto 0); --select second register to read
SelWrite1:in std_logic_vector(3 downto 0); --select which register to write
SelWrite2:in std_logic_vector(3 downto 0);
UseWrite1:in std_logic; --if the register should actually be written to
UseWrite2: in std_logic;
Clock:in std_logic;
Read1:out std_logic_vector(7 downto 0); --register to be read output
Read2:out std_logic_vector(7 downto 0) --register to be read on second output
WriteEnable: in regwritetype;
DataIn: in regdatatype;
Clock: in std_logic;
DataOut: out regdatatype
);
end registerfile;
 
architecture Behavioral of registerfile is
type registerstype is array(0 to 15) of std_logic_vector(7 downto 0);
signal registers: registerstype;
--attribute ram_style : string;
--attribute ram_style of registers: signal is "distributed";
begin
writereg: process(Write1, Write2, SelWrite1, SelWrite2, UseWrite1, UseWrite2, Clock)
begin
if(UseWrite1='1') then
if(rising_edge(clock)) then
registers(conv_integer(SelWrite1)) <= Write1;
end if;
end if;
if(UseWrite2='1') then
if(rising_edge(clock) and conv_integer(SelWrite1)/=conv_integer(SelWrite2)) then
registers(conv_integer(SelWrite2)) <= Write2;
end if;
end if;
end process;
Read1 <= registers(conv_integer(SelRead1));
Read2 <= registers(conv_integer(SelRead2));
regs:
for I in 0 to 15 generate
process(WriteEnable(I), DataIn(I), Clock)
begin
if rising_edge(Clock) then
if(WriteEnable(I) = '1') then
registers(I) <= DataIn(I);
end if;
end if;
end process;
DataOut(I) <= registers(I);
end generate regs;
end Behavioral;
/Makefile
34,10 → 34,10
@mv $(TESTBENCH) simulation/$(TESTBENCH)
run :
@$(SIMDIR)/$(TESTBENCH) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(TESTBENCH).vcdgz
@$(SIMDIR)/$(TESTBENCH) $(GHDL_SIM_OPT) --wave=$(SIMDIR)/$(TESTBENCH).ghw
view :
gunzip --stdout $(SIMDIR)/$(TESTBENCH).vcdgz | $(WAVEFORM_VIEWER) --vcd
$(WAVEFORM_VIEWER) --dump=$(SIMDIR)/$(TESTBENCH).ghw
clean :
$(GHDL_CMD) --clean --workdir=simulation

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