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URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

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  • This comparison shows the changes necessary to convert path 
    /tinycpu/trunk
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/testbench/blockram_tb.vhd
11,8 → 11,8
component blockram
port(
Address: in std_logic_vector(7 downto 0); --memory address
WriteEnable: in std_logic; --write or read
Address: in std_logic_vector(11 downto 0); --memory address
WriteEnable: in std_logic_vector(1 downto 0); --write or read
Enable: in std_logic;
Clock: in std_logic;
DataIn: in std_logic_vector(15 downto 0);
22,8 → 22,8
 
--Inputs
signal Address: std_logic_vector(7 downto 0) := (others => '0');
signal WriteEnable: std_logic := '0';
signal Address: std_logic_vector(11 downto 0) := (others => '0');
signal WriteEnable: std_logic_vector(1 downto 0) := (others => '0');
signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
signal Enable: std_logic := '0';
 
66,27 → 66,32
wait for clock_period*10;
--case 1
WriteEnable <= '0';
WriteEnable(0) <= '0';
WriteEnable(1) <= '0';
wait for 10 ns;
Address <= x"01";
Address <= x"001";
DataIn <= "1000000000001000";
WriteEnable <= '1';
WriteEnable(0) <= '1';
WriteEnable(1) <= '1';
wait for 10 ns;
WriteEnable <= '0';
WriteEnable(0) <= '0';
WriteEnable(1) <= '0';
wait for 10 ns;
assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
 
--case 2
Address <= x"33";
Address <= x"033";
DataIn <= "1000000000001100";
WriteEnable <= '1';
WriteEnable(0) <= '1';
WriteEnable(1) <= '1';
wait for 10 ns;
WriteEnable <= '0';
WriteEnable(0) <= '0';
WriteEnable(1) <= '0';
wait for 10 ns;
assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
 
-- case 3
Address <= x"01";
Address <= x"001";
wait for 10 ns;
assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
/src/blockram.vhd
15,8 → 15,8
 
entity blockram is
port(
Address: in std_logic_vector(7 downto 0); --memory address
WriteEnable: in std_logic; --write or read
Address: in std_logic_vector(11 downto 0); --memory address
WriteEnable: in std_logic_vector(1 downto 0); --write 1 byte at a time option
Enable: in std_logic;
Clock: in std_logic;
DataIn: in std_logic_vector(15 downto 0);
25,18 → 25,31
end blockram;
 
architecture Behavioral of blockram is
type ram_type is array (255 downto 0) of std_logic_vector (15 downto 0);
type ram_type is array (4095 downto 0) of std_logic_vector (15 downto 0);
signal RAM: ram_type;
signal di0, di1, do0, do1: std_logic_vector(7 downto 0); --data inputs and outputs for byte-enable
begin
 
process (WriteEnable,DataIn)
begin
if WriteEnable(0) = '1' then
di0 <= DataIn(7 downto 0);
else
di0 <= RAM(conv_integer(Address))(7 downto 0);
do0 <= RAM(conv_integer(Address))(7 downto 0);
end if;
if WriteEnable(1)= '1' then
di1 <= DataIn(15 downto 8);
else
di1 <= RAM(conv_integer(Address))(15 downto 8);
do1 <= RAM(conv_integer(Address))(15 downto 8);
end if;
end process;
process (Clock)
begin
if rising_edge(Clock) then
if Enable = '1' then
if WriteEnable = '1' then
RAM(conv_integer(Address)) <= DataIn;
end if;
DataOut <= RAM(conv_integer(Address)) ;
DataOut <= do1 & do0;
RAM(conv_integer(Address)) <= di1 & di0;
end if;
end if;
end process;

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