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Subversion Repositories tinycpu

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Rev 1 → Rev 2

/trunk/testbench/registerfile_tb.vhd
0,0 → 1,121
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY registerfile_tb IS
END registerfile_tb;
ARCHITECTURE behavior OF registerfile_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component registerfile
port(
Write:in std_logic_vector(7 downto 0); --what should be put into the write register
SelRead:in std_logic_vector(2 downto 0); --select which register to read
SelWrite:in std_logic_vector(2 downto 0); --select which register to write
UseWrite:in std_logic; --if the register should actually be written to
Clock:in std_logic;
Read:out std_logic_vector(7 downto 0) --register to be read output
);
end component;
 
--Inputs
signal Write : std_logic_vector(7 downto 0) := (others => '0');
signal SelRead: std_logic_vector(2 downto 0) := (others => '0');
signal SelWrite: std_logic_vector(2 downto 0) := (others => '0');
signal UseWrite: std_logic := '0';
 
--Outputs
signal Read : std_logic_vector(7 downto 0);
 
signal Clock: std_logic;
constant clock_period : time := 10 ns;
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: registerfile PORT MAP (
Write => Write,
SelRead => SelRead,
SelWrite => SelWrite,
UseWrite => UseWrite,
Clock => Clock,
Read => Read
);
 
-- Clock process definitions
clock_process :process
begin
Clock <= '0';
wait for clock_period/2;
Clock <= '1';
wait for clock_period/2;
end process;
 
-- Stimulus process
stim_proc: process
variable err_cnt: integer :=0;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
 
wait for clock_period*10;
 
-- case 1
SelWrite <= "000";
Write <= "11110000";
UseWrite <= '1';
wait for 10 ns;
SelRead <= "000";
UseWrite <= '0';
wait for 10 ns;
assert (Read="11110000") report "Storage error case 1" severity error;
if (Read/="11110000") then
err_cnt:=err_cnt+1;
end if;
 
-- case 2
SelWrite <= "100";
Write <= "11110001";
UseWrite <= '1';
wait for 10 ns;
SelRead <= "100";
UseWrite <= '0';
wait for 10 ns;
assert (Read="11110001") report "Storage selector error case 2" severity error;
if (Read/="11110001") then
err_cnt:=err_cnt+1;
end if;
 
-- case 3
SelRead <= "000";
UseWrite <= '0';
wait for 10 ns;
assert (Read="11110000") report "Storage selector(remembering) error case 3" severity error;
if (Read/="11110000") then
err_cnt:=err_cnt+1;
end if;
 
-- summary of testbench
if (err_cnt=0) then
assert false
report "Testbench of registerfile completed successfully!"
severity note;
else
assert true
report "Something wrong, try again"
severity error;
end if;
wait;
 
-- insert stimulus here
 
wait;
end process;
 
 
END;
/trunk/src/registerfile.vhd
0,0 → 1,30
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
 
entity registerfile is
port(
Write:in std_logic_vector(7 downto 0); --what should be put into the write register
SelRead:in std_logic_vector(2 downto 0); --select which register to read
SelWrite:in std_logic_vector(2 downto 0); --select which register to write
UseWrite:in std_logic; --if the register should actually be written to
Clock:in std_logic;
Read:out std_logic_vector(7 downto 0) --register to be read output
);
end registerfile;
 
architecture Behavioral of registerfile is
type registerstype is array(0 to 7) of std_logic_vector(7 downto 0);
signal registers: registerstype;
begin
writereg: process(Write, SelWrite, UseWrite, Clock)
begin
if(UseWrite='1') then
if(rising_edge(clock)) then
registers(conv_integer(SelWrite)) <= Write;
end if;
end if;
end process;
Read <= registers(conv_integer(SelRead));
end Behavioral;
/trunk/Makefile
0,0 → 1,43
# vhdl files
FILES = src/*
VHDLEX = .vhd
# testbench
TESTBENCHPATH = testbench/${TESTBENCH}$(VHDLEX)
#GHDL CONFIG
GHDL_CMD = ghdl
GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic
SIMDIR = simulation
# Simulation break condition
#GHDL_SIM_OPT = --assert-level=error
GHDL_SIM_OPT = --stop-time=500ns
WAVEFORM_VIEWER = gtkwave
all: compile run view
new :
echo "Setting up project ${PROJECT}"
mkdir src testbench simulation
compile :
ifeq ($(strip $(TESTBENCH)),)
@echo "TESTBENCH not set. Use TESTBENCH=value to set it."
@exit 2
endif
mkdir -p simulation
$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simulation --work=work $(TESTBENCHPATH) $(FILES)
$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simulation --work=work $(TESTBENCH)
@mv $(TESTBENCH) simulation/$(TESTBENCH)
run :
@$(SIMDIR)/$(TESTBENCH) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(TESTBENCH).vcdgz
view :
gunzip --stdout $(SIMDIR)/$(TESTBENCH).vcdgz | $(WAVEFORM_VIEWER) --vcd
clean :
$(GHDL_CMD) --clean --workdir=simulation

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