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Subversion Repositories tinycpu

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  • This comparison shows the changes necessary to convert path 
    /tinycpu
    from Rev 9 to Rev 10
    ↔ Reverse comparison
  •

Rev 9 → Rev 10

/trunk/testbench/blockram_tb.vhd
11,7 → 11,7
component blockram
port(
Address: in std_logic_vector(11 downto 0); --memory address
Address: in std_logic_vector(7 downto 0); --memory address
WriteEnable: in std_logic_vector(1 downto 0); --write or read
Enable: in std_logic;
Clock: in std_logic;
22,7 → 22,7
 
--Inputs
signal Address: std_logic_vector(11 downto 0) := (others => '0');
signal Address: std_logic_vector(7 downto 0) := (others => '0');
signal WriteEnable: std_logic_vector(1 downto 0) := (others => '0');
signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
signal Enable: std_logic := '0';
69,7 → 69,7
WriteEnable(0) <= '0';
WriteEnable(1) <= '0';
wait for 10 ns;
Address <= x"001";
Address <= x"01";
DataIn <= "1000000000001000";
WriteEnable(0) <= '1';
WriteEnable(1) <= '1';
80,7 → 80,7
assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
 
--case 2
Address <= x"033";
Address <= x"33";
DataIn <= "1000000000001100";
WriteEnable(0) <= '1';
WriteEnable(1) <= '1';
91,7 → 91,7
assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
 
-- case 3
Address <= x"001";
Address <= x"01";
wait for 10 ns;
assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
/trunk/src/blockram.vhd
11,11 → 11,22
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
 
--if WriteEnable(0) = '1' then
-- di0 <= DataIn(7 downto 0);
-- else
--di0 := RAM(conv_integer(Address))(7 downto 0);
-- di0 <= do(7 downto 0);
--end if;
--if WriteEnable(1) = '1' then
-- di1 <= DataIn(15 downto 8);
--else
--di1 <= RAM(conv_integer(Address))(15 downto 8);
-- di1 <= do(15 downto 8);
--end if;
 
 
entity blockram is
port(
Address: in std_logic_vector(11 downto 0); --memory address
Address: in std_logic_vector(7 downto 0); --memory address
WriteEnable: in std_logic_vector(1 downto 0); --write 1 byte at a time option
Enable: in std_logic;
Clock: in std_logic;
25,33 → 36,24
end blockram;
 
architecture Behavioral of blockram is
type ram_type is array (4095 downto 0) of std_logic_vector (15 downto 0);
type ram_type is array (255 downto 0) of std_logic_vector (15 downto 0);
signal RAM: ram_type;
signal di0, di1, do0, do1: std_logic_vector(7 downto 0); --data inputs and outputs for byte-enable
signal di0, di1: std_logic_vector(7 downto 0);
signal do : std_logic_vector(15 downto 0);
begin
process (WriteEnable,DataIn)
begin
if WriteEnable(0) = '1' then
di0 <= DataIn(7 downto 0);
else
di0 <= RAM(conv_integer(Address))(7 downto 0);
do0 <= RAM(conv_integer(Address))(7 downto 0);
end if;
if WriteEnable(1)= '1' then
di1 <= DataIn(15 downto 8);
else
di1 <= RAM(conv_integer(Address))(15 downto 8);
do1 <= RAM(conv_integer(Address))(15 downto 8);
end if;
end process;
di0 <= DataIn(7 downto 0) when WriteEnable(0)='1' else do(7 downto 0);
di1 <= DataIn(15 downto 8) when WriteEnable(1)='1' else do(15 downto 8);
process (Clock)
begin
if rising_edge(Clock) then
if Enable = '1' then
DataOut <= do1 & do0;
if WriteEnable(0)='1' or WriteEnable(1)='1' then
RAM(conv_integer(Address)) <= di1 & di0;
else
do <= RAM(conv_integer(Address)) ;
end if;
end if;
end if;
end process;
 
DataOut <= do;
end Behavioral;

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