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  • This comparison shows the changes necessary to convert path 
    /tinycpu
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/trunk/testbench/top_tb.vhd
98,7 → 98,7
--start the processor
Reset <= '0';
wait for 30 ns; --wait 3 clock cycles for CPU to execute first instruction
wait for 20 ns; --wait 2 clock cycle for first instruction decode and register write to complete
wait for 10 ns; --wait 1 clock cycle for first instruction decode
assert(Debugr0 = x"57") report "R0 is not loaded properly for first instruction" severity error;
wait for 10 ns;
assert(DebugR0 = x"F1") report "R0 is not loaded properly for second instruction" severity error;
/trunk/testbench/core_tb.vhd
119,13 → 119,13
assert(DebugIR = x"00F1" and DebugR0 /= x"12") report "IR is not correct. Execution occurs during first fetch";
MemIn <= x"0056";
wait for 10 ns;
assert(DebugR0 = x"F1") report "loaded value of R0 is not correct" severity error;
assert(DebugR0 = x"56") report "loaded value of R0 is not correct" severity error;
MemIn <= x"0E50"; --mov IP, 0x50
wait for 10 ns;
assert( MemAddr = x"0150") report "mov to IP doesn't work" severity error; --DebugIP uses regOut, so it won't be updated until next clock cycle actually, but it's correct.
MemIn <= x"0020"; --mov r0, 0x20
wait for 10 ns;
assert (MemAddr = x"0152" and DebugIP=x"50") report "fetching is wrong after move to IP" severity error; --DebugIP uses regOut, Fetchaddress uses regIn, so this is correct
assert (MemAddr = x"0152" and DebugIP=x"52") report "fetching is wrong after move to IP" severity error; --DebugIP uses regOut, Fetchaddress uses regIn, so this is correct
MemIn <= x"0160"; --mov r0,0x60 if TR is set
wait for 10 ns; --wait until register write happens
assert(DebugR0 = x"20") report "mov to r0 is wrong after move to IP" severity error;
/trunk/src/registerfile.vhd
27,12 → 27,13
regs: for I in 0 to 15 generate
process(WriteEnable(I), DataIn(I), Clock)
begin
if falling_edge(Clock) then --I really hope this one falling_edge component doesn't bite me in the ass later
if rising_edge(Clock) then --I really hope this one falling_edge component doesn't bite me in the ass later
if(WriteEnable(I) = '1') then
registers(I) <= DataIn(I);
end if;
end if;
end process;
DataOut(I) <= registers(I);
DataOut(I) <= registers(I) when WriteEnable(I)='0' else DataIn(I);
-- DataOut(I) <= registers(I);
end generate regs;
end Behavioral;
/trunk/src/core.vhd
153,8 → 153,8
);
carryovercs: carryover port map(
EnableCarry => CarryCS,
DataIn => regIn(REGIP),
SegmentIn => regIn(REGCS),
DataIn => regOut(REGIP),
SegmentIn => regOut(REGCS),
Addend => IPAddend,
DataOut => IPCarryOut,
SegmentOut => CSCarryOut,
162,8 → 162,8
);
carryoverss: carryover port map(
EnableCarry => CarrySS,
DataIn => regIn(REGSP),
SegmentIn => RegIn(REGSS),
DataIn => regOut(REGSP),
SegmentIn => RegOut(REGSS),
Addend => SPAddend,
DataOut => SPCarryOut,
SegmentOut => SSCarryOut,
186,9 → 186,9
);
fetcheraddress <= regIn(REGCS) & regIn(REGIP);
MemAddr <= OpAddress when state=WaitForMemory else FetchMemAddr;
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else x"0000";
MemWE <= OpWE when state=WaitForMemory else '0';
MemWW <= OpWW when state=WaitForMemory else '0';
MemOut <= OpData when (state=WaitForMemory and OpWE='1') else "ZZZZZZZZZZZZZZZZ" when state=HoldMemory else x"0000";
MemWE <= OpWE when state=WaitForMemory else 'Z' when state=HoldMemory else '0';
MemWW <= OpWW when state=WaitForMemory else 'Z' when state=HoldMEmory else '0';
OpData <= MemIn when (state=WaitForMemory and OpWE='0') else "ZZZZZZZZZZZZZZZZ";
--opcode shortcuts
opmain <= IR(15 downto 12);
245,10 → 245,6
state <= HoldMemory;
HoldAck <= '1';
FetchEN <= '0';
MemAddr <= "ZZZZZZZZZZZZZZZZ";
MemOut <= "ZZZZZZZZZZZZZZZZ";
MemWE <= 'Z';
MemWW <= 'Z';
elsif Hold='0' and state=HoldMemory then
if reset='1' or InReset='1' then
state <= ResetProcessor;

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