OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /tinycpu
    from Rev 28 to Rev 29
    ↔ Reverse comparison
  •

Rev 28 → Rev 29

/trunk/testbench/core_tb.vhd
141,10 → 141,21
wait for 10 ns;
assert(DebugTR ='0') report "ALU compare is not correct for greater than" severity error;
MemIn <= "0011000000010010"; --TR=r0 < r1
wait for 10 ns;
assert(DebugTR='1') report "ALU compare is not correct for less than" severity error;
 
--now test bitwise
MemIn <= x"00F0"; --mov r0, 0xFO
wait for 10 ns;
MemIn <= x"0218"; --mov r1, 0x18
wait for 10 ns;
MemIn <= "0100000000010001"; --or r0, r1 (r0 = r0 or r1)
wait for 10 ns;
assert(DebugR0 = x"F8") report "ALU OR is not correct" severity error;
MemIn <= x"1070"; --mov [r0], 0x70 -- for debugging
wait for 20 ns;
assert(DebugTR='1') report "ALU compare is not correct for less than" severity error;
--wait for 10 ns; --have to wait an extra cycle for memory
 
 
-- summary of testbench
assert false
report "Testbench of core completed successfully!"
/trunk/src/core.vhd
143,7 → 143,8
signal bankreg3: std_logic_vector(3 downto 0);
signal FetchMemAddr: std_logic_vector(15 downto 0);
 
signal UsuallySS: std_logic_vector(3 downto 0);
signal UsuallyDS: std_logic_vector(3 downto 0);
begin
reg: registerfile port map(
WriteEnable => regWE,
209,10 → 210,12
bankreg1 <= ('1' & opreg1) when (regbank='1' and opreg1(2)='0') else '0' & opreg1;
bankreg2 <= ('1' & opreg2) when (regbank='1' and opreg2(2)='0') else '0' & opreg2;
bankreg3 <= ('1' & opreg3) when (regbank='1' and opreg3(2)='0') else '0' & opreg3;
--UsuallySegment shortcuts (only used when not an immediate
UsuallyDS <= "1101" when opseges='0' else "1110";
UsuallySS <= "1111" when opseges='0' else "1110";
decode: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
foo: process(Clock, Hold, state, IR, inreset, reset, regin, regout, IPCarryOut, CSCarryOut)
begin
if rising_edge(Clock) then
 
273,6 → 276,7
state <= Execute;
FetchEn <= '1';
IpAddend <= x"02";
SpAddend <= x"00";
end if;
 
 
308,15 → 312,46
FetchEN <= '0';
when "0011" => --group 3 comparisons
AluOp <= "01" & opreg3; --nothing hard here, ALU does it all for us
AluIn1 <= regOut(to_integer(unsigned(opreg1)));
AluIn2 <= regOut(to_integer(unsigned(opreg2)));
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
when "0100" => --group 4 bitwise operations
AluOp <= "00" & opreg3; --nothing hard here, ALU does it all for us
AluIn1 <= regOut(to_integer(unsigned(opreg1)));
AluIn2 <= regOut(to_integer(unsigned(opreg2)));
regIn(to_integer(unsigned(opreg1))) <= AluOut;
regWE(to_integer(unsigned(opreg1))) <= '1';
AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
AluIn2 <= regOut(to_integer(unsigned(bankreg2)));
regIn(to_integer(unsigned(bankreg1))) <= AluOut;
regWE(to_integer(unsigned(bankreg1))) <= '1';
when "0101" => --group 5
case opreg3 is
when "000" => --subgroup 5-0
case opreg2 is
when "000" => --push reg
SpAddend <= x"02"; --set SP to increment
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
OpWE <= '1';
OpData <= x"00" & regOut(to_integer(unsigned(bankreg1)));
OpWW <= '1';
state <= WaitForMemory;
IPAddend <= x"00";
FetchEN <= '0';
when "001" => --pop reg
SPAddend <= x"FE"; --set SP to decrement
OpAddress <= regOut(to_integer(unsigned(UsuallySS))) & regOut(REGSP);
OpWE <= '0';
regIn(to_integer(unsigned(bankreg1))) <= OpData(7 downto 0);
OpWW <= '0';
state <= WaitForMemory;
IPAddend <= x"00";
FetchEN <= '0';
when others =>
--synthesis off
report "Not implemented subgroup 5-0" severity error;
--synthesis on
end case;
when others =>
--synthesis off
report "Not implemented group 5" severity error;
--synthesis on
end case;
when others =>
--synthesis off
report "Not implemented" severity error;
325,10 → 360,10
end if;
end if;
 
end if;
 
 
 
end if;
end process;
 
 
/trunk/docs/design.md.txt
286,6 → 286,7
Implemented opcode list:
legend:
r = register choice
R = register choice or opcode choice for sub groups
C = conditional portion
s = segment register choice
i = immediate data
322,6 → 323,13
110: rotate right reg,reg
111: rotate left reg,reg
 
group 5 misc
0101 rrrC CRRR sooo
opcode choices:
000: subgroup 5-0
RRR choices:
000: push reg
001: pop reg
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.