URL
https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
Subversion Repositories tinycpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/tinycpu
- from Rev 33 to Rev 34
- ↔ Reverse comparison
Rev 33 → Rev 34
/trunk/testbench/core_tb.vhd
177,9 → 177,25
assert(MemAddr=x"0200") report "Pop is not fetching from correct address" severity error; |
wait for 10 ns; |
assert(DebugR0=x"20") report "Pop is not assigning to R0 correct" severity error; |
MemIn <= x"0040"; |
MemIn <= x"0040"; --mov r0, 0x40 |
wait for 10 ns; |
MemIn <= b"0101_0010_0000_0001"; --mov r1,r0 |
wait for 10 ns; |
MemIn <= b"0101_0000_0001_0010"; --mov r0, [r1] |
wait for 10 ns; |
assert(MemAddr=x"0040") report "load operation doesn't fetch from proper address" severity error; |
MemIn <= x"1234"; --value to be loaded to r0 (lower value only) |
wait for 10 ns; |
assert(DebugR0=x"34") report "load operation doesn't load into r0 properly" severity error; |
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MemIn <= b"0101_0000_0001_0011"; --mov [r0], r1 |
wait for 10 ns; |
assert(MemAddr=x"0034") report "store operation doesn't store to proper address" severity error; |
assert(MemOut=x"0040") report "store operation doesn't have proper value" severity error; |
wait for 10 ns; |
MemIn <= x"0010"; |
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-- summary of testbench |
assert false |
report "Testbench of core completed successfully!" |
/trunk/src/core.vhd
393,6 → 393,21
when "001" => --mov reg, reg |
regIn(to_integer(unsigned(bankreg1))) <= regOut(to_integer(unsigned(bankreg2))); |
regWE(to_integer(unsigned(bankreg1))) <= '1'; |
when "010" => --mov reg, [reg] (load) |
OpDestReg1 <= bankreg1; |
OpWE <= '0'; |
OpAddress <= regOut(to_integer(unsigned(UsuallyDS))) & regOut(to_integer(unsigned(bankreg2))); |
IpAddend <= x"00"; |
FetchEN <= '0'; |
state <= WaitForMemory; |
when "011" => --mov [reg], reg (store) |
OpDataOut <= x"00" & regOut(to_integer(unsigned(bankreg2))); |
OpWW <= '0'; |
OpWE <= '1'; |
OpAddress <= regOut(to_integer(unsigned(UsuallyDS))) & regOut(to_integer(unsigned(bankreg1))); |
IpAddend <= x"00"; |
FetchEN <= '0'; |
state <= WaitForMemory; |
when others => |
--synthesis off |
report "Not implemented group 5" severity error; |
/trunk/docs/design.md.txt
289,9 → 289,12
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Register order: |
The order of registers is read from left to right with left being the most significant bit of the 16-bit opcode. |
So for instance, |
0101_*000*0_0*111*_0010 is `mov [r0], IP/r7`. The register portions of the opcode are surrounded by astericks |
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Implemented opcode list: |
legend: |
r = register choice |
301,15 → 304,16
i = immediate data |
N = not used |
o = opcode choice (for groups) |
_ = space for readability |
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0000 rrrC iiii iiii |
0000_rrrC_iiii_iiii |
mov reg, immediate |
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0001 rrrC iiii iiii |
0001_rrrC_iiii_iiii |
mov [reg], immediate |
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group 3 comparions |
0011 rrrC Crrr Nooo |
0011_rrrC_Crrr_Nooo |
opcode choices |
000: is greater than reg1,reg2 (TR=reg1>reg2) |
001: is greater or equal to reg,reg |
321,7 → 325,7
111: not equals 0 reg |
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group 4 bitwise |
0100 rrrC Crrr Nooo |
0100_rrrC_Crrr_Nooo |
opcode choices |
000: and reg1,reg2 (reg1=reg1 and reg2) |
001: or reg, reg |
333,14 → 337,13
111: rotate left reg,reg |
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group 5 misc |
0101 rrrC CRRR sooo |
0101_rrrC_CRRR_sooo |
opcode choices: |
000: subgroup 5-0 |
RRR choices: |
000: push reg |
001: pop reg |
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001: mov reg, reg |
010: mov reg, [reg] |
011: mov [reg], reg |
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