URL
https://opencores.org/ocsvn/tinycpu/tinycpu/trunk
Subversion Repositories tinycpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/tinycpu
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/trunk/testbench/top_tb.vhd
19,6 → 19,7
Address: in std_logic_vector(15 downto 0); --memory address (in bytes) |
WriteEnable: in std_logic; |
Data: inout std_logic_vector(15 downto 0); |
Port0: inout std_logic_vector(7 downto 0); |
--debug ports |
DebugR0: out std_logic_vector(7 downto 0) |
); |
32,6 → 33,7
signal Address: std_logic_vector(15 downto 0):=x"0000"; --memory address (in bytes) |
signal WriteEnable: std_logic:='0'; |
signal Data: std_logic_vector(15 downto 0):=x"0000"; |
signal Port0: std_logic_vector(7 downto 0); |
--debug ports |
signal DebugR0: std_logic_vector(7 downto 0); |
|
50,7 → 52,8
Address => Address, |
WriteEnable => WriteEnable, |
Data => Data, |
DebugR0 => DebugR0 |
DebugR0 => DebugR0, |
Port0 => Port0 |
); |
|
-- Clock process definitions |
/trunk/testbench/memory_tb.vhd
16,7 → 16,8
WriteEnable: in std_logic; |
Clock: in std_logic; |
DataIn: in std_logic_vector(15 downto 0); |
DataOut: out std_logic_vector(15 downto 0) |
DataOut: out std_logic_vector(15 downto 0); |
Port0: inout std_logic_vector(7 downto 0) |
); |
end component; |
|
30,6 → 31,9
--Outputs |
signal DataOut: std_logic_vector(15 downto 0); |
|
--inouts |
signal Port0: std_logic_vector(7 downto 0); |
|
signal Clock: std_logic; |
constant clock_period : time := 10 ns; |
|
42,7 → 46,8
WriteEnable => WriteEnable, |
Clock => Clock, |
DataIn => DataIn, |
DataOut => DataOut |
DataOut => DataOut, |
Port0 => Port0 |
); |
|
-- Clock process definitions |
62,7 → 67,7
wait for 50 ns; |
|
|
Address <= x"0000"; |
Address <= x"0100"; |
WriteWord <= '1'; |
WriteEnable <='1'; |
DataIn <= x"1234"; |
72,7 → 77,7
wait for 10 ns; |
assert (DataOut = x"1234") report "Basic storage failure" severity error; |
|
Address <= x"0022"; |
Address <= x"0122"; |
WriteWord <= '1'; |
WriteEnable <= '1'; |
DataIn <= x"5215"; |
80,14 → 85,14
assert (DataOut = x"1234") report "no-change block ram failure" severity error; |
WriteWord <= '0'; |
WriteEnable <= '0'; |
Address <= x"0000"; |
Address <= x"0100"; |
wait for 10 ns; |
assert( DataOut = x"1234") report "Memory retention failure" severity error; |
Address <= x"0022"; |
Address <= x"0122"; |
wait for 10 ns; |
assert( DataOut = x"5215") report "memory timing is too slow" severity error; |
|
Address <= x"0010"; |
Address <= x"0110"; |
WriteWord <= '1'; |
WriteEnable <= '1'; |
DataIn <= x"1234"; |
94,7 → 99,7
wait for 10 ns; |
WriteWord <= '0'; |
WriteEnable <= '0'; |
Address <= x"0011"; |
Address <= x"0111"; |
wait for 10 ns; |
assert (DataOut = x"0012") report "unaligned 8-bit memory read is wrong" severity error; |
WriteWord <='0'; |
104,7 → 109,7
WriteEnable <= '0'; |
wait for 10 ns; |
assert (DataOut = x"0056") report "unaligned 8 bit memory write and then read is wrong" severity error; |
Address <= x"0010"; |
Address <= x"0110"; |
wait for 10 ns; |
assert (DataOut = x"5634") report "aligned memory read after unaligned write is wrong" severity error; |
WriteEnable <= '1'; |
114,6 → 119,21
wait for 10 ns; |
assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error; |
|
Address <= x"0001"; |
WriteWord <= '0'; |
WriteEnable <= '1'; |
DataIn <= b"00000000_0011_1000"; |
wait for 10 ns; |
Address <= x"0000"; |
Port0 <= "10ZZZ101"; |
DataIn <= x"00" & b"00_101_011"; |
wait for 10 ns; |
WriteEnable <= '0'; |
wait for 10 ns; |
assert(Port0 = "10101101") report "Memory mapped port does not work correctly" severity error; |
assert(DataOut = x"00" & "10101101") report "Memory read of mapped port does not work correctly" severity error; |
|
|
assert false |
report "Testbench of memory completed successfully!" |
severity note; |
/trunk/src/top.vhd
19,6 → 19,7
Address: in std_logic_vector(15 downto 0); --memory address (in bytes) |
WriteEnable: in std_logic; |
Data: inout std_logic_vector(15 downto 0); |
Port0: inout std_logic_vector(7 downto 0); |
--debug ports |
DebugR0: out std_logic_vector(7 downto 0) |
); |
33,7 → 34,8
WriteEnable: in std_logic; |
Clock: in std_logic; |
DataIn: in std_logic_vector(15 downto 0); |
DataOut: out std_logic_vector(15 downto 0) |
DataOut: out std_logic_vector(15 downto 0); |
Port0: inout std_logic_vector(7 downto 0) |
); |
end component; |
|
99,7 → 101,8
WriteEnable => MemWriteEnable, |
Clock => Clock, |
DataIn => MemDataIn, |
DataOut => MemDataOut |
DataOut => MemDataOut, |
Port0 => Port0 |
); |
|
MemAddress <= cpuaddr when DMA='0' else Address; |
/trunk/src/memory.vhd
16,7 → 16,9
WriteEnable: in std_logic; |
Clock: in std_logic; |
DataIn: in std_logic_vector(15 downto 0); |
DataOut: out std_logic_vector(15 downto 0) |
DataOut: out std_logic_vector(15 downto 0); |
|
Port0: inout std_logic_vector(7 downto 0) |
-- Reset: in std_logic |
|
--RAM/ROM interface (RAMA is built in to here |
40,8 → 42,8
); |
end component; |
|
constant R1START: integer := 0; |
constant R1END: integer := 1023; |
constant R1START: integer := 15; |
constant R1END: integer := 1023+15; |
signal addr: std_logic_vector(15 downto 0) := (others => '0'); |
signal R1addr: std_logic_vector(7 downto 0); |
signal we: std_logic_vector(1 downto 0); |
52,6 → 54,9
signal R1en: std_logic; |
signal R1in: std_logic_vector(15 downto 0); |
signal R1out: std_logic_vector(15 downto 0); |
|
signal port0we: std_logic_vector(7 downto 0); |
signal port0temp: std_logic_vector(7 downto 0); |
begin |
R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out); |
addrwe: process(Address, WriteWord, WriteEnable, DataIn) |
76,12 → 81,56
end if; |
end process; |
|
assignram: process (we, datawrite, addr, r1out) |
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address) |
variable tmp: integer; |
variable tmp2: integer; |
variable found: boolean := false; |
begin |
tmp := to_integer(unsigned(addr)); |
if tmp >= R1START and tmp <= R1END then |
tmp2 := to_integer(unsigned(Address)); |
if tmp2 <= 15 then --internal registers/mapped IO |
if WriteWord='0' then |
if tmp2=0 then |
dataread <= x"0000"; |
gen: for I in 0 to 7 loop |
if WriteEnable='1' then |
if port0we(I)='1' then --1-bit port set to WRITE mode |
port0(I) <= DataIn(I); |
port0temp(I) <= DataIn(I); |
else |
port0(I) <= 'Z'; |
end if; |
else --not WE |
if port0we(I)='0' then --1-bit-port set to READ mode |
dataread(I) <= port0(I); |
else |
dataread(I) <= port0temp(I); |
end if; |
end if; |
end loop gen; |
elsif tmp2=1 then |
dataread <= x"00" & port0we; |
if WriteEnable='1' then |
port0we <= DataIn(7 downto 0); |
setwe: for I in 0 to 7 loop |
if DataIn(I)='0' then |
port0(I) <= 'Z'; |
end if; |
end loop setwe; |
else |
dataread <= x"00" & port0we; |
end if; |
else |
--synthesis off |
report "Memory address is outside of bounds of RAM and registers" severity warning; |
--synthesis on |
end if; |
else |
--synthesis off |
report "WriteWord is not allowed in register area. Ignoring access" severity warning; |
--synthesis on |
end if; |
elsif tmp >= R1START and tmp <= R1END then --RAM bank1 |
--map all to R1 |
found := true; |
R1en <= '1'; |
106,5 → 155,4
DataOut <= x"00" & dataread(15 downto 8); |
end if; |
end process; |
|
end Behavioral; |
/trunk/assembler/asm.rb
17,6 → 17,7
end |
end |
end |
|
|
|
class Register8 |
27,6 → 28,7
end |
|
$iftr = 0; #0 for no condition, 1 for if TR, 2 for if not TR |
$useextra = 0; |
|
def mov_r8_imm8(reg,imm) |
o = OpcodeByte1.new(); |
40,9 → 42,33
puts PREFIX + o.to_hex + imm.to_s(16) + SUFFIX; |
puts SEPERATOR; |
end |
def mov_rm8_imm8(reg,imm) |
o=OpcodeByte1.new(); |
o.op=1; |
o.register=reg; |
if $iftr<2 then |
o.cond=$iftr; |
else |
raise "if_tr_notset is not allowed with this opcode"; |
end |
puts PREFIX + o.to_hex + imm.to_s(16) + SUFFIX; |
puts SEPERATOR; |
end |
|
|
def mov(arg1,arg2) |
if arg1.kind_of? Register8 and arg2.kind_of? Integer and arg2<0x100 then mov_r8_imm8 arg1,arg2 end |
if arg1.kind_of? Register8 and arg2.kind_of? Integer and arg2<0x100 then |
mov_r8_imm8 arg1,arg2 |
elsif arg1.kind_of? Array and arg2.kind_of? Integer and arg2<0x100 then |
if arg1.length>1 or arg1.length<1 then |
raise "memory reference is not correct. Only a register is allowed"; |
end |
reg=arg1[0]; |
mov_rm8_imm8 reg, arg2 |
else |
raise "No suitable mov opcode found"; |
end |
|
end |
def if_tr_set |
$iftr = 1 |
60,4 → 86,5
if_tr_set{ |
mov r1,0x10 |
} |
mov r1,0x20 |
mov r1,0x20 |
mov [r1], 0x50 |