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URL https://opencores.org/ocsvn/ttl_library/ttl_library/trunk

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Rev 2 → Rev 3

/trunk/Testbench/Testbench_00.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS00N: Quad 2-input NAND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_00 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_00 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not(J(0) and J(1));
D(1) <= not(J(2) and J(3));
D(2) <= not(J(4) and J(5));
D(3) <= not(J(6) and J(7));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS00N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_01.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7401N: Quad 2-input NAND gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_01 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_01 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not (J(0) and J(1)) );
D(1) <= TTL_OC( not (J(2) and J(3)) );
D(2) <= TTL_OC( not (J(4) and J(5)) );
D(3) <= TTL_OC( not (J(6) and J(7)) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7401N
port map(
X_1 => E(0), -- 1Y\
X_2 => J(0), -- 1A
X_3 => J(1), -- 1B
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => J(6), -- 4B
X_12 => J(7), -- 4A
X_13 => E(3), -- 4Y\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_02.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS02N: Quad 2-input NOR gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_02 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_02 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not (J(0) or J(1));
D(1) <= not (J(2) or J(3));
D(2) <= not (J(4) or J(5));
D(3) <= not (J(6) or J(7));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS02N
port map(
X_1 => E(0), -- 1Y\
X_2 => J(0), -- 1A
X_3 => J(1), -- 1B
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => J(6), -- 4B
X_12 => J(7), -- 4A
X_13 => E(3), -- 4Y\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_03.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS03N: Quad 2-input NAND gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_03 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_03 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not(J(0) and J(1)) );
D(1) <= TTL_OC( not(J(2) and J(3)) );
D(2) <= TTL_OC( not(J(4) and J(5)) );
D(3) <= TTL_OC( not(J(6) and J(7)) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS03N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_04.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS04N: Hex inverter (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_04 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_04 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not J(0);
D(1) <= not J(1);
D(2) <= not J(2);
D(3) <= not J(3);
D(4) <= not J(4);
D(5) <= not J(5);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS04N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_05.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS05N: Hex inverter (open collector) (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_05 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_05 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not J(0) );
D(1) <= TTL_OC( not J(1) );
D(2) <= TTL_OC( not J(2) );
D(3) <= TTL_OC( not J(3) );
D(4) <= TTL_OC( not J(4) );
D(5) <= TTL_OC( not J(5) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS05N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_06.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS05N: Hex inverter (open collector) (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_06 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_06 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not J(0) );
D(1) <= TTL_OC( not J(1) );
D(2) <= TTL_OC( not J(2) );
D(3) <= TTL_OC( not J(3) );
D(4) <= TTL_OC( not J(4) );
D(5) <= TTL_OC( not J(5) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7406N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_07.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7407N: Hex buffer (high voltage open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_07 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_07 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( J(0) );
D(1) <= TTL_OC( J(1) );
D(2) <= TTL_OC( J(2) );
D(3) <= TTL_OC( J(3) );
D(4) <= TTL_OC( J(4) );
D(5) <= TTL_OC( J(5) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7407N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_08.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS08N: Quad 2-input AND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_08 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_08 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= (J(0) and J(1));
D(1) <= (J(2) and J(3));
D(2) <= (J(4) and J(5));
D(3) <= (J(6) and J(7));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS08N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_09.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS09N: Quad 2-input AND gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_09 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_09 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( J(0) and J(1) );
D(1) <= TTL_OC( J(2) and J(3) );
D(2) <= TTL_OC( J(4) and J(5) );
D(3) <= TTL_OC( J(6) and J(7) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS09N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_10.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS10N: Triple 3-input NAND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_10 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_10 is
signal J, B : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not(J(0) and J(1) and J(2));
D(1) <= not(J(3) and J(4) and J(5));
D(2) <= not(J(6) and J(7) and J(8));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS10N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(3), -- 2A
X_4 => J(4), -- 2B
X_5 => J(5), -- 2C
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(6), -- 3C
X_10 => J(7), -- 3B
X_11 => J(8), -- 3A
X_12 => E(0), -- 1Y\
X_13 => J(2), -- 1C
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_100.vhd
0,0 → 1,125
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74100N: Dual 4-bit latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_100 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_100 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
subtype quad is std_logic_vector(4 downto 1);
type biquad is array(2 downto 1) of quad;
signal R, Q, Z : biquad;
signal G : std_logic_vector(2 downto 1);
begin
E <= (Q(2), Q(1));
D <= (Z(2), Z(1));
R <= (quad(BC(7 downto 4)), quad(BC(3 downto 0)));
process(CLK) is
variable A, B : natural := 0;
begin
if rising_edge(CLK) then
G <= (others => '0'); -- Default
A := A + 1;
B := B + 1;
if (A = 5) then
A := 0;
G(2) <= '1';
end if;
if (B = 7) then
B := 0;
G(1) <= '1';
end if;
elsif falling_edge(CLK) then
G <= (others => '0');
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
begin
for i in G'range loop
if G(i) = '1' then
Z(i) <= R(i);
end if;
end loop;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74100N
port map(
--
X_2 => R(1)(1), -- 1D1
X_3 => R(1)(2), -- 1D2
X_4 => Q(1)(2), -- 1Q2
X_5 => Q(1)(1), -- 1Q1
--
X_7 => open, -- GND
X_8 => Q(2)(1), -- 2Q1
X_9 => Q(2)(2), -- 2Q2
X_10 => R(2)(2), -- 2D2
X_11 => R(2)(1), -- 2D1
X_12 => G(2), -- 2G
--
--
X_15 => R(2)(3), -- 2D3
X_16 => R(2)(4), -- 2D4
X_17 => Q(2)(4), -- 2Q4
X_18 => Q(2)(3), -- 2Q3
X_19 => Q(1)(3), -- 1Q3
X_20 => Q(1)(4), -- 1Q4
X_21 => R(1)(4), -- 1D4
X_22 => R(1)(3), -- 1D3
X_23 => G(1), -- 1G
X_24 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_101.vhd
0,0 → 1,99
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H101N: JK edge-triggered flipflop: AND-OR input --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_101 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_101 is
signal PS, J, K : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => PS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
SIM: process(CLK, PS) is
variable JK : std_logic_vector(1 downto 0);
begin
if PS = '0' then -- Here, set
D(0) <= '1';
elsif falling_edge(CLK) then
JK := J & K;
case JK is
when "00" => null;
when "01" => D(0) <= '0';
when "10" => D(0) <= '1';
when "11" => D(0) <= not D(0);
when others => null;
end case;
end if;
end process;
D(1) <= not D(0);
J <= (BC(0) and BC(1)) or (BC(2) and BC(3));
K <= (BC(4) and BC(5)) or (BC(6) and BC(7));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H101N
port map(
X_1 => BC(0), -- J1A
X_2 => BC(1), -- J1B
X_3 => BC(2), -- J2A
X_4 => BC(3), -- J2B
X_5 => PS, -- SD\
X_6 => E(0), -- Q
X_7 => open, -- GND
X_8 => E(1), -- Q\
X_9 => BC(4), -- K1A
X_10 => BC(5), -- K1B
X_11 => BC(6), -- K2A
X_12 => BC(7), -- K2B
X_13 => CLK, -- CP
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_102.vhd
0,0 → 1,99
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H102N: JK edge-triggered flipflop (AND inputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_102 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_102 is
signal RS, J, K : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(0) <= '0';
elsif falling_edge(CLK) then
JK := J & K;
case JK is
when "00" => null;
when "01" => D(0) <= '0';
when "10" => D(0) <= '1';
when "11" => D(0) <= not D(0);
when others => null;
end case;
end if;
end process;
D(1) <= not D(0);
J <= JC(0) and JC(1) and JC(2);
K <= JC(3) and JC(4) and JC(5);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H102N
port map(
--
X_2 => RS, -- CD\
X_3 => JC(0), -- J1
X_4 => JC(1), -- J2
X_5 => JC(2), -- J3
X_6 => E(1), -- Q\
X_7 => open, -- GND
X_8 => E(0), -- Q
X_9 => JC(3), -- K1
X_10 => JC(4), -- K2
X_11 => JC(5), -- K3
X_12 => CLK, -- CP\
X_13 => '1', -- SD\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_103.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H103N: Dual JK edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_103 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_103 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H103N
port map(
X_1 => CLK, -- CP1\
X_2 => RS, -- CD1\
X_3 => BC(2), -- K1
X_4 => open, -- Vcc
X_5 => CLK, -- CP2\
X_6 => RS, -- CD2\
X_7 => BC(1), -- J2
X_8 => E(3), -- Q2\
X_9 => E(1), -- Q2
X_10 => BC(3), -- K2
X_11 => open, -- GND
X_12 => E(0), -- Q1
X_13 => E(2), -- Q1\
X_14 => BC(0) -- J1
);
end architecture Test;
/trunk/Testbench/Testbench_106.vhd
0,0 → 1,101
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H106N: Dual JK edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_106 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_106 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H106N
port map(
X_1 => CLK, -- CP1\
X_2 => '1', -- SD1\
X_3 => RS, -- CD1\
X_4 => BC(0), -- J1
X_5 => open, -- Vcc
X_6 => CLK, -- CP2\
X_7 => '1', -- SD2\
X_8 => RS, -- CD2\
X_9 => BC(1), -- J2
X_10 => E(3), -- Q2\
X_11 => E(1), -- Q2
X_12 => BC(3), -- K2
X_13 => open, -- GND
X_14 => E(2), -- Q1\
X_15 => E(0), -- Q1
X_16 => BC(2) -- K1
);
end architecture Test;
/trunk/Testbench/Testbench_107.vhd
0,0 → 1,99
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS107N: Dual JK flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_107 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_107 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS107N
port map(
X_1 => BC(0), -- J1
X_2 => E(2), -- Q1\
X_3 => E(0), -- Q1
X_4 => BC(2), -- K1
X_5 => E(1), -- Q2
X_6 => E(3), -- Q2\
X_7 => open, -- GND
X_8 => BC(1), -- J2
X_9 => CLK, -- CP2\
X_10 => RS, -- CD2\
X_11 => BC(3), -- K2
X_12 => CLK, -- CP1\
X_13 => RS, -- CD2\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_108.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H108N: Dual JK edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_108 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_108 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H108N
port map(
X_1 => BC(2), -- K1
X_2 => E(0), -- Q1
X_3 => E(2), -- Q1\
X_4 => BC(0), -- J1
X_5 => E(3), -- Q2\
X_6 => E(1), -- Q2
X_7 => open, -- GND
X_8 => BC(3), -- K2
X_9 => CLK, -- CP\
X_10 => '1', -- SD2\
X_11 => BC(1), -- J2
X_12 => RS, -- CD\
X_13 => '1', -- SD1\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_109.vhd
0,0 → 1,101
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS109N: Dual JK +ve edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_109 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_109 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif rising_edge(CLK) then
JK := BC(i) & not BC(2+i); -- K is active low
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS109N
port map(
X_1 => RS, -- CD1\
X_2 => BC(0), -- J1
X_3 => BC(2), -- K1\
X_4 => CLK, -- CP1
X_5 => '1', -- SD1\
X_6 => E(0), -- Q1
X_7 => E(2), -- Q1\
X_8 => open, -- GND
X_9 => E(3), -- Q2\
X_10 => E(1), -- Q2
X_11 => '1', -- SD2\
X_12 => CLK, -- CP2
X_13 => BC(3), -- K2\
X_14 => BC(1), -- J2
X_15 => RS, -- CD2\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_11.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS11N: Triple 3-input AND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_11 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_11 is
signal J, B : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= (J(0) and J(1) and J(2));
D(1) <= (J(3) and J(4) and J(5));
D(2) <= (J(6) and J(7) and J(8));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS11N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(3), -- 2A
X_4 => J(4), -- 2B
X_5 => J(5), -- 2C
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(6), -- 3C
X_10 => J(7), -- 3B
X_11 => J(8), -- 3A
X_12 => E(0), -- 1Y\
X_13 => J(2), -- 1C
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_112.vhd
0,0 → 1,100
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS112N: Dual JK -ve edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_112 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_112 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS112N
port map(
X_1 => CLK, -- CP1\
X_2 => BC(2), -- K1
X_3 => BC(0), -- J1
X_4 => '1', -- SD1\
X_5 => E(0), -- Q1
X_6 => E(2), -- Q1\
X_7 => E(3), -- Q2\
X_8 => open, -- GND
X_9 => E(1), -- Q2
X_10 => '1', -- SD2\
X_11 => BC(1), -- J2
X_12 => BC(3), -- K2
X_13 => CLK, -- CP2\
X_14 => RS, -- CD2\
X_15 => RS, -- CD1\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_113.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS113N: Dual JK edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_113 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_113 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '1'; -- Async. preset
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS113N
port map(
X_1 => CLK, -- CP1\
X_2 => BC(2), -- K1
X_3 => BC(0), -- J1
X_4 => RS, -- SD1\
X_5 => E(0), -- Q1
X_6 => E(2), -- Q1\
X_7 => open, -- GND
X_8 => E(3), -- Q2\
X_9 => E(1), -- Q2
X_10 => RS, -- SD2\
X_11 => BC(1), -- J2
X_12 => BC(3), -- K2
X_13 => CLK, -- CP2\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_114.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS114N: Dual JK -ve edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_114 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_114 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS114N
port map(
X_1 => RS, -- CD\
X_2 => BC(2), -- K1
X_3 => BC(0), -- J1
X_4 => '1', -- SD1\
X_5 => E(0), -- Q1
X_6 => E(2), -- Q1\
X_7 => open, -- GND
X_8 => E(3), -- Q2\
X_9 => E(1), -- Q2
X_10 => '1', -- SD2\
X_11 => BC(1), -- J2
X_12 => BC(3), -- K2
X_13 => CLK, -- CP\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_12.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS12N: Triple 3-input NAND gate (open collector)--
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_12 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_12 is
signal J, B : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC(not((J(0) and J(1) and J(2))));
D(1) <= TTL_OC(not((J(3) and J(4) and J(5))));
D(2) <= TTL_OC(not((J(6) and J(7) and J(8))));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS12N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(3), -- 2A
X_4 => J(4), -- 2B
X_5 => J(5), -- 2C
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(6), -- 3C
X_10 => J(7), -- 3B
X_11 => J(8), -- 3A
X_12 => E(0), -- 1Y\
X_13 => J(2), -- 1C
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_121.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74121N: Monostable multivibrator --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_121 is -- Top-level bench
end entity;
 
architecture Test of Testbench_121 is
signal S, Q : std_logic; -- Trigger & output
signal W, N : std_logic; -- Wide & narrow windows
begin
S <= '0',
'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
'1' after 16000 ns, '0' after 16100 ns; -- Should NOT retrigger
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
W <= '0',
'1' after 320 ns, '0' after 10330 ns,
'1' after 15060 ns, '0' after 25080 ns;
N <= '0',
'1' after 350 ns, '0' after 10280 ns,
'1' after 15090 ns, '0' after 25030 ns;
 
-----------------------------------------------------------------------
-- Validate the results
-----------------------------------------------------------------------
process(W, N, Q) is
begin
if (rising_edge(W) and Q = '1') or -- W must rise before Q
(rising_edge(N) and Q = '0') or -- Q must rise before N
(falling_edge(N) and Q = '0') or -- N must fall before Q
(falling_edge(W) and Q = '1') then -- Q must fall before W
assert false
report "Bad monostable pulse"
severity failure;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74121N
generic map(
W => 10 us -- Pulse width
)
port map(
X_1 => open, -- Q\
--
X_3 => '0', -- A1\
X_4 => '0', -- A2\
X_5 => S, -- B
X_6 => Q, -- Q
X_7 => open, -- GND
--
X_9 => open, -- Rint (open for simulation)
X_10 => open, -- Cx
X_11 => open, -- RxCx
--
--
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_122.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74122N: Retriggerable resettable monostable --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_122 is -- Top-level bench
end entity;
 
architecture Test of Testbench_122 is
signal S, Q : std_logic; -- Trigger & output
signal W, N : std_logic; -- Wide & narrow windows
begin
S <= '0',
'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
W <= '0',
'1' after 220 ns, '0' after 10330 ns,
'1' after 15020 ns, '0' after 26080 ns;
N <= '0',
'1' after 350 ns, '0' after 10250 ns,
'1' after 15090 ns, '0' after 26000 ns;
 
-----------------------------------------------------------------------
-- Validate the results
-----------------------------------------------------------------------
process(W, N, Q) is
begin
if (rising_edge(W) and Q = '1') or -- W must rise before Q
(rising_edge(N) and Q = '0') or -- Q must rise before N
(falling_edge(N) and Q = '0') or -- N must fall before Q
(falling_edge(W) and Q = '1') then -- Q must fall before W
assert false
report "Bad monostable pulse"
severity failure;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74122N
generic map(
W => 10 us -- Pulse width
)
port map(
X_1 => '0', -- A1\
X_2 => '0', -- A2\
X_3 => S, -- B1
X_4 => '1', -- B2
X_5 => '1', -- CD\
X_6 => open, -- Q\
X_7 => open, -- GND
X_8 => Q, -- Q
X_9 => open, -- Rint
--
X_11 => open, -- Cx
--
X_13 => open, -- RxCx
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_123.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74123N: Dual retriggerable resettable monostable --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_123 is -- Top-level bench
end entity;
 
architecture Test of Testbench_123 is
signal S, Q : std_logic_vector(1 downto 0); -- Triggers & outputs
signal W, N : std_logic_vector(1 downto 0); -- Wide & narrow windows
begin
S(0) <= '0',
'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
S(1) <= '0',
'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
W(0) <= '0',
'1' after 220 ns, '0' after 9330 ns,
'1' after 15020 ns, '0' after 25080 ns;
N(0) <= '0',
'1' after 350 ns, '0' after 9250 ns,
'1' after 15090 ns, '0' after 25000 ns;
 
W(1) <= '0',
'1' after 220 ns, '0' after 10330 ns,
'1' after 15020 ns, '0' after 26080 ns;
N(1) <= '0',
'1' after 350 ns, '0' after 10250 ns,
'1' after 15090 ns, '0' after 26000 ns;
 
-----------------------------------------------------------------------
-- Validate the results
-----------------------------------------------------------------------
G: for i in Q'range generate
begin
process(W(i), N(i), Q(i)) is
begin
if (rising_edge(W(i)) and Q(i) = '1') or -- W must rise before Q
(rising_edge(N(i)) and Q(i) = '0') or -- Q must rise before N
(falling_edge(N(i)) and Q(i) = '0') or -- N must fall before Q
(falling_edge(W(i)) and Q(i) = '1') then -- Q must fall before W
assert false
report "Bad monostable pulse"
severity warning;
end if;
end process;
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74123N
generic map(
W1 => 10 us, -- Pulse widths
W2 => 9 us
)
port map(
X_1 => '0', -- A1\
X_2 => S(0), -- B1
X_3 => '1', -- CD1\
X_4 => open, -- Q1\
X_5 => Q(1), -- Q2
X_6 => open, -- Cx2
X_7 => open, -- Rx2Cx2
X_8 => open, -- GND
X_9 => '0', -- A2\
X_10 => S(1), -- B2
X_11 => '1', -- CD2\
X_12 => open, -- Q2\
X_13 => Q(0), -- Q1
X_14 => open, -- Cx1
X_15 => open, -- Rx1Cx1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_125.vhd
0,0 → 1,88
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS125N: Quad bus buffer (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_125 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_125 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
subtype quad is std_logic_vector(3 downto 0);
signal I, G : quad;
begin
I <= quad(BC(7 downto 4));
G <= quad(BC(3 downto 0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
GG: for j in G'range generate
begin
D(j) <= I(j) when G(j) = '0' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS125N
port map(
X_1 => G(0), -- E1\
X_2 => I(0), -- D1
X_3 => E(0), -- Q1
X_4 => G(1), -- E2\
X_5 => I(1), -- D2
X_6 => E(1), -- Q2
X_7 => open, -- GND
X_8 => E(2), -- Q3
X_9 => I(2), -- D3
X_10 => G(2), -- E3\
X_11 => E(3), -- Q4
X_12 => I(3), -- D4
X_13 => G(3), -- E4\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_126.vhd
0,0 → 1,88
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS126N: Quad bus buffer (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_126 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_126 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
subtype quad is std_logic_vector(3 downto 0);
signal I, G : quad;
begin
I <= quad(BC(7 downto 4));
G <= quad(BC(3 downto 0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
GG: for j in G'range generate
begin
D(j) <= I(j) when G(j) = '1' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS126N
port map(
X_1 => G(0), -- E1\
X_2 => I(0), -- D1
X_3 => E(0), -- Q1
X_4 => G(1), -- E2\
X_5 => I(1), -- D2
X_6 => E(1), -- Q2
X_7 => open, -- GND
X_8 => E(2), -- Q3
X_9 => I(2), -- D3
X_10 => G(2), -- E3\
X_11 => E(3), -- Q4
X_12 => I(3), -- D4
X_13 => G(3), -- E4\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_13.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS13N: Dual 4-input NAND Schmitt trigger --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_13 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_13 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( J(0) and J(1) and J(2) and J(3) );
D(1) <= not( J(4) and J(5) and J(6) and J(7) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS13N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
--
X_4 => J(2), -- 1C
X_5 => J(3), -- 1D
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2D
X_10 => J(5), -- 2C
--
X_12 => J(6), -- 2B
X_13 => J(7), -- 2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_132.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS132N: Quad 2-input Schmitt trigger NAND gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_132 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_132 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not(J(0) and J(1));
D(1) <= not(J(2) and J(3));
D(2) <= not(J(4) and J(5));
D(3) <= not(J(6) and J(7));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS132N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_133.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS133N: 13-input NAND gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_133 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_133 is
signal J, B : unsigned(12 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= nand_reduce(std_logic_vector(J));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS133N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(2), -- 1C
X_4 => J(3), -- 1D
X_5 => J(4), -- 1E
X_6 => J(5), -- 1F
X_7 => J(6), -- 1G
X_8 => open, -- GND
X_9 => E(0), -- 1Y\
X_10 => J(7), -- 1H
X_11 => J(8), -- 1J
X_12 => J(9), -- 1K
X_13 => J(10), -- 1L
X_14 => J(11), -- 1M
X_15 => J(12), -- 1N
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_134.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74S134N: 12-input NAND gate (3-state output) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_134 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_134 is
signal J, B : unsigned(12 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= nand_reduce(std_logic_vector(J(12 downto 1))) when J(0) = '0'
else 'Z';
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74S134N
port map(
X_1 => J(1), -- 1A
X_2 => J(2), -- 1B
X_3 => J(3), -- 1C
X_4 => J(4), -- 1D
X_5 => J(5), -- 1E
X_6 => J(6), -- 1F
X_7 => J(7), -- 1G
X_8 => open, -- GND
X_9 => E(0), -- 1Y\
X_10 => J(8), -- 1H
X_11 => J(9), -- 1J
X_12 => J(10), -- 1K
X_13 => J(11), -- 1L
X_14 => J(12), -- 1M
X_15 => J(0), -- EB
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_135.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74S135N: Quad XOR/NOR gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_135 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_135 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= J(0) xor J(1) xor J(8);
D(1) <= J(2) xor J(3) xor J(8);
D(2) <= J(4) xor J(5) xor J(9);
D(3) <= J(6) xor J(7) xor J(9);
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74S135N
port map(
X_1 => J(0), -- A1
X_2 => J(1), -- B1
X_3 => E(0), -- Y1
X_4 => J(8), -- C12
X_5 => J(2), -- A2
X_6 => J(3), -- B2
X_7 => E(1), -- Y2
X_8 => open, -- GND
X_9 => E(2), -- Y3
X_10 => J(4), -- B3
X_11 => J(5), -- A3
X_12 => J(9), -- C34
X_13 => E(3), -- Y4
X_14 => J(6), -- B4
X_15 => J(7), -- A4
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_136.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS136N: Quad 2-input XOR gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_136 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_136 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( J(0) xor J(1) );
D(1) <= TTL_OC( J(2) xor J(3) );
D(2) <= TTL_OC( J(4) xor J(5) );
D(3) <= TTL_OC( J(6) xor J(7) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS136N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_137.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS137N: 1-of-8 decoder/demux. (input latches) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_137 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_137 is
signal J, B, Z : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
 
alias A is Z(2 downto 0);
alias LE is Z(3);
alias E1 is Z(4);
alias E2 is Z(5);
begin
Z <= not B;
 
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(Z) is
variable chn : natural range 7 downto 0;
begin
E <= (others => '1');
if LE = '0' then
chn := TTL_to_integer(A);
end if;
if (E2 and not E1) = '1' then
E(chn) <= '0';
end if;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS137N
port map(
X_1 => A(0), -- A0
X_2 => A(1), -- A1
X_3 => A(2), -- A2
X_4 => LE, -- LE\
X_5 => E1, -- E1\
X_6 => E2, -- E2
X_7 => D(7), -- O7\
X_8 => open, -- GND
X_9 => D(6), -- O6\
X_10 => D(5), -- O5\
X_11 => D(4), -- O4\
X_12 => D(3), -- O3\
X_13 => D(2), -- O2\
X_14 => D(1), -- O1\
X_15 => D(0), -- O0\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_138.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS138N: 1-of-8 decoder/demultiplexer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_138 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_138 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal EN : std_logic;
 
alias A is J(2 downto 0);
alias E1 is B(3);
alias E2 is B(4);
alias E3 is B(5);
begin
EN <= (not E1) and (not E2) and E3;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(A, EN) is
variable chn : natural range 7 downto 0;
begin
E <= (others => '1');
if EN = '1' then
chn := TTL_to_integer(A);
E(chn) <= '0';
end if;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS138N
port map(
X_1 => A(0), -- A0
X_2 => A(1), -- A1
X_3 => A(2), -- A2
X_4 => E1, -- E1\
X_5 => E2, -- E2\
X_6 => E3, -- E3
X_7 => D(7), -- O7\
X_8 => open, -- GND
X_9 => D(6), -- O6\
X_10 => D(5), -- O5\
X_11 => D(4), -- O4\
X_12 => D(3), -- O3\
X_13 => D(2), -- O2\
X_14 => D(1), -- O1\
X_15 => D(0), -- O0\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_139.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS139N: Dual 1-of-4 decoder --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_139 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_139 is
signal J, B, Z : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal RS : std_logic;
begin
Z <= (not B) when RS = '1' else (others => '1'); -- Should start with enables high
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(Z) is
variable N : natural range 3 downto 0;
begin
D <= (others => '1');
if Z(0) = '0' then -- EA
N := TTL_to_integer(Z(5 downto 4));
D(N) <= '0';
end if;
if Z(1) = '0' then -- EB
N := TTL_to_integer(Z(3 downto 2));
D(4+N) <= '0';
end if;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS139N
port map(
X_1 => Z(0), -- EA\
X_2 => Z(4), -- A0A
X_3 => Z(5), -- A1A
X_4 => E(0), -- O0A\
X_5 => E(1), -- O1A\
X_6 => E(2), -- O2A\
X_7 => E(3), -- O3A\
X_8 => open, -- GND
X_9 => E(7), -- O3B\
X_10 => E(6), -- O2B\
X_11 => E(5), -- O1B\
X_12 => E(4), -- O0B\
X_13 => Z(3), -- A1B
X_14 => Z(2), -- A0B
X_15 => Z(1), -- EB\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_14.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS14N: Hex Schmitt trigger inverter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_14 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_14 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not J(0);
D(1) <= not J(1);
D(2) <= not J(2);
D(3) <= not J(3);
D(4) <= not J(4);
D(5) <= not J(5);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS14N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_140.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74S140N: Dual 4-input NAND line driver --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_140 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_140 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( J(0) and J(1) and J(2) and J(3) );
D(1) <= not( J(4) and J(5) and J(6) and J(7) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74S140N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
--
X_4 => J(2), -- 1C
X_5 => J(3), -- 1D
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2D
X_10 => J(5), -- 2C
--
X_12 => J(6), -- 2B
X_13 => J(7), -- 2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_145.vhd
0,0 → 1,87
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74145N: 1-of-10 decoder/driver (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_145 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_145 is
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(9 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(J) is
variable N : natural;
begin
D <= (others => 'Z'); -- Default
N := TTL_to_integer(J(3 downto 0));
if N < 10 then
D(N) <= '0';
end if;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74145N
port map(
X_1 => E(0), -- Q0\
X_2 => E(1), -- Q1\
X_3 => E(2), -- Q2\
X_4 => E(3), -- Q3\
X_5 => E(4), -- Q4\
X_6 => E(5), -- Q5\
X_7 => E(6), -- Q6\
X_8 => open, -- GND
X_9 => E(7), -- Q7\
X_10 => E(8), -- Q8\
X_11 => E(9), -- Q9\
X_12 => J(3), -- A3
X_13 => J(2), -- A2
X_14 => J(1), -- A1
X_15 => J(0), -- A0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_15.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS15N: Triple 3-input AND gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_15 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_15 is
signal J, B : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( J(0) and J(1) and J(2) );
D(1) <= TTL_OC( J(3) and J(4) and J(5) );
D(2) <= TTL_OC( J(6) and J(7) and J(8) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS15N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(3), -- 2A
X_4 => J(4), -- 2B
X_5 => J(5), -- 2C
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(6), -- 3C
X_10 => J(7), -- 3B
X_11 => J(8), -- 3A
X_12 => E(0), -- 1Y\
X_13 => J(2), -- 1C
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_150.vhd
0,0 → 1,91
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74150N: 16-input multiplexer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_150 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 100 ms;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_150 is
signal J, B : unsigned(20 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
signal A : unsigned(3 downto 0);
signal chn : natural range 15 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(4 downto 1);
chn <= TTL_to_integer(A);
D(0) <= B(0) or B(5+chn);
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74150N
port map(
X_1 => B(12), -- I7
X_2 => B(11), -- I6
X_3 => B(10), -- I5
X_4 => B(9), -- I4
X_5 => B(8), -- I3
X_6 => B(7), -- I2
X_7 => B(6), -- I1
X_8 => B(5), -- I0
X_9 => B(0), -- E\
X_10 => E(0), -- Z\
X_11 => B(4), -- S3
X_12 => open, -- GND
X_13 => B(3), -- S2
X_14 => B(2), -- S1
X_15 => B(1), -- S0
X_16 => B(20), -- I15
X_17 => B(19), -- I14
X_18 => B(18), -- I13
X_19 => B(17), -- I12
X_20 => B(16), -- I11
X_21 => B(15), -- I10
X_22 => B(14), -- I9
X_23 => B(13), -- I8
X_24 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_151.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS151N: 8-input multiplexer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_151 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_151 is
signal J, B : unsigned(11 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal A : unsigned(2 downto 0);
signal chn : natural range 7 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(3 downto 1);
chn <= TTL_to_integer(A);
D(1) <= B(0) or not B(4+chn);
D(0) <= not D(1);
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS151N
port map(
X_1 => B(7), -- I3
X_2 => B(6), -- I2
X_3 => B(5), -- I1
X_4 => B(4), -- I0
X_5 => E(0), -- Z
X_6 => E(1), -- Z\
X_7 => B(0), -- E\
X_8 => open, -- GND
X_9 => B(3), -- S2
X_10 => B(2), -- S1
X_11 => B(1), -- S0
X_12 => B(11), -- I7
X_13 => B(10), -- I6
X_14 => B(9), -- I5
X_15 => B(8), -- I4
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_153.vhd
0,0 → 1,85
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS153N: Dual 4-input mux. (common selects) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_153 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_153 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal A : unsigned(1 downto 0);
signal chn : natural range 3 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(3 downto 2);
chn <= TTL_to_integer(A);
D(0) <= (not B(0)) and B(7-chn);
D(1) <= (not B(1)) and B(chn+4);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS153N
port map(
X_1 => B(0), -- EA\
X_2 => B(3), -- S1
X_3 => B(4), -- I3A
X_4 => B(5), -- I2A
X_5 => B(6), -- I1A
X_6 => B(7), -- I0A
X_7 => E(0), -- ZA
X_8 => open, -- GND
X_9 => E(1), -- ZB
X_10 => B(4), -- I0B
X_11 => B(5), -- I1B
X_12 => B(6), -- I2B
X_13 => B(7), -- I3B
X_14 => B(2), -- S0
X_15 => B(1), -- EB\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_154.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74154N: 1-of-16 decoder/demultiplexer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_154 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_154 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(15 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
variable chn : natural range 15 downto 0;
variable EN : std_logic;
begin
chn := TTL_to_integer(B(5 downto 2));
EN := B(1) or B(0);
E <= (others => '1');
E(chn) <= EN;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74154N
port map(
X_1 => D(0), -- O0\
X_2 => D(1), -- O1\
X_3 => D(2), -- O2\
X_4 => D(3), -- O3\
X_5 => D(4), -- O4\
X_6 => D(5), -- O5\
X_7 => D(6), -- O6\
X_8 => D(7), -- O7\
X_9 => D(8), -- O8\
X_10 => D(9), -- O9\
X_11 => D(10), -- O10\
X_12 => open, -- GND
X_13 => D(11), -- O11\
X_14 => D(12), -- O12\
X_15 => D(13), -- O13\
X_16 => D(14), -- O14\
X_17 => D(15), -- O15\
X_18 => B(0), -- E0\
X_19 => B(1), -- E1\
X_20 => B(5), -- A3
X_21 => B(4), -- A2
X_22 => B(3), -- A1
X_23 => B(2), -- A0
X_24 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_155.vhd
0,0 → 1,91
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS155N: Dual 1-of-4 decoder/demultiplexer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_155 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_155 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
begin
 
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
variable N : natural range 3 downto 0;
variable EA, EB : std_logic;
begin
N := TTL_to_integer(B(5 downto 4));
EA := B(0) and not B(1);
EB := not(B(2) or B(3));
D <= (others => '1');
D(N+4) <= not EB;
D(N) <= not EA;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS155N
port map(
X_1 => B(0), -- EA
X_2 => B(1), -- EA\
X_3 => B(5), -- A1
X_4 => E(3), -- O3A\
X_5 => E(2), -- O2A\
X_6 => E(1), -- O1A\
X_7 => E(0), -- O0A\
X_8 => open, -- GND
X_9 => E(4), -- O0B\
X_10 => E(5), -- O1B\
X_11 => E(6), -- O2B\
X_12 => E(7), -- O3B\
X_13 => B(4), -- A0
X_14 => B(3), -- EB2\
X_15 => B(2), -- EB1\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_156.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS156N: Dual 1-of-4 decoder/demux (o/c) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_156 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_156 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
variable N : natural range 3 downto 0;
variable EA, EB : std_logic;
variable X : std_logic_vector(7 downto 0);
begin
N := TTL_to_integer(B(5 downto 4));
EA := B(0) and not B(1);
EB := not(B(2) or B(3));
X := (others => '1');
X(N+4) := not EB;
X(N) := not EA;
for i in X'range loop
D(i) <= TTL_OC(X(i));
end loop;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS156N
port map(
X_1 => B(0), -- EA
X_2 => B(1), -- EA\
X_3 => B(5), -- A1
X_4 => E(3), -- O3A\
X_5 => E(2), -- O2A\
X_6 => E(1), -- O1A\
X_7 => E(0), -- O0A\
X_8 => open, -- GND
X_9 => E(4), -- O0B\
X_10 => E(5), -- O1B\
X_11 => E(6), -- O2B\
X_12 => E(7), -- O3B\
X_13 => B(4), -- A0
X_14 => B(3), -- EB2\
X_15 => B(2), -- EB1\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_157.vhd
0,0 → 1,88
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS157N: Quad 2-input mux. (common select) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_157 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_157 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
begin
if B(0) = '1' then
D <= (others => '0');
elsif B(1) = '0' then
D <= (B(8), B(6), B(4), B(2));
else
D <= (B(9), B(7), B(5), B(3));
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS157N
port map(
X_1 => B(1), -- S
X_2 => B(2), -- I0A
X_3 => B(3), -- I1A
X_4 => E(0), -- ZA
X_5 => B(4), -- I0B
X_6 => B(5), -- I1B
X_7 => E(1), -- ZB
X_8 => open, -- GND
X_9 => E(3), -- ZD
X_10 => B(9), -- I1D
X_11 => B(8), -- I0D
X_12 => E(2), -- ZC
X_13 => B(7), -- I1C
X_14 => B(6), -- I0C
X_15 => B(0), -- E\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_158.vhd
0,0 → 1,90
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS158N: Quad 2-input mux (common select: invt) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_158 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_158 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
variable Z : std_logic_vector(3 downto 0);
begin
if B(0) = '1' then
Z := (others => '0');
elsif B(1) = '0' then
Z := (B(8), B(6), B(4), B(2));
else
Z := (B(9), B(7), B(5), B(3));
end if;
D <= not Z;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS158N
port map(
X_1 => B(1), -- S
X_2 => B(2), -- I0A
X_3 => B(3), -- I1A
X_4 => E(0), -- ZA
X_5 => B(4), -- I0B
X_6 => B(5), -- I1B
X_7 => E(1), -- ZB
X_8 => open, -- GND
X_9 => E(3), -- ZD
X_10 => B(9), -- I1D
X_11 => B(8), -- I0D
X_12 => E(2), -- ZC
X_13 => B(7), -- I1C
X_14 => B(6), -- I0C
X_15 => B(0), -- E\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_16.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7416N: Hex inverter/driver (HV open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_16 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_16 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not J(0) );
D(1) <= TTL_OC( not J(1) );
D(2) <= TTL_OC( not J(2) );
D(3) <= TTL_OC( not J(3) );
D(4) <= TTL_OC( not J(4) );
D(5) <= TTL_OC( not J(5) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7416N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_160.vhd
0,0 → 1,148
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS160N: Synchronous presettable BCD decade ctr --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_160 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 30 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_160 is
signal RS, NRS : std_logic;
signal CLK, R : std_logic;
signal J, B : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal PE : std_logic := '1';
signal CEP : std_logic := '1';
signal CET : std_logic := '1';
 
alias P : unsigned(3 downto 0) is B(3 downto 0);
alias CP : std_logic is CLK;
constant modulus : natural := 10;
constant asyncrst : boolean := true;
constant limit : unsigned(3 downto 0) := to_unsigned(modulus-1, 4);
 
begin
RS <= NRS and R;
CEP <= J(0);
CET <= J(1);
process(CLK) is -- Generate control signals
variable T2, T3 : natural := 0;
begin
if rising_edge(CLK) then
if T2 = 37 then
PE <= '0';
T2 := 0;
else
PE <= '1';
T2 := T2 + 1;
end if;
if T3 = 41 then
R <= '0';
T3 := 0;
else
R <= '1';
T3 := T3 + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP, RS) is
variable N : unsigned(3 downto 0);
begin
if asyncrst and (RS = '0') then
N := (others => '0');
elsif rising_edge(CP) then
if RS = '0' then
N := (others => '0');
elsif PE = '0' then
N := unsigned(P);
elsif (CEP and CET) = '1' then
if modulus = 16 then -- Simple binary count
N := N + 1;
else -- Decade count, cover illegal cases
case N is
when "1001" => N := "0000";
when "1011" | "1101" => N := "0100";
when "1111" => N := "1000";
when others => N := N + 1;
end case;
end if;
end if;
end if;
D(3 downto 0) <= std_logic_vector(N); -- Export results
if now > 1 ns and N = limit then
D(4) <= CET;
else
D(4) <= '0';
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS160N
port map(
X_1 => RS, -- R\
X_2 => CP, -- CP
X_3 => B(0), -- P0
X_4 => B(1), -- P1
X_5 => B(2), -- P2
X_6 => B(3), -- P3
X_7 => CEP, -- CEP
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CET, -- CET
X_11 => E(3), -- Q3
X_12 => E(2), -- Q2
X_13 => E(1), -- Q1
X_14 => E(0), -- Q0
X_15 => E(4), -- TC
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_161.vhd
0,0 → 1,148
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS161N: Synch. presettable 4-bit binary ctr --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_161 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 30 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_161 is
signal RS, NRS : std_logic;
signal CLK, R : std_logic;
signal J, B : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal PE : std_logic := '1';
signal CEP : std_logic := '1';
signal CET : std_logic := '1';
 
alias P : unsigned(3 downto 0) is B(3 downto 0);
alias CP : std_logic is CLK;
constant modulus : natural := 16;
constant asyncrst : boolean := true;
constant limit : unsigned(3 downto 0) := to_unsigned(modulus-1, 4);
 
begin
RS <= NRS and R;
CEP <= J(0);
CET <= J(1);
process(CLK) is -- Generate control signals
variable T2, T3 : natural := 0;
begin
if rising_edge(CLK) then
if T2 = 37 then
PE <= '0';
T2 := 0;
else
PE <= '1';
T2 := T2 + 1;
end if;
if T3 = 41 then
R <= '0';
T3 := 0;
else
R <= '1';
T3 := T3 + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP, RS) is
variable N : unsigned(3 downto 0);
begin
if asyncrst and (RS = '0') then
N := (others => '0');
elsif rising_edge(CP) then
if RS = '0' then
N := (others => '0');
elsif PE = '0' then
N := unsigned(P);
elsif (CEP and CET) = '1' then
if modulus = 16 then -- Simple binary count
N := N + 1;
else -- Decade count, cover illegal cases
case N is
when "1001" => N := "0000";
when "1011" | "1101" => N := "0100";
when "1111" => N := "1000";
when others => N := N + 1;
end case;
end if;
end if;
end if;
D(3 downto 0) <= std_logic_vector(N); -- Export results
if now > 1 ns and N = limit then
D(4) <= CET;
else
D(4) <= '0';
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS161N
port map(
X_1 => RS, -- R\
X_2 => CP, -- CP
X_3 => B(0), -- P0
X_4 => B(1), -- P1
X_5 => B(2), -- P2
X_6 => B(3), -- P3
X_7 => CEP, -- CEP
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CET, -- CET
X_11 => E(3), -- Q3
X_12 => E(2), -- Q2
X_13 => E(1), -- Q1
X_14 => E(0), -- Q0
X_15 => E(4), -- TC
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_162.vhd
0,0 → 1,148
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS162N: Synchronous presettable BCD decade ctr --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_162 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 30 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_162 is
signal RS, NRS : std_logic;
signal CLK, R : std_logic;
signal J, B : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal PE : std_logic := '1';
signal CEP : std_logic := '1';
signal CET : std_logic := '1';
 
alias P : unsigned(3 downto 0) is B(3 downto 0);
alias CP : std_logic is CLK;
constant modulus : natural := 10;
constant asyncrst : boolean := false;
constant limit : unsigned(3 downto 0) := to_unsigned(modulus-1, 4);
 
begin
RS <= NRS and R;
CEP <= J(0);
CET <= J(1);
process(CLK) is -- Generate control signals
variable T2, T3 : natural := 0;
begin
if rising_edge(CLK) then
if T2 = 37 then
PE <= '0';
T2 := 0;
else
PE <= '1';
T2 := T2 + 1;
end if;
if T3 = 41 then
R <= '0';
T3 := 0;
else
R <= '1';
T3 := T3 + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP, RS) is
variable N : unsigned(3 downto 0);
begin
if asyncrst and (RS = '0') then
N := (others => '0');
elsif rising_edge(CP) then
if RS = '0' then
N := (others => '0');
elsif PE = '0' then
N := unsigned(P);
elsif (CEP and CET) = '1' then
if modulus = 16 then -- Simple binary count
N := N + 1;
else -- Decade count, cover illegal cases
case N is
when "1001" => N := "0000";
when "1011" | "1101" => N := "0100";
when "1111" => N := "1000";
when others => N := N + 1;
end case;
end if;
end if;
end if;
D(3 downto 0) <= std_logic_vector(N); -- Export results
if now > 1 ns and N = limit then
D(4) <= CET;
else
D(4) <= '0';
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS162N
port map(
X_1 => RS, -- R\
X_2 => CP, -- CP
X_3 => B(0), -- P0
X_4 => B(1), -- P1
X_5 => B(2), -- P2
X_6 => B(3), -- P3
X_7 => CEP, -- CEP
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CET, -- CET
X_11 => E(3), -- Q3
X_12 => E(2), -- Q2
X_13 => E(1), -- Q1
X_14 => E(0), -- Q0
X_15 => E(4), -- TC
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_163.vhd
0,0 → 1,148
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS163N: Synch. presettable 4-bit binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_163 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 30 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_163 is
signal RS, NRS : std_logic;
signal CLK, R : std_logic;
signal J, B : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal PE : std_logic := '1';
signal CEP : std_logic := '1';
signal CET : std_logic := '1';
 
alias P : unsigned(3 downto 0) is B(3 downto 0);
alias CP : std_logic is CLK;
constant modulus : natural := 16;
constant asyncrst : boolean := false;
constant limit : unsigned(3 downto 0) := to_unsigned(modulus-1, 4);
 
begin
RS <= NRS and R;
CEP <= J(0);
CET <= J(1);
process(CLK) is -- Generate control signals
variable T2, T3 : natural := 0;
begin
if rising_edge(CLK) then
if T2 = 37 then
PE <= '0';
T2 := 0;
else
PE <= '1';
T2 := T2 + 1;
end if;
if T3 = 41 then
R <= '0';
T3 := 0;
else
R <= '1';
T3 := T3 + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP, RS) is
variable N : unsigned(3 downto 0);
begin
if asyncrst and (RS = '0') then
N := (others => '0');
elsif rising_edge(CP) then
if RS = '0' then
N := (others => '0');
elsif PE = '0' then
N := unsigned(P);
elsif (CEP and CET) = '1' then
if modulus = 16 then -- Simple binary count
N := N + 1;
else -- Decade count, cover illegal cases
case N is
when "1001" => N := "0000";
when "1011" | "1101" => N := "0100";
when "1111" => N := "1000";
when others => N := N + 1;
end case;
end if;
end if;
end if;
D(3 downto 0) <= std_logic_vector(N); -- Export results
if now > 1 ns and N = limit then
D(4) <= CET;
else
D(4) <= '0';
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS163N
port map(
X_1 => RS, -- R\
X_2 => CP, -- CP
X_3 => B(0), -- P0
X_4 => B(1), -- P1
X_5 => B(2), -- P2
X_6 => B(3), -- P3
X_7 => CEP, -- CEP
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CET, -- CET
X_11 => E(3), -- Q3
X_12 => E(2), -- Q2
X_13 => E(1), -- Q1
X_14 => E(0), -- Q0
X_15 => E(4), -- TC
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_164.vhd
0,0 → 1,94
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS164N: SIPO shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_164 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_164 is
signal RS, RSH : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
alias CP : std_logic is CLK;
alias A : std_logic is JC(1);
alias B : std_logic is JC(2);
alias MR : std_logic is RS;
begin
RS <= RSH;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RSH,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP, MR) is
variable N : std_logic_vector(7 downto 0);
begin
if MR = '0' then
N := (others => '0');
elsif rising_edge(CP) then
N := N(6 downto 0) & (A and B);
end if;
D <= N;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS164N
port map(
X_1 => A, -- A
X_2 => B, -- B
X_3 => E(0), -- Q0
X_4 => E(1), -- Q1
X_5 => E(2), -- Q2
X_6 => E(3), -- Q3
X_7 => open, -- GND
X_8 => CP, -- CP
X_9 => MR, -- MR\
X_10 => E(4), -- Q4
X_11 => E(5), -- Q5
X_12 => E(6), -- Q6
X_13 => E(7), -- Q7
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_165.vhd
0,0 → 1,118
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS165N: 8-bit parallel-to-serial converter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_165 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_165 is
signal CLK, ICLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal PL, RS : std_logic;
signal CP1, CP2 : std_logic;
signal P1 : std_logic_vector(7 downto 0) := (others => '0');
signal SR : std_logic_vector(7 downto 0);
alias DS : std_logic is BC(1);
begin
P1 <= std_logic_vector(BC(9 downto 2));
ICLK <= not((CP1 and PL) or (CP2 and PL));
D(0) <= SR(7);
D(1) <= not SR(7);
process(CLK, RS) is
variable X : unsigned(5 downto 0);
begin
if RS = '0' then
CP1 <= '0';
CP2 <= '0';
PL <= '0';
elsif rising_edge(CLK) then
CP1 <= BC(0);
CP2 <= not BC(0);
X := BC(X'range);
case X is
when "000000" => PL <= '0';
when others => PL <= '1';
end case;
elsif falling_edge(CLK) then
CP1 <= '0';
CP2 <= '0';
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(ICLK, PL) is
begin
if PL = '0' then -- Asynchronous load
SR <= P1;
elsif falling_edge(ICLK) then
SR <= SR(6 downto 0) & DS;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS165N
port map(
X_1 => PL, -- PL\
X_2 => CP1, -- CP1
X_3 => P1(4), -- P4
X_4 => P1(5), -- P5
X_5 => P1(6), -- P6
X_6 => P1(7), -- P7
X_7 => E(1), -- Q7\
X_8 => open, -- GND
X_9 => E(0), -- Q7
X_10 => DS, -- DS
X_11 => P1(0), -- P0
X_12 => P1(1), -- P1
X_13 => P1(2), -- P2
X_14 => P1(3), -- P3
X_15 => CP2, -- CP2
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_166.vhd
0,0 → 1,121
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS166N: 8-bit PISO shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_166 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_166 is
signal CLK, ICLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
signal PL, RS : std_logic;
signal CP1, CP2 : std_logic;
signal P1 : std_logic_vector(7 downto 0) := (others => '0');
signal SR : std_logic_vector(7 downto 0);
alias DS : std_logic is BC(1);
begin
P1 <= std_logic_vector(BC(9 downto 2));
ICLK <= CP1 or CP2;
D(0) <= SR(7);
process(CLK, RS) is
variable X : unsigned(5 downto 0);
begin
if RS = '0' then
CP1 <= '0';
CP2 <= '0';
PL <= '0';
elsif rising_edge(CLK) then
CP1 <= BC(0);
CP2 <= not BC(0);
X := BC(X'range);
case X is
when "000000" => PL <= '0';
when others => PL <= '1';
end case;
elsif falling_edge(CLK) then
CP1 <= '0';
CP2 <= '0';
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(ICLK, RS) is
begin
if RS = '0' then -- Asynchronous reset
SR <= (others => '0');
elsif rising_edge(ICLK) then
if PL = '0' then
SR <= P1;
else
SR <= SR(6 downto 0) & DS;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS166N
port map(
X_1 => DS, -- DS
X_2 => P1(0), -- P0
X_3 => P1(1), -- P1
X_4 => P1(2), -- P2
X_5 => P1(3), -- P3
X_6 => CP2, -- CP2
X_7 => CP1, -- CP1
X_8 => open, -- GND
X_9 => RS, -- MR\
X_10 => P1(4), -- P4
X_11 => P1(5), -- P5
X_12 => P1(6), -- P6
X_13 => E(0), -- Q7
X_14 => P1(7), -- P7
X_15 => PL, -- PE\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_168.vhd
0,0 → 1,163
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS168N: Synchronous bidirectional BCD counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_168 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_168 is
signal RS : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal PE : std_logic := '1';
signal CEP : std_logic := '1';
signal CET : std_logic := '1';
signal UD : std_logic := '1';
signal X, Y, Z : std_logic;
signal W : std_logic_vector(3 downto 0);
 
alias P : unsigned(3 downto 0) is B(3 downto 0);
alias CP : std_logic is CLK;
constant modulus : natural := 10;
constant limit : unsigned(3 downto 0) := to_unsigned(modulus-1, 4);
constant decade : boolean := true;
 
begin
CEP <= J(0);
CET <= J(1);
X <= W(0) and W(3) and not CET;
Y <= nor_reduce(W) and not CET;
Z <= not X when UD = '1' else not Y;
D <= Z & W;
process(CP, RS) is -- Generate control signals
variable T2, T3 : natural := 0;
begin
if RS = '0' then
PE <= '0';
elsif rising_edge(CP) then
if T2 = 37 then
PE <= '0';
T2 := 0;
else
PE <= '1';
T2 := T2 + 1;
end if;
if T3 = 41 then
UD <= not UD;
T3 := 0;
else
T3 := T3 + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP) is
variable SW : std_logic_vector(3 downto 0);
variable R : unsigned(3 downto 0);
begin
if CP'event and CP = '1' then -- Everything is synchronous
SW := (PE, CEP, CET, UD);
case SW is
when "0000" | "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" | "0111"=> -- Load
R := unsigned(P);
when "1001" => -- Count up
if decade then
case R is
when "1001" => R := "0000";
when "1011" => R := "0100";
when "1101" => R := "0100";
when others => R := R + 1;
end case;
else
R := R + 1;
end if;
when "1000" => -- Count down
if decade then
case R is
when "0000" => R := "1001";
when "1010" => R := "0001";
when "1100" => R := "0011";
when "1110" => R := "0101";
when others => R := R - 1;
end case;
else
R := R - 1;
end if;
when others => -- No change
null;
end case;
end if;
W <= std_logic_vector(R);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS168N
port map(
X_1 => UD, -- U_D\
X_2 => CP, -- CP
X_3 => B(0), -- P0
X_4 => B(1), -- P1
X_5 => B(2), -- P2
X_6 => B(3), -- P3
X_7 => CEP, -- CEP\
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CET, -- CET\
X_11 => E(3), -- Q3
X_12 => E(2), -- Q2
X_13 => E(1), -- Q1
X_14 => E(0), -- Q0
X_15 => E(4), -- TC\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_169.vhd
0,0 → 1,163
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS169N: Synch. bidirectional 4-bit binary ctr --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_169 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_169 is
signal RS : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal PE : std_logic := '1';
signal CEP : std_logic := '1';
signal CET : std_logic := '1';
signal UD : std_logic := '1';
signal X, Y, Z : std_logic;
signal W : std_logic_vector(3 downto 0);
 
alias P : unsigned(3 downto 0) is B(3 downto 0);
alias CP : std_logic is CLK;
constant modulus : natural := 10;
constant limit : unsigned(3 downto 0) := to_unsigned(modulus-1, 4);
constant decade : boolean := false;
 
begin
CEP <= J(0);
CET <= J(1);
X <= and_reduce(W) and not CET;
Y <= nor_reduce(W) and not CET;
Z <= not X when UD = '1' else not Y;
D <= Z & W;
process(CP, RS) is -- Generate control signals
variable T2, T3 : natural := 0;
begin
if RS = '0' then
PE <= '0';
elsif rising_edge(CP) then
if T2 = 37 then
PE <= '0';
T2 := 0;
else
PE <= '1';
T2 := T2 + 1;
end if;
if T3 = 41 then
UD <= not UD;
T3 := 0;
else
T3 := T3 + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP) is
variable SW : std_logic_vector(3 downto 0);
variable R : unsigned(3 downto 0);
begin
if CP'event and CP = '1' then -- Everything is synchronous
SW := (PE, CEP, CET, UD);
case SW is
when "0000" | "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" | "0111"=> -- Load
R := unsigned(P);
when "1001" => -- Count up
if decade then
case R is
when "1001" => R := "0000";
when "1011" => R := "0100";
when "1101" => R := "0100";
when others => R := R + 1;
end case;
else
R := R + 1;
end if;
when "1000" => -- Count down
if decade then
case R is
when "0000" => R := "1001";
when "1010" => R := "0001";
when "1100" => R := "0011";
when "1110" => R := "0101";
when others => R := R - 1;
end case;
else
R := R - 1;
end if;
when others => -- No change
null;
end case;
end if;
W <= std_logic_vector(R);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS169N
port map(
X_1 => UD, -- U_D\
X_2 => CP, -- CP
X_3 => B(0), -- P0
X_4 => B(1), -- P1
X_5 => B(2), -- P2
X_6 => B(3), -- P3
X_7 => CEP, -- CEP\
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CET, -- CET\
X_11 => E(3), -- Q3
X_12 => E(2), -- Q2
X_13 => E(1), -- Q1
X_14 => E(0), -- Q0
X_15 => E(4), -- TC\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_17.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7417N: Hex buffer/driver (HV open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_17 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_17 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( J(0) );
D(1) <= TTL_OC( J(1) );
D(2) <= TTL_OC( J(2) );
D(3) <= TTL_OC( J(3) );
D(4) <= TTL_OC( J(4) );
D(5) <= TTL_OC( J(5) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7417N
port map(
X_1 => J(0), -- 1A
X_2 => E(0), -- 1Y\
X_3 => J(1), -- 2A
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 3A
X_6 => E(2), -- 3Y\
X_7 => open, -- GND
X_8 => E(3), -- 4Y\
X_9 => J(3), -- 4A
X_10 => E(4), -- 5Y\
X_11 => J(4), -- 5A
X_12 => E(5), -- 6Y\
X_13 => J(5), -- 6A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_170.vhd
0,0 → 1,132
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS170N: 4 X 4 register file (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_170 is -- Top-level bench
generic(
OC : boolean := true;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_170 is
subtype T_quad is std_logic_vector(4 downto 1);
type T_mem is array(3 downto 0) of T_quad;
subtype T_addr is natural range 3 downto 0;
 
signal J, B : unsigned(5 downto 0); -- Unused
signal D, E : T_quad; -- Expected & actual results
signal CLK, RS : std_logic;
signal RA, WA : unsigned(1 downto 0) := (others => '0');
signal DI : unsigned(4 downto 0);
signal RE, WE : std_logic := '1';
signal Phase : natural;
 
begin
RA <= J(1 downto 0);
WA <= B(1 downto 0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
variable ER : std_logic;
begin
ER := '1';
WE <= '1';
if RS = '0' then
DI <= (others => '0');
elsif rising_edge(CLK) then
DI <= DI + 1;
case to_integer(DI) is
when 5 | 6 | 7 | 8 => WE <= '0' after 15 ns;
when 9 |10 | 11 | 12 => ER := '0';
when 16 => DI <= (others => '0');
when others => null;
end case;
RE <= ER;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable mem : T_mem; -- Testbench memory
variable AR, AW : natural;
variable QI : T_quad;
begin
AR := TTL_to_integer(RA);
AW := TTL_to_integer(WA);
D <= (others => 'Z');
if WE = '0' then
mem(AW) := std_logic_vector(DI(3 downto 0));
end if;
if RE = '0' then
QI := mem(AR);
for i in D'range loop
D(i) <= TTL_OC(QI(i));
end loop;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS170N
port map(
X_1 => DI(1), -- D2
X_2 => DI(2), -- D3
X_3 => DI(3), -- D4
X_4 => RA(1), -- RA1
X_5 => RA(0), -- RA0
X_6 => E(4), -- Q4
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => E(2), -- Q2
X_10 => E(1), -- Q1
X_11 => RE, -- RE\
X_12 => WE, -- WE\
X_13 => WA(1), -- WA1
X_14 => WA(0), -- WA0
X_15 => DI(0), -- D1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_173.vhd
0,0 → 1,111
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS173N: 4-bit D-type register (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_173 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_173 is
signal RS, RSH : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal SR, DI : std_logic_vector(3 downto 0);
signal DIX : unsigned(4 downto 0);
signal IE1, IE2, OE1, OE2 : std_logic;
begin
RSH <= not RS;
IE1 <= BC(0);
IE2 <= BC(1);
OE1 <= BC(2);
OE2 <= BC(3);
 
DI <= std_logic_vector(DIX(3 downto 0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RSH) is
begin
if RSH = '1' then
SR <= (others => '0');
DIX <= (others => '0');
elsif rising_edge(CLK) then
if to_integer(DIX) = 4 then
DIX <= (others => '0');
else
DIX <= DIX + 1;
end if;
if (IE1 or IE2) = '0' then
SR <= DI;
end if;
end if;
end process;
D <= SR when (OE1 or OE2) = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS173N
port map(
X_1 => OE1, -- OE1\
X_2 => OE2, -- OE2\
X_3 => E(0), -- Q0
X_4 => E(1), -- Q1
X_5 => E(2), -- Q2
X_6 => E(3), -- Q3
X_7 => CLK, -- CP
X_8 => open, -- GND
X_9 => IE1, -- IE1\
X_10 => IE2, -- IE2\
X_11 => DI(3), -- D3
X_12 => DI(2), -- D2
X_13 => DI(1), -- D1
X_14 => DI(0), -- D0
X_15 => RSH, -- MR
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_174.vhd
0,0 → 1,90
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS174N: Hex D-flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_174 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_174 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal R : std_logic_vector(5 downto 0); -- Input
begin
R <= std_logic_vector(JC);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RS) is
begin
if RS = '0' then
D <= (others => '0');
elsif rising_edge(CLK) then
D <= R;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS174N
port map(
X_1 => RS, -- MR\
X_2 => E(0), -- Q0
X_3 => R(0), -- D0
X_4 => R(1), -- D1
X_5 => E(1), -- Q1
X_6 => R(2), -- D2
X_7 => E(2), -- Q2
X_8 => open, -- GND
X_9 => CLK, -- CP
X_10 => E(3), -- Q3
X_11 => R(3), -- D3
X_12 => E(4), -- Q4
X_13 => R(4), -- D4
X_14 => R(5), -- D5
X_15 => E(5), -- Q5
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_175.vhd
0,0 → 1,94
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS175N: Quad D-flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_175 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_175 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(3 downto 0); -- Input
begin
R <= std_logic_vector(JC);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RS) is
begin
if RS = '0' then
D(3 downto 0) <= (others => '0');
D(7 downto 4) <= (others => '1');
elsif rising_edge(CLK) then
for i in R'range loop
D(i) <= R(i);
D(4+i) <= not R(i);
end loop;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS175N
port map(
X_1 => RS, -- MR\
X_2 => E(0), -- Q0
X_3 => E(4), -- Q0\
X_4 => R(0), -- D0
X_5 => R(1), -- D1
X_6 => E(5), -- Q1\
X_7 => E(1), -- Q1
X_8 => open, -- GND
X_9 => CLK, -- CP
X_10 => E(2), -- Q2
X_11 => E(6), -- Q2\
X_12 => R(2), -- D2
X_13 => R(3), -- D3
X_14 => E(7), -- Q3\
X_15 => E(3), -- Q3
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_176.vhd
0,0 → 1,130
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74176N: Presettable decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_176 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_176 is
signal RS, PL : std_logic;
signal CLK, C0, C1 : std_logic;
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E, R : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
C0 <= CLK;
R <= std_logic_vector(J);
C1 <= D(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate irregular LD signal
-----------------------------------------------------------------------
process(RS, CLK) is
variable N : natural;
begin
if RS = '0' then
N := 1;
PL <= '1';
elsif rising_edge(CLK) then
if N >= 23 then
N := 1;
PL <= '0', '1' after 30 ns;
else
N := N + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(C0, PL, RS, R) is
variable Q0 : std_logic;
begin
if RS = '0' then
Q0 := '0';
elsif PL = '0' then
Q0 := R(0);
elsif falling_edge(C0) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(C1, PL, RS, R) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '0' then
Q31 := (others => '0');
elsif PL = '0' then
Q31 := unsigned(R(3 downto 1));
elsif falling_edge(C1) then
case TTL_to_integer(Q31) is
when 4 to 7 => Q31 := Q31 - 4;
when others => Q31 := Q31 + 1;
end case;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74176N
port map(
X_1 => PL, -- PL\
X_2 => E(2), -- Q2
X_3 => R(2), -- P2
X_4 => R(0), -- P0
X_5 => E(0), -- Q0
X_6 => C1, -- CP1\
X_7 => open, -- GND
X_8 => C0, -- CP0\
X_9 => E(1), -- Q1
X_10 => R(1), -- P1
X_11 => R(3), -- P3
X_12 => E(3), -- Q3
X_13 => RS, -- MR\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_177.vhd
0,0 → 1,127
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74177N: Presettable binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_177 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 160 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_177 is
signal RS, PL : std_logic;
signal CLK, C0, C1 : std_logic;
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E, R : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
C0 <= CLK;
R <= std_logic_vector(J);
C1 <= D(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate irregular LD signal
-----------------------------------------------------------------------
process(RS, CLK) is
variable N : natural;
begin
if RS = '0' then
N := 1;
PL <= '1';
elsif rising_edge(CLK) then
if N >= 23 then
N := 1;
PL <= '0', '1' after 30 ns;
else
N := N + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(C0, PL, RS, R) is
variable Q0 : std_logic;
begin
if RS = '0' then
Q0 := '0';
elsif PL = '0' then
Q0 := R(0);
elsif falling_edge(C0) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(C1, PL, RS, R) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '0' then
Q31 := (others => '0');
elsif PL = '0' then
Q31 := unsigned(R(3 downto 1));
elsif falling_edge(C1) then
Q31 := Q31 + 1;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74177N
port map(
X_1 => PL, -- PL\
X_2 => E(2), -- Q2
X_3 => R(2), -- P2
X_4 => R(0), -- P0
X_5 => E(0), -- Q0
X_6 => C1, -- CP1\
X_7 => open, -- GND
X_8 => C0, -- CP0\
X_9 => E(1), -- Q1
X_10 => R(1), -- P1
X_11 => R(3), -- P3
X_12 => E(3), -- Q3
X_13 => RS, -- MR\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_178.vhd
0,0 → 1,113
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74178N: 4-bit shift register --
-- Note: 74178 is 74179 without MR\ & Q3\ pins --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_178 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_178 is
signal RS, PE, SE : std_logic;
signal CLK,DS : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal P, REG : std_logic_vector(3 downto 0);
begin
D(3 downto 0) <= REG;
P <= std_logic_vector(JC(3 downto 0));
DS <= JC(4);
process(CLK, RS) is
variable N : natural := 1;
begin
if RS = '0' then
N := 1;
PE <= '0';
SE <= '0';
elsif falling_edge(CLK) then
PE <= '0';
SE <= '0';
N := N - 1;
case N is
when 1 => PE <= '1';
when 2 | 4 | 6 | 8 | 9 => SE <= '1';
when 0 => N := 16;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if falling_edge(CLK) then
if SE = '1' then
REG <= REG(2 downto 0) & DS;
elsif PE = '1' then
REG <= P;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74178N
port map(
X_1 => P(1), -- P1
X_2 => P(0), -- P0
X_3 => DS, -- DS
X_4 => E(0), -- Q0
X_5 => CLK, -- CP\
X_6 => E(1), -- Q1
X_7 => open, -- GND
X_8 => E(2), -- Q2
X_9 => PE, -- PE
X_10 => E(3), -- Q3
X_11 => SE, -- SE
X_12 => P(3), -- P3
X_13 => P(2), -- P2
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_179.vhd
0,0 → 1,117
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74179N: 4-bit shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_179 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_179 is
signal RS, PE, SE : std_logic;
signal CLK,DS : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal P, REG : std_logic_vector(3 downto 0);
begin
D(3 downto 0) <= REG;
D(4) <= not REG(3);
P <= std_logic_vector(JC(3 downto 0));
DS <= JC(4);
process(CLK, RS) is
variable N : natural := 1;
begin
if RS = '0' then
N := 1;
PE <= '0';
SE <= '0';
elsif falling_edge(CLK) then
PE <= '0';
SE <= '0';
N := N - 1;
case N is
when 1 => PE <= '1';
when 2 | 4 | 6 | 8 | 9 => SE <= '1';
when 0 => N := 16;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RS) is
begin
if RS = '0' then
REG <= (others => '0');
elsif falling_edge(CLK) then
if SE = '1' then
REG <= REG(2 downto 0) & DS;
elsif PE = '1' then
REG <= P;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74179N
port map(
X_1 => RS, -- MR\
X_2 => P(1), -- P1
X_3 => P(0), -- P0
X_4 => DS, -- DS
X_5 => E(0), -- Q0
X_6 => CLK, -- CP\ (falling)
X_7 => E(1), -- Q1
X_8 => open, -- GND
X_9 => E(2), -- Q2
X_10 => PE, -- PE
X_11 => E(3), -- Q3
X_12 => E(4), -- Q3\
X_13 => SE, -- SE
X_14 => P(3), -- P3
X_15 => P(2), -- P2
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_180.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74180N: 8-bit parity generator/checker --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_180 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 200 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_180 is
signal RS, I : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal EI, OI : std_logic;
constant SO : natural := 0;
constant SE : natural := 1;
begin
I <= xnor_reduce(std_logic_vector(JC(7 downto 0)));
EI <= JC(8);
OI <= not JC(9);
 
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable K : std_logic_vector(1 downto 0);
begin
K := EI & OI;
D(SE) <= EI xnor I;
D(SO) <= OI xnor I;
case K is
when "00" => D(SE) <= '1'; D(SO) <= '1';
when "01" => null;
when "10" => null;
when others => D(SE) <= '0'; D(SO) <= '0';
end case;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74180N
port map(
X_1 => JC(6), -- I6
X_2 => JC(7), -- I7
X_3 => EI, -- EI
X_4 => OI, -- OI
X_5 => E(SE), -- SE
X_6 => E(SO), -- SO
X_7 => open, -- GND
X_8 => JC(0), -- I0
X_9 => JC(1), -- I1
X_10 => JC(2), -- I2
X_11 => JC(3), -- I3
X_12 => JC(4), -- I4
X_13 => JC(5), -- I5
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_181.vhd
0,0 → 1,154
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- July, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS181N: 4-bit arithmetic/logic unit --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_181 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 1600 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_181 is
signal JC, BC : unsigned(13 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal A, B, F, S : unsigned(3 downto 0);
signal CI, M : std_logic;
signal CO, EQ, P, G : std_logic;
constant M1 : unsigned(3 downto 0) := (others => '1');
begin
S <= BC( 3 downto 0);
A <= BC( 7 downto 4);
B <= BC(11 downto 8);
CI <= BC(12);
M <= BC(13);
D <= CO & EQ & P & G & std_logic_vector(F);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable BB, XX, YY, ZZ, FF, LL : unsigned(3 downto 0);
variable MB : std_logic;
variable L01 : std_logic;
variable L02 : std_logic;
variable L03 : std_logic;
variable L04 : std_logic;
variable L05 : std_logic;
variable L06 : std_logic;
variable L07 : std_logic;
variable L08 : std_logic;
variable L09 : std_logic;
variable L10 : std_logic;
variable L11 : std_logic;
variable L12 : std_logic;
variable L13 : std_logic;
variable L14 : std_logic;
variable L15 : std_logic;
begin
MB := not ( M );
BB := not B;
for i in A'range loop
YY(i) := not ( ( B(i) and S(3) and A(i) ) or ( A(i) and S(2) and BB(i) ) );
XX(i) := not ( ( BB(i) and S(1) ) or ( S(0) and B(i) ) or A(i) );
end loop;
ZZ := XX xor YY;
L15 := ( XX(3) );
L11 := ( YY(3) and XX(2) );
L12 := ( YY(3) and YY(2) and XX(1) );
L13 := ( YY(3) and YY(2) and YY(1) and XX(0) );
L01 := not ( YY(3) and YY(2) and YY(1) and YY(0) and CI );
L02 := ( CI and YY(0) and YY(1) and YY(2) and MB );
L03 := ( YY(1) and YY(2) and XX(0) and MB );
L04 := ( YY(2) and XX(1) and MB );
L05 := ( XX(2) and MB );
L06 := ( CI and YY(0) and YY(1) and MB );
L07 := ( YY(1) and XX(0) and MB );
L08 := ( XX(1) and MB );
L09 := ( CI and YY(0) and MB );
L10 := ( XX(0) and MB );
LL(0) := not ( CI and MB );
LL(3) := not ( L02 or L03 or L04 or L05 );
LL(2) := not ( L06 or L07 or L08 );
LL(1) := not ( L09 or L10 );
L14 := not ( L15 or L11 or L12 or L13 );
FF := LL xor ZZ;
G <= L14;
CO <= not ( L14 and L01 );
P <= nand_reduce(std_logic_vector(YY));
EQ <= and_reduce(std_logic_vector(FF));
F <= FF;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS181N
port map(
X_1 => B(0), -- B(0)\
X_2 => A(0), -- A(0)\
X_3 => S(3), -- S(3)
X_4 => S(2), -- S(2)
X_5 => S(1), -- S(1)
X_6 => S(0), -- S(0)
X_7 => CI, -- Cn
X_8 => M, -- M
X_9 => E(0), -- F(0)\
X_10 => E(1), -- F(1)\
X_11 => E(2), -- F(2)\
X_12 => open, -- GND
X_13 => E(3), -- F(3)\
X_14 => E(6), -- A=B
X_15 => E(5), -- P\
X_16 => E(7), -- Cn+4
X_17 => E(4), -- G\
X_18 => B(3), -- B(3)\
X_19 => A(3), -- A(3)\
X_20 => B(2), -- B(2)\
X_21 => A(2), -- A(2)\
X_22 => B(1), -- B(1)\
X_23 => A(1), -- A(1)\
X_24 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_182.vhd
0,0 → 1,124
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- July, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS182N: Fast carry unit for 4 x LS181 --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_182 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 30 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_182 is
signal JC, BC : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
alias Cn is JC(0);
alias G0 is JC(1);
alias G1 is JC(2);
alias G2 is JC(3);
alias G3 is JC(4);
alias P0 is JC(5);
alias P1 is JC(6);
alias P2 is JC(7);
alias P3 is JC(8);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable L1 : std_logic;
variable L2 : std_logic;
variable L3 : std_logic;
variable L4 : std_logic;
variable L5 : std_logic;
variable L6 : std_logic;
variable L7 : std_logic;
variable L8 : std_logic;
variable L9 : std_logic;
variable L10 : std_logic;
variable L11 : std_logic;
variable L12 : std_logic;
variable L13 : std_logic;
variable N1 : std_logic;
begin
N1 := NOT ( CN );
L1 := ( G3 AND G2 AND G1 AND G0 );
L2 := ( P1 AND G3 AND G2 AND G1 );
L3 := ( P2 AND G3 AND G2 );
L4 := ( P3 AND G3 );
L5 := ( G2 AND G1 AND G0 AND N1 );
L6 := ( P0 AND G2 AND G1 AND G0 );
L7 := ( P1 AND G2 AND G1 );
L8 := ( P2 AND G2 );
L9 := ( G1 AND G0 AND N1 );
L10 := ( P0 AND G1 AND G0 );
L11 := ( P1 AND G1 );
L12 := ( G0 AND N1 );
L13 := ( P0 AND G0 );
D(4) <= ( P3 OR P2 OR P1 OR P0 );
D(3) <= ( L1 OR L2 OR L3 OR L4 );
D(2) <= NOT ( L5 OR L6 OR L7 OR L8 );
D(1) <= NOT ( L9 OR L10 OR L11 );
D(0) <= NOT ( L12 OR L13 );
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS182N
port map(
X_1 => G1, -- G1
X_2 => P1, -- P1
X_3 => G0, -- G0
X_4 => P0, -- P0
X_5 => G3, -- G3
X_6 => P3, -- P3
X_7 => E(4), -- P
X_8 => open, -- GND
X_9 => E(2), -- Cnz
X_10 => E(3), -- G
X_11 => E(1), -- Cny
X_12 => E(0), -- Cnx
X_13 => Cn, -- Cn
X_14 => G2, -- G2
X_15 => P2, -- P2
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_183.vhd
0,0 → 1,104
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- July, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H183N: Dual high-speed adder --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_183 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 25 ns;
Finish : time := 2 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_183 is
subtype Pair is std_logic_vector(1 downto 0);
subtype Triple is std_logic_vector(2 downto 0);
type Table is array(0 to 7) of Pair;
signal JC, BC : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal X, Y : Pair;
 
alias CIa is BC(0);
alias Aa is BC(1);
alias Ba is BC(2);
alias CIb is BC(3);
alias Ab is BC(4);
alias Bb is BC(5);
constant SUM : natural := 1;
constant CARRY : natural := 0;
impure function Adder(A, B, C : std_logic) return Pair is -- impure, as it calls "now"
constant ANS : Table := (("00"), ("10"), ("10"), ("01"), ("10"), ("01"), ("01"), ("11"));
variable Z : unsigned(2 downto 0) := (others => '0');
variable R : natural range 7 downto 0 := 0;
begin
if now > 5 ns then -- Avoid metavalues at T=0
Z := A & B & C;
R := to_integer(Z);
end if;
return ANS(R);
end function;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
X <= Adder(Aa, Ba, CIa);
Y <= Adder(Ab, Bb, CIb);
D <= (Y(SUM), Y(CARRY), X(SUM), X(CARRY));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H183N
port map(
X_1 => Aa, -- Aa
X_3 => Ba, -- Ba
X_4 => CIa, -- CIa
X_5 => E(0), -- COa
X_6 => E(1), -- Sa
X_7 => open, -- GND
X_8 => E(3), -- Sb
X_10 => E(2), -- COb
X_11 => CIb, -- CIb
X_12 => Bb, -- Bb
X_13 => Ab, -- Ab
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_189.vhd
0,0 → 1,153
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- July, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS189N: 64-bit RAM (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_189 is -- Top-level bench
generic(
OC : boolean := false;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_189 is
signal J, B : unsigned(5 downto 0); -- Unused
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TTLword := (others => '0');
signal DI, Q, QQ : TTLquad;
signal CE, WE : std_logic;
 
signal W : std_logic;
signal Phase : natural;
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1;
when 1 => WR <= W; Phase <= 2;
when 2 => WR <= '1'; Phase <= 3;
when others => CS <= '1'; WR <= '1'; Phase <= 0;
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(3 downto 0);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := "0110";
elsif rising_edge(CLK) and Phase = 3 then
if AD = "1111" then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
for i in TD'range loop
DI(i+1) <= TD(i);
end loop;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CE <= WR and not CS;
WE <= not(WR or CS);
process(CE, WE, AD, DI) is
variable mem : TTLmem; -- Testbench memory
variable adr : TTLaddr;
variable QI : TTLquad;
begin
adr := TTL_to_integer(AD);
if WE'event and WE = '1' then
mem(adr) := not DI; -- Data is output inverted
end if;
if CE = '1' then
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then
for i in Q'range loop
Q(i) <= TTL_OC(QI(i));
end loop;
else
Q <= QI;
end if;
end process;
D <= Q;
E <= QQ;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS189N
port map(
X_1 => AD(0), -- A0
X_2 => CS, -- CS\
X_3 => WR, -- WE\
X_4 => DI(1), -- D1
X_5 => QQ(1), -- Q1\
X_6 => DI(2), -- D2
X_7 => QQ(2), -- Q2\
X_8 => open, -- GND
X_9 => QQ(3), -- Q3\
X_10 => DI(3), -- D3
X_11 => QQ(4), -- Q4\
X_12 => DI(4), -- D4
X_13 => AD(3), -- A3
X_14 => AD(2), -- A2
X_15 => AD(1), -- A1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_190.vhd
0,0 → 1,138
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS190N: Up/down decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_190 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 15 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_190 is
signal JC, BC : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal P : unsigned(3 downto 0);
signal CP : std_logic;
signal RS, PL : std_logic;
signal CE, UD : std_logic;
signal T1, T2, T3, T4, T5,
T6, T7, T8, T9, T10,
T11, T12, T13, T14, T15,
T16 : std_logic;
 
signal Q, QB, X : unsigned(3 downto 0);
begin
P <= JC(6 downto 3);
CE <= BC(6);
process(CP) is
begin
if rising_edge(CP) then
PL <= RS and nand_reduce(std_logic_vector(BC(4 downto 0))) after 10 ns, '1' after 80 ns;
UD <= BC(5);
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CP,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
T1 <= not (UD);
T2 <= not (UD or CE);
T3 <= not (CE or T1);
T4 <= not (QB(1) and QB(2) and QB(3));
T5 <= T3 and QB(0) and T4;
T6 <= Q(0) and QB(3) and T2;
T7 <= T4 and T3 and QB(0) and QB(1);
T8 <= Q(0) and Q(1) and T2;
T9 <= T3 and QB(0) and QB(1) and QB(2);
T10 <= Q(0) and Q(3) and T2;
T11 <= Q(0) and Q(1) and Q(2) and T2;
X(0) <= not (CE);
X(1) <= T5 or T6;
X(2) <= T7 or T8;
X(3) <= T9 or T10 or T11;
process(CP, PL) is
begin
if PL = '0' then
Q <= P;
elsif rising_edge(CP) and (CE = '0') then
Q <= Q xor X; -- 'T' flipflops
end if;
end process;
QB <= not Q;
T15 <= (T1 and Q(0) and Q(3)); -- True for count = 9, 11, 13, 15
T16 <= (UD and QB(0) and QB(1) and QB(2) and QB(3));
T12 <= (T15 or T16);
T13 <= not (CP);
T14 <= not (CE);
D(3 downto 0) <= std_logic_vector(Q);
D(4) <= T12;
D(5) <= not (T13 and T14 and T12);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS190N
port map(
X_1 => P(1), -- P1
X_2 => E(1), -- Q1
X_3 => E(0), -- Q0
X_4 => CE, -- CE\
X_5 => UD, -- U\/D
X_6 => E(2), -- Q2
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => P(3), -- P3
X_10 => P(2), -- P2
X_11 => PL, -- PL\
X_12 => E(4), -- TC
X_13 => E(5), -- RC\
X_14 => CP, -- CP
X_15 => P(0), -- P0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_191.vhd
0,0 → 1,133
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS191N: Up/down binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_191 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 15 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_191 is
signal JC, BC : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal P : unsigned(3 downto 0);
signal CP : std_logic;
signal RS, PL : std_logic;
signal CE, UD : std_logic;
signal T1, T2, T3, T4, T5,
T6, T7, T8, T9, T10,
T11, T12, T13, T14 : std_logic;
 
signal Q, QB, X : unsigned(3 downto 0);
begin
P <= JC(6 downto 3);
CE <= BC(6);
process(CP) is
begin
if rising_edge(CP) then
PL <= RS and nand_reduce(std_logic_vector(BC(4 downto 0))) after 10 ns, '1' after 80 ns;
UD <= BC(5);
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CP,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
T1 <= not (UD);
T2 <= not (UD or CE);
T3 <= not (CE or T1);
T4 <= T1 and Q(0) and Q(1) and Q(2) and Q(3);
T5 <= UD and QB(0) and QB(1) and QB(2) and QB(3);
T6 <= T3 and QB(0);
T7 <= Q(0) and T2;
T8 <= T3 and QB(0) and QB(1);
T9 <= Q(0) and Q(1) and T2;
T10 <= T3 and QB(0) and QB(1) and QB(2);
T11 <= Q(0) and Q(1) and Q(2) and T2;
X(0) <= not (CE);
X(1) <= T6 or T7;
X(2) <= T8 or T9;
X(3) <= T10 or T11;
T12 <= not (CP);
T13 <= not (CE);
T14 <= T4 or T5;
process(CP, PL) is
begin
if PL = '0' then
Q <= P;
elsif rising_edge(CP) and (CE = '0') then
Q <= Q xor X; -- 'T' flipflops
end if;
end process;
QB <= not Q;
D(3 downto 0) <= std_logic_vector(Q(3 downto 0));
D(4) <= T14;
D(5) <= not (T12 and T13 and T14);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS191N
port map(
X_1 => P(1), -- P1
X_2 => E(1), -- Q1
X_3 => E(0), -- Q0
X_4 => CE, -- CE\
X_5 => UD, -- U\/D
X_6 => E(2), -- Q2
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => P(3), -- P3
X_10 => P(2), -- P2
X_11 => PL, -- PL\
X_12 => E(4), -- TC
X_13 => E(5), -- RC\
X_14 => CP, -- CP
X_15 => P(0), -- P0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_192.vhd
0,0 → 1,142
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS192N: Up/down decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_192 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 15 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_192 is
signal JC, BC : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal P : unsigned(3 downto 0);
signal CLK, CPU, CPD : std_logic;
signal MR, RS, PL : std_logic;
signal Q, QB : unsigned(3 downto 0);
signal T1, T2, T3, T4, T5,
T6, T7, T8, T9, T10,
T11, T12 : std_logic;
signal CX, CL, PR, CC : std_logic_vector(3 downto 0);
 
begin
P <= JC(6 downto 3);
MR <= not RS; -- Active high
process(CLK) is
begin
if rising_edge(CLK) then
PL <= nand_reduce(std_logic_vector(BC(4 downto 0))) after 10 ns, '1' after 80 ns;
CPU <= BC(5);
CPD <= not BC(5);
elsif falling_edge(CLK) then -- NB Inactive clock should be high
CPU <= '1';
CPD <= '1';
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
T1 <= not (CPD);
T2 <= not (CPU);
T3 <= not (QB(1) and QB(2) and QB(3));
T4 <= T1 and QB(0) and T3;
T5 <= Q(0) and QB(3) and T2;
T6 <= T3 and T1 and QB(0) and QB(1);
T7 <= Q(0) and Q(1) and T2;
T8 <= T1 and QB(0) and QB(1) and QB(2);
T9 <= Q(0) and Q(3) and T2;
T10 <= Q(0) and Q(1) and Q(2) and T2;
T11 <= not (MR);
T12 <= not (PL);
CX(0) <= not (T1 or T2);
CX(1) <= not (T4 or T5);
CX(2) <= not (T6 or T7);
CX(3) <= not (T8 or T9 or T10);
G: for i in CX'range generate
begin
PR(i) <= not (P(i) and T12 and T11);
CC(i) <= not (PR(i) and T12);
CL(i) <= (T11 and CC(i));
process(CX, PR, CL) is -- A 'T' flipflop
begin
if CL(i) = '0' then
Q(i) <= '0';
elsif PR(i) = '0' then
Q(i) <= '1';
elsif rising_edge(CX(i)) then
Q(i) <= not Q(i);
end if;
end process;
end generate;
QB <= not Q;
D(3 downto 0) <= std_logic_vector(Q);
D(4) <= not (Q(0) and Q(3) and T2);
D(5) <= not (T1 and QB(0) and QB(1) and QB(2) and QB(3));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS192N
port map(
X_1 => P(1), -- P1
X_2 => E(1), -- Q1
X_3 => E(0), -- Q0
X_4 => CPD, -- CPD
X_5 => CPU, -- CPU
X_6 => E(2), -- Q2
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => P(3), -- P3
X_10 => P(2), -- P2
X_11 => PL, -- PL\
X_12 => E(4), -- TCU\
X_13 => E(5), -- TCD\
X_14 => MR, -- MR
X_15 => P(0), -- P0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_193.vhd
0,0 → 1,139
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS193N: Up/down binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_193 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 15 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_193 is
signal JC, BC : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal P : unsigned(3 downto 0);
signal CLK, CPU, CPD : std_logic;
signal MR, RS, PL : std_logic;
signal Q, QB : unsigned(3 downto 0);
signal CX, CL, PR, CC : std_logic_vector(3 downto 0);
signal T1, T2, T3, T4, T5,
T6, T7, T8, T9, T10 : std_logic;
 
begin
P <= JC(6 downto 3);
MR <= not RS; -- Active high
process(CLK) is
begin
if rising_edge(CLK) then
PL <= nand_reduce(std_logic_vector(BC(4 downto 0))) after 10 ns, '1' after 80 ns;
CPU <= BC(5);
CPD <= not BC(5);
elsif falling_edge(CLK) then -- NB Inactive clock should be high
CPU <= '1';
CPD <= '1';
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
T1 <= not (CPD);
T2 <= not (CPU);
T3 <= T1 and QB(0);
T4 <= Q(0) and T2;
T5 <= T1 and QB(0) and QB(1);
T6 <= Q(0) and Q(1) and T2;
T7 <= T1 and QB(0) and QB(1) and QB(2);
T8 <= Q(0) and Q(1) and Q(2) and T2;
T9 <= not (MR);
T10 <= not (PL);
CX(0) <= not (T1 or T2);
CX(1) <= not (T3 or T4);
CX(2) <= not (T5 or T6);
CX(3) <= not (T7 or T8);
G: for i in CX'range generate
begin
PR(i) <= not (P(i) and T10 and T9);
CC(i) <= not (PR(i) and T10);
CL(i) <= (T9 and CC(i));
process(CX, PR, CL) is -- A 'T' flipflop
begin
if CL(i) = '0' then
Q(i) <= '0';
elsif PR(i) = '0' then
Q(i) <= '1';
elsif rising_edge(CX(i)) then
Q(i) <= not Q(i);
end if;
end process;
end generate;
QB <= not Q;
D(3 downto 0) <= std_logic_vector(Q);
D(4) <= not (Q(0) and Q(1) and Q(2) and Q(3) and T2);
D(5) <= not (T1 and QB(0) and QB(1) and QB(2) and QB(3));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS193N
port map(
X_1 => P(1), -- P1
X_2 => E(1), -- Q1
X_3 => E(0), -- Q0
X_4 => CPD, -- CPD
X_5 => CPU, -- CPU
X_6 => E(2), -- Q2
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => P(3), -- P3
X_10 => P(2), -- P2
X_11 => PL, -- PL\
X_12 => E(4), -- TCU\
X_13 => E(5), -- TCD\
X_14 => MR, -- MR
X_15 => P(0), -- P0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_194.vhd
0,0 → 1,108
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS194N: 4-bit bidirectional shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_194 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 15 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_194 is
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal P : unsigned(3 downto 0);
signal CLK, RS : std_logic;
signal S : std_logic_vector(1 downto 0);
signal DR, DL : std_logic;
-- NB Q3 is considered the rightmost bit (see data sheet)
signal M, R, Q : unsigned(0 to 3);
begin
(DR, DL, P) <= BC(5 downto 0);
S(0) <= and_reduce(std_logic_vector(JC(4 downto 0)));
S(1) <= nor_reduce(std_logic_vector(JC(4 downto 0)));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
M <= P(3) & P(2) & P(1) & P(0);
with S select R <=
M when "11", -- Load
Q(1 to 3) & DL when "10", -- Left
DR & Q(0 to 2) when "01", -- Right
Q when others; -- Hold
process(CLK, RS) is
begin
if RS = '0' then
Q <= (others => '0');
elsif rising_edge(CLK) then
Q <= R;
end if;
end process;
(D(3), D(2), D(1), D(0)) <= Q;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS194N
port map(
X_1 => RS, -- MR\
X_2 => DR, -- DSR
X_3 => P(0), -- P0
X_4 => P(1), -- P1
X_5 => P(2), -- P2
X_6 => P(3), -- P3
X_7 => DL, -- DSL
X_8 => open, -- GND
X_9 => S(0), -- S(0)
X_10 => S(1), -- S(1)
X_11 => CLK, -- CP
X_12 => E(3), -- Q3
X_13 => E(2), -- Q2
X_14 => E(1), -- Q1
X_15 => E(0), -- Q0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_195.vhd
0,0 → 1,130
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS195N: Universal 4-bit shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_195 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 15 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_195 is
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal P : unsigned(3 downto 0);
signal CLK, RS : std_logic;
signal J, KB, PE : std_logic;
signal L1 : std_logic;
signal L2 : std_logic;
signal L3 : std_logic;
signal L4 : std_logic;
signal L5 : std_logic;
signal L6 : std_logic;
signal L7 : std_logic;
signal L8 : std_logic;
signal L9 : std_logic;
signal L10 : std_logic;
signal L11 : std_logic;
signal L12 : std_logic;
signal L13 : std_logic;
signal L14 : std_logic;
signal N1 : std_logic;
signal N2 : std_logic;
signal N3 : std_logic;
signal N4 : std_logic;
signal N5 : std_logic;
signal N6 : std_logic;
begin
(J, KB, P) <= BC(5 downto 0);
PE <= and_reduce(std_logic_vector(JC(5 downto 0)));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
N1 <= not (PE);
N2 <= PE;
L1 <= not (N3);
L2 <= L1 and J and N2;
L3 <= N2 and KB and N3;
L4 <= N1 and P(0);
L5 <= L2 or L3 or L4;
L6 <= N3 and N2;
L7 <= N1 and P(1);
L8 <= L6 or L7;
L9 <= N4 and N2;
L10 <= N1 and P(2);
L11 <= L9 or L10;
L12 <= N5 and N2;
L13 <= N1 and P(3);
L14 <= L12 or L13;
D38 : TTL_FF port map(q=>N3, d=>L5, clk=>CLK, cl=>RS);
D39 : TTL_FF port map(q=>N4, d=>L8, clk=>CLK, cl=>RS);
D40 : TTL_FF port map(q=>N5, d=>L11, clk=>CLK, cl=>RS);
D41 : TTL_FF port map(q=>N6, d=>L14, clk=>CLK, cl=>RS);
D(0) <= N3;
D(1) <= N4;
D(2) <= N5;
D(3) <= N6;
D(4) <= not (N6);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS195N
port map(
X_1 => RS, -- MR\
X_2 => J, -- J
X_3 => KB, -- K\
X_4 => P(0), -- P0
X_5 => P(1), -- P1
X_6 => P(2), -- P2
X_7 => P(3), -- P3
X_8 => open, -- GND
X_9 => PE, -- PE\
X_10 => CLK, -- CP
X_11 => E(4), -- Q3\
X_12 => E(3), -- Q3
X_13 => E(2), -- Q2
X_14 => E(1), -- Q1
X_15 => E(0), -- Q0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_196.vhd
0,0 → 1,130
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS196N: Presettable decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_196 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_196 is
signal RS, PL : std_logic;
signal CLK, C0, C1 : std_logic;
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E, R : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
C0 <= CLK;
R <= std_logic_vector(J);
C1 <= D(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate irregular LD signal
-----------------------------------------------------------------------
process(RS, CLK) is
variable N : natural;
begin
if RS = '0' then
N := 1;
PL <= '1';
elsif rising_edge(CLK) then
if N >= 23 then
N := 1;
PL <= '0', '1' after 30 ns;
else
N := N + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(C0, PL, RS, R) is
variable Q0 : std_logic;
begin
if RS = '0' then
Q0 := '0';
elsif PL = '0' then
Q0 := R(0);
elsif falling_edge(C0) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(C1, PL, RS, R) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '0' then
Q31 := (others => '0');
elsif PL = '0' then
Q31 := unsigned(R(3 downto 1));
elsif falling_edge(C1) then
case TTL_to_integer(Q31) is
when 4 to 7 => Q31 := Q31 - 4;
when others => Q31 := Q31 + 1;
end case;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS196N
port map(
X_1 => PL, -- PL\
X_2 => E(2), -- Q2
X_3 => R(2), -- P2
X_4 => R(0), -- P0
X_5 => E(0), -- Q0
X_6 => C1, -- CP1\
X_7 => open, -- GND
X_8 => C0, -- CP0\
X_9 => E(1), -- Q1
X_10 => R(1), -- P1
X_11 => R(3), -- P3
X_12 => E(3), -- Q3
X_13 => RS, -- MR\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_197.vhd
0,0 → 1,127
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS197N: Presettable binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_197 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 160 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_197 is
signal RS, PL : std_logic;
signal CLK, C0, C1 : std_logic;
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E, R : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
C0 <= CLK;
R <= std_logic_vector(J);
C1 <= D(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate irregular LD signal
-----------------------------------------------------------------------
process(RS, CLK) is
variable N : natural;
begin
if RS = '0' then
N := 1;
PL <= '1';
elsif rising_edge(CLK) then
if N >= 23 then
N := 1;
PL <= '0', '1' after 30 ns;
else
N := N + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(C0, PL, RS, R) is
variable Q0 : std_logic;
begin
if RS = '0' then
Q0 := '0';
elsif PL = '0' then
Q0 := R(0);
elsif falling_edge(C0) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(C1, PL, RS, R) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '0' then
Q31 := (others => '0');
elsif PL = '0' then
Q31 := unsigned(R(3 downto 1));
elsif falling_edge(C1) then
Q31 := Q31 + 1;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS197N
port map(
X_1 => PL, -- PL\
X_2 => E(2), -- Q2
X_3 => R(2), -- P2
X_4 => R(0), -- P0
X_5 => E(0), -- Q0
X_6 => C1, -- CP1\
X_7 => open, -- GND
X_8 => C0, -- CP0\
X_9 => E(1), -- Q1
X_10 => R(1), -- P1
X_11 => R(3), -- P3
X_12 => E(3), -- Q3
X_13 => RS, -- MR\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_198.vhd
0,0 → 1,130
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS198N: 8-bit right/left shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_198 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 50 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_198 is
signal CLK, RS : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 to 7); -- Expected & actual results
signal S : std_logic_vector(1 downto 0);
signal P, Q : std_logic_vector(0 to 7);
signal DSR, DSL : std_logic;
signal L1 : std_logic;
signal L2 : std_logic;
signal L3 : std_logic;
signal L4 : std_logic;
signal N0 : std_logic;
signal T1, T2, T3, T4 : std_logic_vector(0 to 7);
 
 
begin
P <= std_logic_vector(JC(7 downto 0));
DSR <= JC(8);
DSL <= JC(9);
S <= std_logic_vector(BC(5 downto 4));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
L1 <= not S(1);
L2 <= not S(0);
L3 <= L1 and L2;
L4 <= not(L1 or L2);
N0 <= CLK or L3;
T1(0) <= DSR and L1;
T3(7) <= L2 and DSL;
G1: for i in 1 to 7 generate
begin
T1(i) <= (Q(i-1) and L1);
end generate;
G2: for i in 0 to 6 generate
begin
T3(i) <= L2 and Q(i+1);
end generate;
G3: for i in 0 to 7 generate
begin
T2(i) <= L4 and P(i);
T4(i) <= T1(i) or T2(i) or T3(i);
DQ : TTL_FF port map(q=>Q(i), d=>T4(i), clk=>N0, cl=>RS);
end generate;
D <= Q;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS198N
port map(
X_1 => S(0), -- S(0)
X_2 => DSR, -- DSR
X_3 => P(0), -- P0
X_4 => E(0), -- Q0
X_5 => P(1), -- P1
X_6 => E(1), -- Q1
X_7 => P(2), -- P2
X_8 => E(2), -- Q2
X_9 => P(3), -- P3
X_10 => E(3), -- Q3
X_11 => CLK, -- CP
X_12 => open, -- GND
X_13 => RS, -- MR\
X_14 => E(4), -- Q4
X_15 => P(4), -- P4
X_16 => E(5), -- Q5
X_17 => P(5), -- P5
X_18 => E(6), -- Q6
X_19 => P(6), -- P6
X_20 => E(7), -- Q7
X_21 => P(7), -- P7
X_22 => DSL, -- DSL
X_23 => S(1), -- S(1)
X_24 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_199.vhd
0,0 → 1,119
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS199N: 8-bit parallel IO shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_199 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 50 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_199 is
signal CLK, RS : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 to 7); -- Expected & actual results
signal P, Q : std_logic_vector(0 to 7);
signal J, KB, CP1, CP2, PE, CP, I : std_logic;
signal JKB : std_logic_vector(1 downto 0);
 
begin
P <= std_logic_vector(BC(7 downto 0)) after 1 ns; -- Be sure CP evaluates first
(J, KB, PE) <= JC(2 downto 0) after 1 ns;
CP1 <= CLK;
CP2 <= '1', '0' after 288 ns;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CP <= CP1 or CP2;
JKB <= J & KB;
with JKB select I <=
'0' when "00",
not Q(0) when "10",
'1' when "11",
Q(0) when others;
process(RS, CP) is
begin
if RS = '0' then
Q <= (others => '0');
elsif rising_edge(CP) then
if PE <= '0' then
Q <= P;
else
Q <= I & Q(0 to 6);
end if;
end if;
end process;
D <= (Q(0), Q(1), Q(2), Q(3), Q(4), Q(5), Q(6), Q(7));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS199N
port map(
X_1 => KB, -- in KB\
X_2 => J, -- in J
X_3 => P(0), -- in P0
X_4 => E(0), -- out Q0
X_5 => P(1), -- in P1
X_6 => E(1), -- out Q1
X_7 => P(2), -- in P2
X_8 => E(2), -- out Q2
X_9 => P(3), -- in P3
X_10 => E(3), -- out Q3
X_11 => CP1, -- in CP1
X_12 => open, -- inout GND
X_13 => CP2, -- in CP2
X_14 => RS, -- in MR\
X_15 => E(4), -- out Q4
X_16 => P(4), -- in P4
X_17 => E(5), -- out Q5
X_18 => P(5), -- in P5
X_19 => E(6), -- out Q6
X_20 => P(6), -- in P6
X_21 => E(7), -- out Q7
X_22 => P(7), -- in P7
X_23 => PE, -- in PE\
X_24 => open -- inout Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_20.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS20N: Dual 4-input NAND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_20 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_20 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( J(0) and J(1) and J(2) and J(3) );
D(1) <= not( J(4) and J(5) and J(6) and J(7) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS20N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
--
X_4 => J(2), -- 1C
X_5 => J(3), -- 1D
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2D
X_10 => J(5), -- 2C
--
X_12 => J(6), -- 2B
X_13 => J(7), -- 2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_21.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS21N: Dual 4-input AND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_21 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_21 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= J(0) and J(1) and J(2) and J(3);
D(1) <= J(4) and J(5) and J(6) and J(7);
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS21N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
--
X_4 => J(2), -- 1C
X_5 => J(3), -- 1D
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2D
X_10 => J(5), -- 2C
--
X_12 => J(6), -- 2B
X_13 => J(7), -- 2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_22.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS22N: Dual 4-input NAND gate (o/c) (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_22 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_22 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not( J(0) and J(1) and J(2) and J(3) ) );
D(1) <= TTL_OC( not( J(4) and J(5) and J(6) and J(7) ) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS22N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
--
X_4 => J(2), -- 1C
X_5 => J(3), -- 1D
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2D
X_10 => J(5), -- 2C
--
X_12 => J(6), -- 2B
X_13 => J(7), -- 2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_221.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- August, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS221N: Dual monostable multivibrator --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_221 is -- Top-level bench
end entity;
 
architecture Test of Testbench_221 is
signal S, Q : std_logic_vector(1 downto 0); -- Triggers & outputs
signal W, N : std_logic_vector(1 downto 0); -- Wide & narrow windows
begin
S(0) <= '0',
'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
S(1) <= '0',
'1' after 250 ns, '0' after 350 ns, -- Trigger, let it time out
'1' after 15000 ns, '0' after 15100 ns, -- Trigger again
'1' after 16000 ns, '0' after 16100 ns; -- This should retrigger
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
W(0) <= '0',
'1' after 220 ns, '0' after 9330 ns,
'1' after 15020 ns, '0' after 25080 ns;
N(0) <= '0',
'1' after 350 ns, '0' after 9250 ns,
'1' after 15090 ns, '0' after 25000 ns;
 
W(1) <= '0',
'1' after 220 ns, '0' after 10330 ns,
'1' after 15020 ns, '0' after 26080 ns;
N(1) <= '0',
'1' after 350 ns, '0' after 10250 ns,
'1' after 15090 ns, '0' after 26000 ns;
 
-----------------------------------------------------------------------
-- Validate the results
-----------------------------------------------------------------------
G: for i in Q'range generate
begin
process(W(i), N(i), Q(i)) is
begin
if (rising_edge(W(i)) and Q(i) = '1') or -- W must rise before Q
(rising_edge(N(i)) and Q(i) = '0') or -- Q must rise before N
(falling_edge(N(i)) and Q(i) = '0') or -- N must fall before Q
(falling_edge(W(i)) and Q(i) = '1') then -- Q must fall before W
assert false
report "Bad monostable pulse"
severity warning;
end if;
end process;
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS221N
generic map(
W1 => 10 us, -- Pulse widths
W2 => 9 us
)
port map(
X_1 => '0', -- A1\
X_2 => S(0), -- B1
X_3 => '1', -- CD1\
X_4 => open, -- Q1\
X_5 => Q(1), -- Q2
X_6 => open, -- Cx2
X_7 => open, -- Rx2Cx2
X_8 => open, -- GND
X_9 => '0', -- A2\
X_10 => S(1), -- B2
X_11 => '1', -- CD2\
X_12 => open, -- Q2\
X_13 => Q(0), -- Q1
X_14 => open, -- Cx1
X_15 => open, -- Rx1Cx1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_240.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS240N: Octal buffer/line driver (3-state ops) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_240 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_240 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal OEA, OEB : std_logic;
signal IA, IB : std_logic_vector(3 downto 0);
begin
OEA <= JC(9);
OEB <= JC(8);
IA <= std_logic_vector(BC(4 downto 1));
IB <= std_logic_vector(BC(3 downto 0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
GG: for j in IA'range generate
begin
D(j) <= not IA(j) when OEA = '0' else 'Z';
D(j+4) <= not IB(j) when OEB = '0' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS240N
port map(
X_1 => OEA, -- OEA\
X_2 => IA(0), -- IA0
X_3 => E(4), -- YB0\
X_4 => IA(1), -- IA1
X_5 => E(5), -- YB1\
X_6 => IA(2), -- IA2
X_7 => E(6), -- YB2\
X_8 => IA(3), -- IA3
X_9 => E(7), -- YB3\
X_10 => open, -- GND
X_11 => IB(3), -- IB3
X_12 => E(3), -- YA3\
X_13 => IB(2), -- IB2
X_14 => E(2), -- YA2\
X_15 => IB(1), -- IB1
X_16 => E(1), -- YA1\
X_17 => IB(0), -- IB0
X_18 => E(0), -- YA0\
X_19 => OEB, -- OEB\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_241.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS241N: Octal buffer/line driver (3-state ops) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_241 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_241 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal OEA, OEB : std_logic;
signal IA, IB : std_logic_vector(3 downto 0);
begin
OEA <= JC(9);
OEB <= JC(8);
IA <= std_logic_vector(BC(4 downto 1));
IB <= std_logic_vector(BC(3 downto 0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
GG: for j in IA'range generate
begin
D(j) <= IA(j) when OEA = '0' else 'Z';
D(j+4) <= IB(j) when OEB = '1' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS241N
port map(
X_1 => OEA, -- OEA\
X_2 => IA(0), -- IA0
X_3 => E(4), -- YB0
X_4 => IA(1), -- IA1
X_5 => E(5), -- YB1
X_6 => IA(2), -- IA2
X_7 => E(6), -- YB2
X_8 => IA(3), -- IA3
X_9 => E(7), -- YB3
X_10 => open, -- GND
X_11 => IB(3), -- IB3
X_12 => E(3), -- YA3
X_13 => IB(2), -- IB2
X_14 => E(2), -- YA2
X_15 => IB(1), -- IB1
X_16 => E(1), -- YA1
X_17 => IB(0), -- IB0
X_18 => E(0), -- YA0
X_19 => OEB, -- OEB
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_242.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS242N: Quad bus transceiver (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_242 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_242 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(8 downto 1); -- Expected & actual results
signal A2B, B2A : std_logic;
signal IA : std_logic_vector(4 downto 1);
begin
IA <= std_logic_vector(JC(3 downto 0));
A2B <= BC(0);
B2A <= BC(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-- Special version for bidirectional circuits
-----------------------------------------------------------------------
GG: process(all) is
begin
for j in IA'range loop
D(j) <= IA(j) xnor A2B;
D(j+4) <= IA(j) xor B2A;
E(j) <= not IA(j) when A2B = '0' else 'Z';
E(j+4) <= not IA(j) when B2A = '1' else 'Z';
end loop;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS242N
port map(
X_1 => A2B, -- A2B\
--
X_3 => E(1), -- A1
X_4 => E(2), -- A2
X_5 => E(3), -- A3
X_6 => E(4), -- A4
X_7 => open, -- GND
X_8 => E(8), -- B4\
X_9 => E(7), -- B3\
X_10 => E(6), -- B2\
X_11 => E(5), -- B1\
--
X_13 => B2A, -- B2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_243.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS243N: Quad bus transceiver (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_243 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_243 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(8 downto 1); -- Expected & actual results
signal A2B, B2A : std_logic;
signal IA : std_logic_vector(4 downto 1);
begin
IA <= std_logic_vector(JC(3 downto 0));
A2B <= BC(0);
B2A <= BC(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-- Special version for bidirectional circuits
-----------------------------------------------------------------------
GG: process(all) is
begin
for j in IA'range loop
D(j) <= IA(j);
D(j+4) <= IA(j);
E(j) <= IA(j) when A2B = '0' else 'Z';
E(j+4) <= IA(j) when B2A = '1' else 'Z';
end loop;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS243N
port map(
X_1 => A2B, -- A2B\
--
X_3 => E(1), -- A1
X_4 => E(2), -- A2
X_5 => E(3), -- A3
X_6 => E(4), -- A4
X_7 => open, -- GND
X_8 => E(8), -- B4\
X_9 => E(7), -- B3\
X_10 => E(6), -- B2\
X_11 => E(5), -- B1\
--
X_13 => B2A, -- B2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_244.vhd
0,0 → 1,95
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS244N: Octal buffer/line driver (3-state ops) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_244 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_244 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal OEA, OEB : std_logic;
signal IA, IB : std_logic_vector(3 downto 0);
begin
OEA <= JC(9);
OEB <= JC(8);
IA <= std_logic_vector(BC(4 downto 1));
IB <= std_logic_vector(BC(3 downto 0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
GG: for j in IA'range generate
begin
D(j) <= IA(j) when OEA = '0' else 'Z';
D(j+4) <= IB(j) when OEB = '0' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS244N
port map(
X_1 => OEA, -- OEA\
X_2 => IA(0), -- IA0
X_3 => E(4), -- YB0
X_4 => IA(1), -- IA1
X_5 => E(5), -- YB1
X_6 => IA(2), -- IA2
X_7 => E(6), -- YB2
X_8 => IA(3), -- IA3
X_9 => E(7), -- YB3
X_10 => open, -- GND
X_11 => IB(3), -- IB3
X_12 => E(3), -- YA3
X_13 => IB(2), -- IB2
X_14 => E(2), -- YA2
X_15 => IB(1), -- IB1
X_16 => E(1), -- YA1
X_17 => IB(0), -- IB0
X_18 => E(0), -- YA0
X_19 => OEB, -- OEB\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_245.vhd
0,0 → 1,101
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS245N: Octal bus transceiver (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_245 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_245 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(15 downto 0); -- Expected & actual results
signal A2B, ENB : std_logic;
signal IA : std_logic_vector(7 downto 0);
begin
IA <= std_logic_vector(JC);
A2B <= BC(0);
ENB <= BC(1);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-- Special version for bidirectional circuits
-----------------------------------------------------------------------
GG: process(all) is
begin
for j in IA'range loop
D(j) <= IA(j) when A2B = '0' else 'Z';
D(j+8) <= IA(j) when A2B = '1' else 'Z';
E(j) <= IA(j) when A2B = '0' else 'Z';
E(j+8) <= IA(j) when A2B = '1' else 'Z';
end loop;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS245N
port map(
X_1 => A2B, -- A2B
X_2 => E(0), -- A0
X_3 => E(1), -- A1
X_4 => E(2), -- A2
X_5 => E(3), -- A3
X_6 => E(4), -- A4
X_7 => E(5), -- A5
X_8 => E(6), -- A6
X_9 => E(7), -- A7
X_10 => open, -- GND
X_11 => E(15), -- B7
X_12 => E(14), -- B6
X_13 => E(13), -- B5
X_14 => E(12), -- B4
X_15 => E(11), -- B3
X_16 => E(10), -- B2
X_17 => E(9), -- B1
X_18 => E(8), -- B0
X_19 => ENB, -- E\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_251.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS251N: 8-input multiplexer (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_251 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 75 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_251 is
signal J, B : unsigned(11 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal A : unsigned(2 downto 0);
signal chn : natural range 7 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(3 downto 1);
chn <= TTL_to_integer(A);
D(1) <= not B(4+chn) when B(0) = '0' else 'Z';
D(0) <= notz(D(1));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS251N
port map(
X_1 => B(7), -- I3
X_2 => B(6), -- I2
X_3 => B(5), -- I1
X_4 => B(4), -- I0
X_5 => E(0), -- Z
X_6 => E(1), -- Z\
X_7 => B(0), -- E\
X_8 => open, -- GND
X_9 => B(3), -- S2
X_10 => B(2), -- S1
X_11 => B(1), -- S0
X_12 => B(11), -- I7
X_13 => B(10), -- I6
X_14 => B(9), -- I5
X_15 => B(8), -- I4
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_253.vhd
0,0 → 1,85
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS253N: Dual 4-input mux. (common selects) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_253 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_253 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal A : unsigned(1 downto 0);
signal chn : natural range 3 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(3 downto 2);
chn <= TTL_to_integer(A);
D(0) <= B(7-chn) when B(0) = '0' else 'Z';
D(1) <= B(chn+4) when B(1) = '0' else 'Z';
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS253N
port map(
X_1 => B(0), -- EA\
X_2 => B(3), -- S1
X_3 => B(4), -- I3A
X_4 => B(5), -- I2A
X_5 => B(6), -- I1A
X_6 => B(7), -- I0A
X_7 => E(0), -- ZA
X_8 => open, -- GND
X_9 => E(1), -- ZB
X_10 => B(4), -- I0B
X_11 => B(5), -- I1B
X_12 => B(6), -- I2B
X_13 => B(7), -- I3B
X_14 => B(2), -- S0
X_15 => B(1), -- EB\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_256.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74256N: Dual 4-bit addressable latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_256 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_256 is
signal RS : std_logic;
signal CLK : std_logic;
signal EN : std_logic;
signal JC, BC : unsigned(4 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
process(all) is
begin
if falling_edge(BC(0)) then
EN <= '0' after 20 ns, '1' after 100 ns;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable N : natural;
begin
N := to_integer(unsigned(BC(2 downto 1)));
if RS = '0' then
D <= (others => '0');
elsif EN = '0' then
D(N) <= BC(3);
D(4+N) <= BC(4);
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS256N
port map(
X_1 => BC(1), -- A0
X_2 => BC(2), -- A1
X_3 => BC(3), -- DA
X_4 => E(0), -- O0A
X_5 => E(1), -- O1A
X_6 => E(2), -- O2A
X_7 => E(3), -- O3A
X_8 => open, -- GND
X_9 => E(4), -- O0B
X_10 => E(5), -- O1B
X_11 => E(6), -- O2B
X_12 => E(7), -- O3B
X_13 => BC(4), -- DB
X_14 => EN, -- E\
X_15 => RS, -- CL\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_257.vhd
0,0 → 1,88
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS257N: Quad 2-input mux. (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_257 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_257 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
begin
if B(0) = '1' then
D <= (others => 'Z');
elsif B(1) = '0' then
D <= (B(8), B(6), B(4), B(2));
else
D <= (B(9), B(7), B(5), B(3));
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS257N
port map(
X_1 => B(1), -- S
X_2 => B(2), -- I0A
X_3 => B(3), -- I1A
X_4 => E(0), -- ZA
X_5 => B(4), -- I0B
X_6 => B(5), -- I1B
X_7 => E(1), -- ZB
X_8 => open, -- GND
X_9 => E(3), -- ZD
X_10 => B(9), -- I1D
X_11 => B(8), -- I0D
X_12 => E(2), -- ZC
X_13 => B(7), -- I1C
X_14 => B(6), -- I0C
X_15 => B(0), -- E\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_258.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS258N: Quad 2-input mux (3-state inverting) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_258 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_258 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B) is
variable Z : std_logic_vector(3 downto 0);
begin
if B(0) = '1' then
Z := (others => 'Z');
elsif B(1) = '0' then
Z := (B(8), B(6), B(4), B(2));
else
Z := (B(9), B(7), B(5), B(3));
end if;
for i in Z'range loop
if Z(i) = 'Z' then
D(i) <= 'Z';
else
D(i) <= not Z(i);
end if;
end loop;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS258N
port map(
X_1 => B(1), -- S
X_2 => B(2), -- I0A
X_3 => B(3), -- I1A
X_4 => E(0), -- ZA
X_5 => B(4), -- I0B
X_6 => B(5), -- I1B
X_7 => E(1), -- ZB
X_8 => open, -- GND
X_9 => E(3), -- ZD
X_10 => B(9), -- I1D
X_11 => B(8), -- I0D
X_12 => E(2), -- ZC
X_13 => B(7), -- I1C
X_14 => B(6), -- I0C
X_15 => B(0), -- E\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_259.vhd
0,0 → 1,97
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74259N: 8-bit addressable latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_259 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_259 is
signal RS : std_logic;
signal CLK : std_logic;
signal EN : std_logic;
signal JC, BC : unsigned(4 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
process(all) is
begin
if falling_edge(BC(0)) then
EN <= '0' after 20 ns, '1' after 100 ns;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable N : natural;
begin
N := to_integer(unsigned(BC(3 downto 1)));
if RS = '0' then
D <= (others => '0');
elsif EN = '0' then
D(N) <= BC(4);
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS259N
port map(
X_1 => BC(1), -- A0
X_2 => BC(2), -- A1
X_3 => BC(3), -- A2
X_4 => E(0), -- Q0
X_5 => E(1), -- Q1
X_6 => E(2), -- Q2
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => E(4), -- Q4
X_10 => E(5), -- Q5
X_11 => E(6), -- Q6
X_12 => E(7), -- Q7
X_13 => BC(4), -- D
X_14 => EN, -- E\
X_15 => RS, -- CL\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_26.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS26N: Quad 2-input NAND buffer (open collector)--
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_26 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_26 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not(J(0) and J(1)) );
D(1) <= TTL_OC( not(J(2) and J(3)) );
D(2) <= TTL_OC( not(J(4) and J(5)) );
D(3) <= TTL_OC( not(J(6) and J(7)) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS26N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_260.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS260N: Dual 5-input NOR gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_260 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_260 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( J(0) or J(1) or J(2) or J(3) or J(4) );
D(1) <= not( J(5) or J(6) or J(7) or J(8) or J(9) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS260N
port map(
X_1 => J(0), -- I1A
X_2 => J(1), -- I2A
X_3 => J(2), -- I3A
X_4 => J(5), -- I1B
X_5 => E(0), -- ZA\
X_6 => E(1), -- ZB\
X_7 => open, -- GND
X_8 => J(6), -- I2B
X_9 => J(7), -- I3B
X_10 => J(8), -- I4B
X_11 => J(9), -- I5B
X_12 => J(3), -- I4A
X_13 => J(4), -- I5A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_266.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS266N: Quad 2-input XNOR gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_266 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_266 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not ( J(0) xor J(1) ) );
D(1) <= TTL_OC( not ( J(2) xor J(3) ) );
D(2) <= TTL_OC( not ( J(4) xor J(5) ) );
D(3) <= TTL_OC( not ( J(6) xor J(7) ) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS266N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_27.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS27N: Triple 3-input NOR gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_27 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_27 is
signal J, B : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( J(0) or J(1) or J(2) );
D(1) <= not( J(3) or J(4) or J(5) );
D(2) <= not( J(6) or J(7) or J(8) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS27N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(3), -- 2A
X_4 => J(4), -- 2B
X_5 => J(5), -- 2C
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(6), -- 3C
X_10 => J(7), -- 3B
X_11 => J(8), -- 3A
X_12 => E(0), -- 1Y\
X_13 => J(2), -- 1C
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_273.vhd
0,0 → 1,92
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS273N: 8-bit D-type register with clear --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_273 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_273 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RS) is
begin
if RS = '0' then
D <= (others => '0');
elsif rising_edge(CLK) then
D <= std_logic_vector(BC);
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS273N
port map(
X_1 => RS, -- MR\
X_2 => E(0), -- Q0
X_3 => BC(0), -- D0
X_4 => BC(1), -- D1
X_5 => E(1), -- Q1
X_6 => E(2), -- Q2
X_7 => BC(2), -- D2
X_8 => BC(3), -- D3
X_9 => E(3), -- Q3
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(4), -- Q4
X_13 => BC(4), -- D4
X_14 => BC(5), -- D5
X_15 => E(5), -- Q5
X_16 => E(6), -- Q6
X_17 => BC(6), -- D6
X_18 => BC(7), -- D7
X_19 => E(7), -- Q7
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_279.vhd
0,0 → 1,112
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS279N: 4-bit S-R latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_279 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := warning
);
end entity;
 
architecture Test of Testbench_279 is
signal J, B : unsigned(11 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal X : std_logic_vector(11 downto 0); -- Shortened R-X-S pulses
signal CLK, RS : std_logic;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
process(CLK, RS) is -- Generate short R-S pulses
variable Y : std_logic_vector(11 downto 0);
begin
if RS = '0' then
X <= "011011011011"; -- General reset
elsif rising_edge(CLK) then
Y := std_logic_vector(J);
Y(9) := Y(9) or not Y(11); -- Reset dominates, all cases
Y(6) := Y(6) or not (Y(7) and Y(8));
Y(3) := Y(3) or not Y(5);
Y(1) := Y(1) or not Y(2);
Y(0) := Y(0) or not Y(2);
X <= Y, (others => '1') after Period / 2;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable R, S : std_logic_vector(3 downto 0);
variable Z : std_logic_vector(1 downto 0);
begin
R := (X(11), X(8) and X(7), X(5), X(2));
S := (X(9), X(6), X(3), X(1) and X(0));
for i in R'range loop
Z := S(i) & R(i);
case Z is
when "11" => null;
when "01" => D(i) <= '1';
when "10" => D(i) <= '0';
when others => D(i) <= 'X';
end case;
end loop;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS279N
port map(
X_1 => X(2), -- 1R\
X_2 => X(1), -- 1S1\
X_3 => X(0), -- 1S2\
X_4 => E(0), -- 1Q
X_5 => X(5), -- 2R\
X_6 => X(3), -- 2S\
X_7 => E(1), -- 2Q
X_8 => open, -- GND
X_9 => E(2), -- 3Q
X_10 => X(6), -- 3S\
X_11 => X(7), -- 3R1\
X_12 => X(8), -- 3R2\
X_13 => E(3), -- 4Q
X_14 => X(9), -- 4S\
X_15 => X(11), -- 4R\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_28.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS28N: Quad 2-input NOR buffer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_28 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_28 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not (J(0) or J(1));
D(1) <= not (J(2) or J(3));
D(2) <= not (J(4) or J(5));
D(3) <= not (J(6) or J(7));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS28N
port map(
X_1 => E(0), -- 1Y\
X_2 => J(0), -- 1A
X_3 => J(1), -- 1B
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => J(6), -- 4B
X_12 => J(7), -- 4A
X_13 => E(3), -- 4Y\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_280.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS280N: 9-bit parity generator/checker --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_280 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_280 is
signal J, B : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= xnor_reduce(std_logic_vector(J));
D(1) <= xor_reduce(std_logic_vector(J));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS280N
port map(
X_1 => J(6), -- I6
X_2 => J(7), -- I7
--
X_4 => J(8), -- I8
X_5 => E(0), -- SE
X_6 => E(1), -- SO
X_7 => open, -- GND
X_8 => J(0), -- I0
X_9 => J(1), -- I1
X_10 => J(2), -- I2
X_11 => J(3), -- I3
X_12 => J(4), -- I4
X_13 => J(5), -- I5
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_283.vhd
0,0 → 1,90
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS283N: 4-bit binary full adder (fast carry) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_283 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_283 is
signal JC, BC : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(JC) is
variable X, Y, Z : natural := 0;
begin
if now > 1 ns then -- Meaningless to run at T=0
X := TTL_to_integer(JC(7 downto 4));
Y := TTL_to_integer(JC(3 downto 0));
Z := TTL_to_integer(JC(8 downto 8));
Z := Z + X + Y;
end if;
D <= std_logic_vector(to_unsigned(Z, D'length));
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS283N
port map(
X_1 => E(1), -- S1
X_2 => JC(5), -- B1
X_3 => JC(1), -- A1
X_4 => E(0), -- S0
X_5 => JC(0), -- A0
X_6 => JC(4), -- B0
X_7 => JC(8), -- C0
X_8 => open, -- GND
X_9 => E(4), -- C4
X_10 => E(3), -- S3
X_11 => JC(7), -- B3
X_12 => JC(3), -- A3
X_13 => E(2), -- S2
X_14 => JC(2), -- A2
X_15 => JC(6), -- B2
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_289.vhd
0,0 → 1,153
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS289N: 64-bit RAM (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_289 is -- Top-level bench
generic(
OC : boolean := true;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_289 is
signal J, B : unsigned(5 downto 0); -- Unused
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TTLword := (others => '0');
signal DI, Q, QQ : TTLquad;
signal CE, WE : std_logic;
 
signal W : std_logic;
signal Phase : natural;
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1;
when 1 => WR <= W; Phase <= 2;
when 2 => WR <= '1'; Phase <= 3;
when others => CS <= '1'; WR <= '1'; Phase <= 0;
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(3 downto 0);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := "0110";
elsif rising_edge(CLK) and Phase = 3 then
if AD = "1111" then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
for i in TD'range loop
DI(i+1) <= TD(i);
end loop;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CE <= WR and not CS;
WE <= not(WR or CS);
process(CE, WE, AD, DI) is
variable mem : TTLmem; -- Testbench memory
variable adr : TTLaddr;
variable QI : TTLquad;
begin
adr := TTL_to_integer(AD);
if WE'event and WE = '1' then
mem(adr) := not DI; -- Data is output inverted
end if;
if CE = '1' then
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then
for i in Q'range loop
Q(i) <= TTL_OC(QI(i));
end loop;
else
Q <= QI;
end if;
end process;
D <= Q;
E <= QQ;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS89N
port map(
X_1 => AD(0), -- A0
X_2 => CS, -- CS\
X_3 => WR, -- WE\
X_4 => DI(1), -- D1
X_5 => QQ(1), -- Q1\
X_6 => DI(2), -- D2
X_7 => QQ(2), -- Q2\
X_8 => open, -- GND
X_9 => QQ(3), -- Q3\
X_10 => DI(3), -- D3
X_11 => QQ(4), -- Q4\
X_12 => DI(4), -- D4
X_13 => AD(3), -- A3
X_14 => AD(2), -- A2
X_15 => AD(1), -- A1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_290.vhd
0,0 → 1,106
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS290N: BCD decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_290 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_290 is
signal RS, C0, NRS : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '1' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '1' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
case TTL_to_integer(Q31) is
when 4 to 7 => Q31 := Q31 - 4;
when others => Q31 := Q31 + 1;
end case;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS290N
port map(
X_1 => '0', -- MS1
--
X_3 => '0', -- MS2
X_4 => E(2), -- Q2
X_5 => E(1), -- Q1
--
X_7 => open, -- GND
X_8 => E(3), -- Q3
X_9 => C0, -- Q0
X_10 => B(0), -- CP0\
X_11 => C0, -- CP1\
X_12 => RS, -- MR1
X_13 => RS, -- MR2
X_14 => open -- Vcc
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_293.vhd
0,0 → 1,103
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS293N: 4-bit binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_293 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_293 is
signal RS, C0, NRS : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '1' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '1' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
Q31 := Q31 + 1;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS293N
port map(
--
--
--
X_4 => E(2), -- Q2
X_5 => E(1), -- Q1
--
X_7 => open, -- GND
X_8 => E(3), -- Q3
X_9 => C0, -- Q0
X_10 => B(0), -- CP0\
X_11 => C0, -- CP1\
X_12 => RS, -- MR1
X_13 => RS, -- MR2
X_14 => open -- Vcc
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_295.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS295AN: 4-bit shift register (3-state outputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_295 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_295 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal P, Q : std_logic_vector(3 downto 0);
signal CP, OE, PE, DS : std_logic := '1';
begin
P <= std_logic_vector(JC(3 downto 0));
DS <= JC(1);
CP <= CLK;
PE <= '1' when ((BC = "1000") or (RS = '0')) else '0';
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP) is
begin
if falling_edge(CP) then
if PE = '0' then
Q <= Q(2 downto 0) & DS;
else
Q <= P;
end if;
end if;
end process;
D <= Q when OE = '1' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS295AN
port map(
X_1 => DS, -- DS
X_2 => P(0), -- P0
X_3 => P(1), -- P1
X_4 => P(2), -- P2
X_5 => P(3), -- P3
X_6 => PE, -- PE
X_7 => open, -- GND
X_8 => OE, -- OE
X_9 => CP, -- CP\
X_10 => E(3), -- Q3
X_11 => E(2), -- Q2
X_12 => E(1), -- Q1
X_13 => E(0), -- Q0
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_298.vhd
0,0 → 1,92
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS298N: Quad 2-input mux. with register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_298 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '0';
Period : time := 40 ns;
Finish : time := 50 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_298 is
signal J, B, Y : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal CP, S, RS, CLK : std_logic;
 
begin
CP <= B(1) or (CLK and not RS);
Y <= B after 10 ns;
S <= Y(0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP) is
begin
if falling_edge(CP) then
if S = '0' then
D <= (Y(8), Y(6), Y(4), Y(2));
else
D <= (Y(9), Y(7), Y(5), Y(3));
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS298N
port map(
X_1 => Y(5), -- I1B
X_2 => Y(3), -- I1A
X_3 => Y(2), -- I0A
X_4 => Y(4), -- I0B
X_5 => Y(7), -- I1C
X_6 => Y(9), -- I1D
X_7 => Y(8), -- I0D
X_8 => open, -- GND
X_9 => Y(6), -- I0C
X_10 => S, -- S
X_11 => CP, -- CP\
X_12 => E(3), -- QD
X_13 => E(2), -- QC
X_14 => E(1), -- QB
X_15 => E(0), -- QA
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_299.vhd
0,0 → 1,112
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS299N: 8 bit universal shift/storage register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_299 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 40 ns;
Finish : time := 50 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_299 is
signal J, B : unsigned(13 downto 0); -- Test stimuli
signal D, E : std_logic_vector(9 downto 0); -- Expected & actual results
signal RS, CLK : std_logic;
signal OE : std_logic;
signal DI, R, DT : std_logic_vector(0 to 7);
alias S0 is J(8);
alias S1 is J(9);
alias OE1 is J(10);
alias OE2 is J(11);
alias DS0 is J(12);
alias DS7 is J(13);
 
begin
OE <= not((S1 and S0) or OE1 or OE2);
DI <= TTL_REV(J(7 downto 0)) when OE = '0' else (others => 'Z');
E <= "ZZ" & TTL_REV(DI);
DT <= TTL_REV(J(7 downto 0)) when OE = '0' else R;
D <= R(7) & R(0) & TTL_REV(DT);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(RS, CLK) is
variable S : unsigned(1 downto 0);
begin
if RS = '0' then
R <= (others => '0');
elsif rising_edge(CLK) then
S := (S1, S0);
case S is
when "01" => R <= DS0 & R(0 to 6); -- Shift right
when "10" => R <= R(1 to 7) & DS7; -- Shift left
when "11" => R <= DT; -- Parallel load
when others => null; -- "00" hold
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS299N
port map(
X_1 => S0, -- S0
X_2 => OE1, -- OE1\
X_3 => OE2, -- OE2\
X_4 => DI(6), -- IO6
X_5 => DI(4), -- IO4
X_6 => DI(2), -- IO2
X_7 => DI(0), -- IO0
X_8 => E(8), -- Q0
X_9 => RS, -- MR\
X_10 => open, -- GND
X_11 => DS0, -- DS0
X_12 => CLK, -- CP
X_13 => DI(1), -- IO1
X_14 => DI(3), -- IO3
X_15 => DI(5), -- IO5
X_16 => DI(7), -- IO7
X_17 => E(9), -- Q7
X_18 => DS7, -- DS7
X_19 => S1, -- S1
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_30.vhd
0,0 → 1,76
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS30N: 8-input NAND gate (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_30 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_30 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= nand_reduce(std_logic_vector(J(7 downto 0)));
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS30N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => J(2), -- 1C
X_4 => J(3), -- 1D
X_5 => J(4), -- 1E
X_6 => J(5), -- 1F
X_7 => open, -- GND
X_8 => E(0), -- 1Y\
--
--
X_11 => J(6), -- 1G
X_12 => J(7), -- 1H
--
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_32.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS32N: Quad 2-input OR gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_32 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_32 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= (J(0) or J(1));
D(1) <= (J(2) or J(3));
D(2) <= (J(4) or J(5));
D(3) <= (J(6) or J(7));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS32N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_322.vhd
0,0 → 1,116
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS322N: 8 bit ser/par register + sign extend --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_322 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 40 ns;
Finish : time := 50 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_322 is
signal J, B : unsigned(14 downto 0); -- Test stimuli
signal D, E : std_logic_vector(8 downto 0); -- Expected & actual results
signal RS, CLK : std_logic;
signal OEI, DIN : std_logic;
signal DI, R, DT : std_logic_vector(7 downto 0);
alias RE is J(8);
alias SP is J(9);
alias D0 is J(10);
alias D1 is J(11);
alias OE is J(12);
alias SE is J(13);
alias S is J(14);
 
begin
OEI <= (SP or RE) and not(OE);
DIN <= D0 when S = '0' else D1;
DI <= std_logic_vector(J(7 downto 0)) when OE = '1' else (others => 'Z');
E <= "Z" & DI;
DT <= std_logic_vector(J(7 downto 0)) when OE = '1' else
R when OEI = '1' else
(others => 'Z');
D <= R(0) & DT;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(RS, CLK) is
variable SEL : unsigned(2 downto 0);
begin
if RS = '0' then
R <= (others => '0');
elsif rising_edge(CLK) then
SEL := RE & SP & SE;
case SEL is
when "011" => R <= DIN & R(7 downto 1); -- Shift right
when "010" => R <= R(7) & R(7 downto 1); -- Shift left
when "00-" => R <= DT; -- Parallel load
when others => null; -- Hold
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS322N
port map(
X_1 => RE, -- RE\
X_2 => SP, -- S/P\
X_3 => D0, -- D0
X_4 => DI(7), -- IO7
X_5 => DI(5), -- IO5
X_6 => DI(3), -- IO3
X_7 => DI(1), -- IO1
X_8 => OE, -- OE\
X_9 => RS, -- MR\
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(8), -- Q0
X_13 => DI(0), -- IO0
X_14 => DI(2), -- IO2
X_15 => DI(4), -- IO4
X_16 => DI(6), -- IO6
X_17 => D1, -- D1
X_18 => SE, -- SE\
X_19 => S, -- S
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_323.vhd
0,0 → 1,111
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS323N: 8 bit universal shift/storage register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_323 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 40 ns;
Finish : time := 50 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_323 is
signal J, B : unsigned(13 downto 0); -- Test stimuli
signal D, E : std_logic_vector(9 downto 0); -- Expected & actual results
signal RS, CLK : std_logic;
signal OE : std_logic;
signal DI, R, DT : std_logic_vector(0 to 7);
alias S0 is J(8);
alias S1 is J(9);
alias OE1 is J(10);
alias OE2 is J(11);
alias DS0 is J(12);
alias DS7 is J(13);
 
begin
OE <= not((S1 and S0) or OE1 or OE2);
DI <= TTL_REV(J(7 downto 0)) when OE = '0' else (others => 'Z');
E <= "ZZ" & TTL_REV(DI);
DT <= TTL_REV(J(7 downto 0)) when OE = '0' else R;
D <= R(7) & R(0) & TTL_REV(DT);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(RS, CLK) is
variable S : unsigned(2 downto 0);
begin
if rising_edge(CLK) then
S := (RS, S1, S0);
case S is
when "0--" => R <= (others => '0'); -- Sync. reset
when "101" => R <= DS0 & R(0 to 6); -- Shift right
when "110" => R <= R(1 to 7) & DS7; -- Shift left
when "111" => R <= DT; -- Parallel load
when others => null; -- "00" hold
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS323N
port map(
X_1 => S0, -- S0
X_2 => OE1, -- OE1\
X_3 => OE2, -- OE2\
X_4 => DI(6), -- IO6
X_5 => DI(4), -- IO4
X_6 => DI(2), -- IO2
X_7 => DI(0), -- IO0
X_8 => E(8), -- Q0
X_9 => RS, -- SR\
X_10 => open, -- GND
X_11 => DS0, -- DS0
X_12 => CLK, -- CP
X_13 => DI(1), -- IO1
X_14 => DI(3), -- IO3
X_15 => DI(5), -- IO5
X_16 => DI(7), -- IO7
X_17 => E(9), -- Q7
X_18 => DS7, -- DS7
X_19 => S1, -- S1
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_33.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS33N: Quad 2-input NOR buffer (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_33 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_33 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not (J(0) or J(1)) );
D(1) <= TTL_OC( not (J(2) or J(3)) );
D(2) <= TTL_OC( not (J(4) or J(5)) );
D(3) <= TTL_OC( not (J(6) or J(7)) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS33N
port map(
X_1 => E(0), -- 1Y\
X_2 => J(0), -- 1A
X_3 => J(1), -- 1B
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => J(6), -- 4B
X_12 => J(7), -- 4A
X_13 => E(3), -- 4Y\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_352.vhd
0,0 → 1,85
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS352N: Dual 4-input mux. (common selects) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_352 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_352 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal A : unsigned(1 downto 0);
signal chn : natural range 3 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(3 downto 2);
chn <= TTL_to_integer(A);
D(0) <= not((not B(0)) and B(7-chn));
D(1) <= not((not B(1)) and B(chn+4));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS352N
port map(
X_1 => B(0), -- EA\
X_2 => B(3), -- S1
X_3 => B(4), -- I3A
X_4 => B(5), -- I2A
X_5 => B(6), -- I1A
X_6 => B(7), -- I0A
X_7 => E(0), -- ZA\
X_8 => open, -- GND
X_9 => E(1), -- ZB\
X_10 => B(4), -- I0B
X_11 => B(5), -- I1B
X_12 => B(6), -- I2B
X_13 => B(7), -- I3B
X_14 => B(2), -- S0
X_15 => B(1), -- EB\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_353.vhd
0,0 → 1,85
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS353N: Dual 4-input mux. (common selects) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_353 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_353 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
signal A : unsigned(1 downto 0);
signal chn : natural range 3 downto 0;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
A <= B(3 downto 2);
chn <= TTL_to_integer(A);
D(0) <= not(B(7-chn)) when B(0) = '0' else 'Z';
D(1) <= not(B(chn+4)) when B(1) = '0' else 'Z';
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS353N
port map(
X_1 => B(0), -- EA\
X_2 => B(3), -- S1
X_3 => B(4), -- I3A
X_4 => B(5), -- I2A
X_5 => B(6), -- I1A
X_6 => B(7), -- I0A
X_7 => E(0), -- ZA\
X_8 => open, -- GND
X_9 => E(1), -- ZB\
X_10 => B(4), -- I0B
X_11 => B(5), -- I1B
X_12 => B(6), -- I2B
X_13 => B(7), -- I3B
X_14 => B(2), -- S0
X_15 => B(1), -- EB\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_365.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS365N: Hex 3-state buffer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_365 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_365 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal EN : std_logic;
begin
EN <= not(J(1) or J(0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D <= std_logic_vector(B) when EN = '1' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS365AN
port map(
X_1 => J(0), -- E1\
X_2 => B(0), -- A1
X_3 => E(0), -- Y1
X_4 => B(1), -- A2
X_5 => E(1), -- Y2
X_6 => B(2), -- A3
X_7 => E(2), -- Y3
X_8 => open, -- GND
X_9 => E(3), -- Y4
X_10 => B(3), -- A4
X_11 => E(4), -- Y5
X_12 => B(4), -- A5
X_13 => E(5), -- Y6
X_14 => B(5), -- A6
X_15 => J(1), -- E2\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_366.vhd
0,0 → 1,81
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS366N: Hex 3-state buffer (inverting) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_366 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_366 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal EN : std_logic;
begin
EN <= not(J(1) or J(0));
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D <= not std_logic_vector(B) when EN = '1' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS366AN
port map(
X_1 => J(0), -- E1\
X_2 => B(0), -- A1
X_3 => E(0), -- Y1\
X_4 => B(1), -- A2
X_5 => E(1), -- Y2\
X_6 => B(2), -- A3
X_7 => E(2), -- Y3\
X_8 => open, -- GND
X_9 => E(3), -- Y4\
X_10 => B(3), -- A4
X_11 => E(4), -- Y5\
X_12 => B(4), -- A5
X_13 => E(5), -- Y6\
X_14 => B(5), -- A6
X_15 => J(1), -- E2\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_367.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS367N: 2- & 4-bit 3-state buffer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_367 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_367 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in B'range generate
signal EN : std_logic;
begin
EN <= J(1) when i > 3 else J(0);
D(i) <= B(i) when EN = '0' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS367AN
port map(
X_1 => J(0), -- E1\
X_2 => B(0), -- A1
X_3 => E(0), -- Y1
X_4 => B(1), -- A2
X_5 => E(1), -- Y2
X_6 => B(2), -- A3
X_7 => E(2), -- Y3
X_8 => open, -- GND
X_9 => E(3), -- Y4
X_10 => B(3), -- A4
X_11 => E(4), -- Y5
X_12 => B(4), -- A5
X_13 => E(5), -- Y6
X_14 => B(5), -- A6
X_15 => J(1), -- E2\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_368.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS367N: 2- & 4-bit 3-state buffer (inverting) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_368 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 200 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_368 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in B'range generate
signal EN : std_logic;
begin
EN <= J(1) when i > 3 else J(0);
D(i) <= not B(i) when EN = '0' else 'Z';
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS368AN
port map(
X_1 => J(0), -- E1\
X_2 => B(0), -- A1
X_3 => E(0), -- Y1\
X_4 => B(1), -- A2
X_5 => E(1), -- Y2\
X_6 => B(2), -- A3
X_7 => E(2), -- Y3\
X_8 => open, -- GND
X_9 => E(3), -- Y4\
X_10 => B(3), -- A4
X_11 => E(4), -- Y5\
X_12 => B(4), -- A5
X_13 => E(5), -- Y6\
X_14 => B(5), -- A6
X_15 => J(1), -- E2\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_37.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS37N: Quad 2-input NAND buffer --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_37 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_37 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not (J(0) and J(1));
D(1) <= not (J(2) and J(3));
D(2) <= not (J(4) and J(5));
D(3) <= not (J(6) and J(7));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS37N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_373.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS373N: 8-bit transparent latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_373 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_373 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
alias OE is J(0);
alias LE is J(1);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
begin
if LE = '1' then
R <= std_logic_vector(B);
end if;
end process;
D <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS373N
port map(
X_1 => OE, -- OE\
X_2 => E(0), -- Q0
X_3 => B(0), -- D0
X_4 => B(1), -- D1
X_5 => E(1), -- Q1
X_6 => E(2), -- Q2
X_7 => B(2), -- D2
X_8 => B(3), -- D3
X_9 => E(3), -- Q3
X_10 => open, -- GND
X_11 => LE, -- LE
X_12 => E(4), -- Q4
X_13 => B(4), -- D4
X_14 => B(5), -- D5
X_15 => E(5), -- Q5
X_16 => E(6), -- Q6
X_17 => B(6), -- D6
X_18 => B(7), -- D7
X_19 => E(7), -- Q7
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_374.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS374N: 8-bit D flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_374 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_374 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
signal CLK : std_logic;
alias OE is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
R <= std_logic_vector(B);
end if;
end process;
D <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS374N
port map(
X_1 => OE, -- OE\
X_2 => E(0), -- Q0
X_3 => B(0), -- D0
X_4 => B(1), -- D1
X_5 => E(1), -- Q1
X_6 => E(2), -- Q2
X_7 => B(2), -- D2
X_8 => B(3), -- D3
X_9 => E(3), -- Q3
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(4), -- Q4
X_13 => B(4), -- D4
X_14 => B(5), -- D5
X_15 => E(5), -- Q5
X_16 => E(6), -- Q6
X_17 => B(6), -- D6
X_18 => B(7), -- D7
X_19 => E(7), -- Q7
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_375.vhd
0,0 → 1,118
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS375N: 4-bit bistable latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_375 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_375 is
signal CLK : std_logic;
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal S : std_logic_vector(3 downto 0);
signal E12, E34 : std_logic;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if falling_edge(CLK) then
E12 <= J(4), '0' after 45 ns;
E34 <= J(5), '0' after 45 ns;
end if;
end process;
S <= (E34, E34, E12, E12);
G1: for i in 3 downto 0 generate
begin
process(S, J) is
begin
if S(i) = '1' then
D(i) <= J(i);
D(i+4) <= not J(i);
end if;
end process;
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS375N
-- port map(
-- X_1 => E(4), -- Q1\
-- X_2 => J(0), -- D1
-- X_3 => J(1), -- D2
-- X_4 => E34, -- E34
-- X_5 => open, -- Vcc
-- X_6 => J(2), -- D3
-- X_7 => J(3), -- D4
-- X_8 => E(7), -- Q4\
-- X_9 => E(3), -- Q4
-- X_10 => E(6), -- Q3\
-- X_11 => E(2), -- Q3
-- X_12 => open, -- GND
-- X_13 => E12, -- E12
-- X_14 => E(5), -- Q2\
-- X_15 => E(1), -- Q2
-- X_16 => E(0) -- Q1
-- );
port map(
X_1 => J(0), -- D1
X_2 => E(4), -- Q1\
X_3 => E(0), -- Q1
X_4 => E12, -- E12
X_5 => E(1), -- Q2
X_6 => E(5), -- Q2\
X_7 => J(1), -- D2
X_8 => open, -- GND
X_9 => J(2), -- D3
X_10 => E(6), -- Q3\
X_11 => E(2), -- Q3
X_12 => E34, -- E34
X_13 => E(3), -- Q4
X_14 => E(7), -- Q4\
X_15 => J(3), -- D4
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_377.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS377N: 8-bit D flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_377 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_377 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
signal CLK : std_logic;
alias EN is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
if EN = '0' then
R <= std_logic_vector(B);
end if;
end if;
end process;
D <= R;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS377N
port map(
X_1 => EN, -- EN\
X_2 => E(0), -- Q0
X_3 => B(0), -- D0
X_4 => B(1), -- D1
X_5 => E(1), -- Q1
X_6 => E(2), -- Q2
X_7 => B(2), -- D2
X_8 => B(3), -- D3
X_9 => E(3), -- Q3
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(4), -- Q4
X_13 => B(4), -- D4
X_14 => B(5), -- D5
X_15 => E(5), -- Q5
X_16 => E(6), -- Q6
X_17 => B(6), -- D6
X_18 => B(7), -- D7
X_19 => E(7), -- Q7
X_20 => open -- Vcc
);
 
end architecture Test;
/trunk/Testbench/Testbench_378.vhd
0,0 → 1,92
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS378N: 8-bit D flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_378 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_378 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(5 downto 0); -- Expected & actual results
signal R : std_logic_vector(5 downto 0); -- Register
signal CLK : std_logic;
alias EN is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
if EN = '0' then
R <= std_logic_vector(B);
end if;
end if;
end process;
D <= R;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS378N
port map(
X_1 => EN, -- E\
X_2 => E(0), -- Q0
X_3 => B(0), -- D0
X_4 => B(1), -- D1
X_5 => E(1), -- Q1
X_6 => B(2), -- D2
X_7 => E(2), -- Q2
X_8 => open, -- GND
X_9 => CLK, -- CP
X_10 => E(3), -- Q3
X_11 => B(3), -- D3
X_12 => E(4), -- Q4
X_13 => B(4), -- D4
X_14 => B(5), -- D5
X_15 => E(5), -- Q5
X_16 => open -- Vcc
);
 
end architecture Test;
/trunk/Testbench/Testbench_379.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS379N: 4-bit D flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_379 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_379 is
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R, N : std_logic_vector(3 downto 0); -- Register
signal CLK : std_logic;
alias EN is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
if EN = '0' then
R <= std_logic_vector(B);
end if;
end if;
end process;
N <= not R;
D <= N & R;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS379N
port map(
X_1 => EN, -- E\
X_2 => E(0), -- Q0
X_3 => E(4), -- Q0\
X_4 => B(0), -- D0
X_5 => B(1), -- D1
X_6 => E(5), -- Q1\
X_7 => E(1), -- Q1
X_8 => open, -- GND
X_9 => CLK, -- CP
X_10 => E(2), -- Q2
X_11 => E(6), -- Q2\
X_12 => B(2), -- D2
X_13 => B(3), -- D3
X_14 => E(7), -- Q3\
X_15 => E(3), -- Q3
X_16 => open -- Vcc
);
 
end architecture Test;
/trunk/Testbench/Testbench_38.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS38N: Quad 2-input NAND buffer (open collector)--
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_38 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_38 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not (J(0) and J(1)) );
D(1) <= TTL_OC( not (J(2) and J(3)) );
D(2) <= TTL_OC( not (J(4) and J(5)) );
D(3) <= TTL_OC( not (J(6) and J(7)) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS38N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_386.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS386N: Quad 2-input XOR gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_386 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_386 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= J(0) xor J(1);
D(1) <= J(2) xor J(3);
D(2) <= J(4) xor J(5);
D(3) <= J(6) xor J(7);
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS386N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_39.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS39N: Quad 2-input NAND buffer (open collector)--
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_39 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_39 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not (J(0) and J(1)) );
D(1) <= TTL_OC( not (J(2) and J(3)) );
D(2) <= TTL_OC( not (J(4) and J(5)) );
D(3) <= TTL_OC( not (J(6) and J(7)) );
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS39N
port map(
X_1 => E(0), -- 1Y\
X_2 => J(0), -- 1A
X_3 => J(1), -- 1B
X_4 => E(1), -- 2Y\
X_5 => J(2), -- 2A
X_6 => J(3), -- 2B
X_7 => open, -- GND
X_8 => J(4), -- 3B
X_9 => J(5), -- 3A
X_10 => E(2), -- 3Y\
X_11 => J(6), -- 4B
X_12 => J(7), -- 4A
X_13 => E(3), -- 4Y\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_390.vhd
0,0 → 1,112
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS390N: Dual decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_390 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_390 is
signal RS, NRS, C0, C1 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CA: process(B, RS) is
variable NA : natural;
begin
if RS = '1' then
NA := 0;
elsif falling_edge(B(0)) then
case NA is
when 9 | 11 | 13 | 15 => NA := NA - 9;
when others => NA := NA + 1;
end case;
end if;
D(3 downto 0) <= std_logic_vector(to_unsigned(NA, 4));
end process;
CB: process(B, RS) is
variable NB : natural;
begin
if RS = '1' then
NB := 0;
elsif falling_edge(B(1)) then
case NB is
when 9 | 11 | 13 | 15 => NB := NB - 9;
when others => NB := NB + 1;
end case;
end if;
D(7 downto 4) <= std_logic_vector(to_unsigned(NB, 4));
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS390N
port map(
X_1 => B(0), -- CPA0\
X_2 => RS, -- MRA
X_3 => C0, -- Q0A
X_4 => C0, -- CPA1\
X_5 => E(1), -- Q1A
X_6 => E(2), -- Q2A
X_7 => E(3), -- Q3A
X_8 => open, -- GND
X_9 => E(7), -- Q3B
X_10 => E(6), -- Q2B
X_11 => E(5), -- Q1B
X_12 => C1, -- CPB1\
X_13 => C1, -- Q0B
X_14 => RS, -- MRB
X_15 => B(1), -- CPB0\
X_16 => open -- Vcc
);
E(0) <= C0;
E(4) <= C1;
end architecture Test;
/trunk/Testbench/Testbench_393.vhd
0,0 → 1,108
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS393N: Dual 4-bit binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_393 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_393 is
signal RS, NRS : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CA: process(B, RS) is
variable NA : natural;
begin
if RS = '1' then
NA := 0;
elsif falling_edge(B(0)) then
case NA is
when 15 => NA := 0;
when others => NA := NA + 1;
end case;
end if;
D(3 downto 0) <= std_logic_vector(to_unsigned(NA, 4));
end process;
CB: process(B, RS) is
variable NB : natural;
begin
if RS = '1' then
NB := 0;
elsif falling_edge(B(1)) then
case NB is
when 15 => NB := 0;
when others => NB := NB + 1;
end case;
end if;
D(7 downto 4) <= std_logic_vector(to_unsigned(NB, 4));
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS393N
port map(
X_1 => B(0), -- CPA\
X_2 => RS, -- MRA
X_3 => E(0), -- Q0A
X_4 => E(1), -- Q1A
X_5 => E(2), -- Q2A
X_6 => E(3), -- Q3A
X_7 => open, -- GND
X_8 => E(7), -- Q3B
X_9 => E(6), -- Q2B
X_10 => E(5), -- Q1B
X_11 => E(4), -- Q0B
X_12 => RS, -- MRB
X_13 => B(1), -- CPB\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_395.vhd
0,0 → 1,100
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS395N: 4-bit shift/load register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_395 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 75 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_395 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal R : std_logic_vector(3 downto 0);
alias S is JC(0);
alias OE is JC(1);
alias DS is JC(2);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(RS, CLK) is
begin
if RS = '0' then
R <= (others => '0');
elsif falling_edge(CLK) then
if S = '0' then
R <= R(2 downto 0) & DS;
else
R <= std_logic_vector(BC);
end if;
end if;
end process;
D(4) <= R(3);
D(3 downto 0) <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS395N
port map(
X_1 => RS, -- MR\
X_2 => DS, -- DS
X_3 => BC(0), -- P0
X_4 => BC(1), -- P1
X_5 => BC(2), -- P2
X_6 => BC(3), -- P3
X_7 => S, -- S
X_8 => open, -- GND
X_9 => OE, -- OE\
X_10 => CLK, -- CP\
X_11 => E(4), -- Q3
X_12 => E(3), -- O3
X_13 => E(2), -- O2
X_14 => E(1), -- O1
X_15 => E(0), -- O0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_40.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS40N: Dual 4-input NAND buffer (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_40 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_40 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( J(0) and J(1) and J(2) and J(3) );
D(1) <= not( J(4) and J(5) and J(6) and J(7) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS40N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
--
X_4 => J(2), -- 1C
X_5 => J(3), -- 1D
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2D
X_10 => J(5), -- 2C
--
X_12 => J(6), -- 2B
X_13 => J(7), -- 2A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_42.vhd
0,0 → 1,87
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS42N: 1-of-10 decoder --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_42 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_42 is
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(9 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(J) is
variable N : natural;
begin
D <= (others => '1'); -- Default
N := TTL_to_integer(J(3 downto 0));
if N < 10 then
D(N) <= '0';
end if;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS42N
port map(
X_1 => E(0), -- Q0\
X_2 => E(1), -- Q1\
X_3 => E(2), -- Q2\
X_4 => E(3), -- Q3\
X_5 => E(4), -- Q4\
X_6 => E(5), -- Q5\
X_7 => E(6), -- Q6\
X_8 => open, -- GND
X_9 => E(7), -- Q7\
X_10 => E(8), -- Q8\
X_11 => E(9), -- Q9\
X_12 => J(3), -- A3
X_13 => J(2), -- A2
X_14 => J(1), -- A1
X_15 => J(0), -- A0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_45.vhd
0,0 → 1,87
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7445N: 1-of-10 decoder/driver (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_45 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_45 is
signal J, B : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(9 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(J) is
variable N : natural;
begin
D <= (others => 'Z'); -- Default
N := TTL_to_integer(J(3 downto 0));
if N < 10 then
D(N) <= '0';
end if;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7445N
port map(
X_1 => E(0), -- Q0\
X_2 => E(1), -- Q1\
X_3 => E(2), -- Q2\
X_4 => E(3), -- Q3\
X_5 => E(4), -- Q4\
X_6 => E(5), -- Q5\
X_7 => E(6), -- Q6\
X_8 => open, -- GND
X_9 => E(7), -- Q7\
X_10 => E(8), -- Q8\
X_11 => E(9), -- Q9\
X_12 => J(3), -- A3
X_13 => J(2), -- A2
X_14 => J(1), -- A1
X_15 => J(0), -- A0
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_490.vhd
0,0 → 1,110
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS490N: Dual decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_490 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_490 is
signal RS, NRS, C0, C1 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CA: process(B, RS) is
variable NA : natural;
begin
if RS = '1' then
NA := 0;
elsif falling_edge(B(0)) then
case NA is
when 11 | 13 | 15 => NA := NA - 9;
when others => NA := NA + 1;
end case;
end if;
D(3 downto 0) <= std_logic_vector(to_unsigned(NA, 4));
end process;
CB: process(B, RS) is
variable NB : natural;
begin
if RS = '1' then
NB := 0;
elsif falling_edge(B(1)) then
case NB is
when 11 | 13 | 15 => NB := NB - 9;
when others => NB := NB + 1;
end case;
end if;
D(7 downto 4) <= std_logic_vector(to_unsigned(NB, 4));
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS490N
port map(
X_1 => B(0), -- CPA\
X_2 => RS, -- MRA
X_3 => E(0), -- Q0A
X_4 => '0', -- MSA
X_5 => E(1), -- Q1A
X_6 => E(2), -- Q2A
X_7 => E(3), -- Q3A
X_8 => open, -- GND
X_9 => E(7), -- Q3B
X_10 => E(6), -- Q2B
X_11 => E(5), -- Q1B
X_12 => '0', -- MSB
X_13 => E(4), -- Q0B
X_14 => RS, -- MRB
X_15 => B(1), -- CPB\
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_51.vhd
0,0 → 1,78
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS51N: Dual 2-wide, 2/3-input AOI (Pinout B) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_51 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_51 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( (J(0) and J(1)) or (J(2) and J(3)) );
D(1) <= not( (J(4) and J(5) and J(6)) or (J(7) and J(8) and J(9)) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS51N
port map(
X_1 => J(9), -- 2A1
X_2 => J(0), -- 1A1
X_3 => J(1), -- 1A2
X_4 => J(2), -- 1B1
X_5 => J(3), -- 1B2
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
X_8 => E(1), -- 2Y\
X_9 => J(4), -- 2B3
X_10 => J(5), -- 2B2
X_11 => J(6), -- 2B1
X_12 => J(7), -- 2A3
X_13 => J(8), -- 2A2
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_533.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS533N: 8-bit transparent latch (inverting) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_533 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_533 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
alias OE is J(0);
alias LE is J(1);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
begin
if LE = '1' then
R <= not std_logic_vector(B);
end if;
end process;
D <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS533N
port map(
X_1 => OE, -- OE\
X_2 => E(0), -- Q0\
X_3 => B(0), -- D0
X_4 => B(1), -- D1
X_5 => E(1), -- Q1\
X_6 => E(2), -- Q2\
X_7 => B(2), -- D2
X_8 => B(3), -- D3
X_9 => E(3), -- Q3\
X_10 => open, -- GND
X_11 => LE, -- LE
X_12 => E(4), -- Q4\
X_13 => B(4), -- D4
X_14 => B(5), -- D5
X_15 => E(5), -- Q5\
X_16 => E(6), -- Q6\
X_17 => B(6), -- D6
X_18 => B(7), -- D7
X_19 => E(7), -- Q7\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_534.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS534N: 8-bit D flipflop (inverting) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_534 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_534 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
signal CLK : std_logic;
alias OE is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
R <= not std_logic_vector(B);
end if;
end process;
D <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS534N
port map(
X_1 => OE, -- OE\
X_2 => E(0), -- Q0\
X_3 => B(0), -- D0
X_4 => B(1), -- D1
X_5 => E(1), -- Q1\
X_6 => E(2), -- Q2\
X_7 => B(2), -- D2
X_8 => B(3), -- D3
X_9 => E(3), -- Q3\
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(4), -- Q4\
X_13 => B(4), -- D4
X_14 => B(5), -- D5
X_15 => E(5), -- Q5\
X_16 => E(6), -- Q6\
X_17 => B(6), -- D6
X_18 => B(7), -- D7
X_19 => E(7), -- Q7\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_54.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS54N: 4-wide 2-input AOI gate (Pinout C) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_54 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_54 is
signal J, B : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( (J(0) and J(1)) or (J(2) and J(3) and J(4)) or
(J(8) and J(9)) or (J(5) and J(6) and J(7)) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS54N
port map(
X_1 => J(0), -- 1A1
X_2 => J(1), -- 1A2
X_3 => J(2), -- 1B1
X_4 => J(3), -- 1B2
X_5 => J(4), -- 1B3
X_6 => E(0), -- 1Y\
X_7 => open, -- GND
--
X_9 => J(5), -- 1D3
X_10 => J(6), -- 1D2
X_11 => J(7), -- 1D1
X_12 => J(8), -- 1C2
X_13 => J(9), -- 1C1
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_540.vhd
0,0 → 1,91
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS540N: Octal buffer/line driver (3-state ops) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_540 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_540 is
signal RS, OE : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal I : std_logic_vector(7 downto 0);
alias OEA is JC(9);
alias OEB is JC(8);
begin
I <= std_logic_vector(BC(7 downto 0));
OE <= not(OEA or OEB);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D <= not I when OE = '1' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS540N
port map(
X_1 => OEA, -- E1\
X_2 => I(0), -- A0
X_3 => I(1), -- A1
X_4 => I(2), -- A2
X_5 => I(3), -- A3
X_6 => I(4), -- A4
X_7 => I(5), -- A5
X_8 => I(6), -- A6
X_9 => I(7), -- A7
X_10 => open, -- GND
X_11 => E(7), -- Y7\
X_12 => E(6), -- Y6\
X_13 => E(5), -- Y5\
X_14 => E(4), -- Y4\
X_15 => E(3), -- Y3\
X_16 => E(2), -- Y2\
X_17 => E(1), -- Y1\
X_18 => E(0), -- Y0\
X_19 => OEB, -- E2\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_541.vhd
0,0 → 1,91
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS540N: Octal buffer/line driver (3-state ops) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_541 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_541 is
signal RS, OE : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(9 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal I : std_logic_vector(7 downto 0);
alias OEA is JC(9);
alias OEB is JC(8);
begin
I <= std_logic_vector(BC(7 downto 0));
OE <= not(OEA or OEB);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D <= I when OE = '1' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS541N
port map(
X_1 => OEA, -- E1\
X_2 => I(0), -- A0
X_3 => I(1), -- A1
X_4 => I(2), -- A2
X_5 => I(3), -- A3
X_6 => I(4), -- A4
X_7 => I(5), -- A5
X_8 => I(6), -- A6
X_9 => I(7), -- A7
X_10 => open, -- GND
X_11 => E(7), -- Y7\
X_12 => E(6), -- Y6\
X_13 => E(5), -- Y5\
X_14 => E(4), -- Y4\
X_15 => E(3), -- Y3\
X_16 => E(2), -- Y2\
X_17 => E(1), -- Y1\
X_18 => E(0), -- Y0\
X_19 => OEB, -- E2\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_55.vhd
0,0 → 1,77
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS55N: 2-wide 4-input AOI gate (Pinout B) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_55 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_55 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( (J(0) and J(1) and J(2) and J(3)) or
(J(4) and J(5) and J(6) and J(7)) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS55N
port map(
X_1 => J(0), -- 1A1
X_2 => J(1), -- 1A2
X_3 => J(2), -- 1A3
X_4 => J(3), -- 1A4
--
--
X_7 => open, -- GND
X_8 => E(0), -- 1Y\
--
X_10 => J(4), -- 1B4
X_11 => J(5), -- 1B3
X_12 => J(6), -- 1B2
X_13 => J(7), -- 1B1
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_563.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS563N: 8-bit transparent latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_563 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_563 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
alias OE is J(0);
alias LE is J(1);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
begin
if LE = '1' then
R <= std_logic_vector(B);
end if;
end process;
D <= not R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS563N
port map(
X_1 => OE, -- OE\
X_2 => B(0), -- D0
X_3 => B(1), -- D1
X_4 => B(2), -- D2
X_5 => B(3), -- D3
X_6 => B(4), -- D4
X_7 => B(5), -- D5
X_8 => B(6), -- D6
X_9 => B(7), -- D7
X_10 => open, -- GND
X_11 => LE, -- LE
X_12 => E(7), -- O7\
X_13 => E(6), -- O6\
X_14 => E(5), -- O5\
X_15 => E(4), -- O4\
X_16 => E(3), -- O3\
X_17 => E(2), -- O2\
X_18 => E(1), -- O1\
X_19 => E(0), -- O0\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_564.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS564N: 8-bit D flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_564 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_564 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
signal CLK : std_logic;
alias OE is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
R <= std_logic_vector(B);
end if;
end process;
D <= not R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS564N
port map(
X_1 => OE, -- OE\
X_2 => B(0), -- D0
X_3 => B(1), -- D1
X_4 => B(2), -- D2
X_5 => B(3), -- D3
X_6 => B(4), -- D4
X_7 => B(5), -- D5
X_8 => B(6), -- D6
X_9 => B(7), -- D7
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(7), -- O7
X_13 => E(6), -- O6
X_14 => E(5), -- O5
X_15 => E(4), -- O4
X_16 => E(3), -- O3
X_17 => E(2), -- O2
X_18 => E(1), -- O1
X_19 => E(0), -- O0
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_573.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS573N: 8-bit transparent latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_573 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_573 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
alias OE is J(0);
alias LE is J(1);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
begin
if LE = '1' then
R <= std_logic_vector(B);
end if;
end process;
D <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS573N
port map(
X_1 => OE, -- OE\
X_2 => B(0), -- D0
X_3 => B(1), -- D1
X_4 => B(2), -- D2
X_5 => B(3), -- D3
X_6 => B(4), -- D4
X_7 => B(5), -- D5
X_8 => B(6), -- D6
X_9 => B(7), -- D7
X_10 => open, -- GND
X_11 => LE, -- LE
X_12 => E(7), -- O7\
X_13 => E(6), -- O6\
X_14 => E(5), -- O5\
X_15 => E(4), -- O4\
X_16 => E(3), -- O3\
X_17 => E(2), -- O2\
X_18 => E(1), -- O1\
X_19 => E(0), -- O0\
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_574.vhd
0,0 → 1,93
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS574N: 8-bit D flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_574 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_574 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal R : std_logic_vector(7 downto 0); -- Latch
signal CLK : std_logic;
alias OE is J(0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if rising_edge(CLK) then
R <= std_logic_vector(B);
end if;
end process;
D <= R when OE = '0' else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS574N
port map(
X_1 => OE, -- OE\
X_2 => B(0), -- D0
X_3 => B(1), -- D1
X_4 => B(2), -- D2
X_5 => B(3), -- D3
X_6 => B(4), -- D4
X_7 => B(5), -- D5
X_8 => B(6), -- D6
X_9 => B(7), -- D7
X_10 => open, -- GND
X_11 => CLK, -- CP
X_12 => E(7), -- O7
X_13 => E(6), -- O6
X_14 => E(5), -- O5
X_15 => E(4), -- O4
X_16 => E(3), -- O3
X_17 => E(2), -- O2
X_18 => E(1), -- O1
X_19 => E(0), -- O0
X_20 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_64.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74S64N: 4-2-3-2 input AND-OR-Invert gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_64 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_64 is
signal J, B : unsigned(10 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= not( (J(0) and J(1) and J(2) and J(3)) or
(J(4) and J(5)) or
(J(6) and J(7) and J(8)) or
(J(9) and J(10)) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74S64N
port map(
X_1 => J(0), -- 1D1
X_2 => J(4), -- 1A1
X_3 => J(5), -- 1A2
X_4 => J(6), -- 1B1
X_5 => J(7), -- 1B2
X_6 => J(8), -- 1B3
X_7 => open, -- GND
X_8 => E(0), -- 1Y\
X_9 => J(9), -- 1C2
X_10 => J(10), -- 1C1
X_11 => J(1), -- 1D4
X_12 => J(2), -- 1D3
X_13 => J(3), -- 1D2
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_65.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74S65N: 4-2-3-2 input AOI gate (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_65 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_65 is
signal J, B : unsigned(10 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= TTL_OC( not( (J(0) and J(1) and J(2) and J(3)) or
(J(4) and J(5)) or
(J(6) and J(7) and J(8)) or
(J(9) and J(10)) ) );
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74S65N
port map(
X_1 => J(0), -- 1D1
X_2 => J(4), -- 1A1
X_3 => J(5), -- 1A2
X_4 => J(6), -- 1B1
X_5 => J(7), -- 1B2
X_6 => J(8), -- 1B3
X_7 => open, -- GND
X_8 => E(0), -- 1Y\
X_9 => J(9), -- 1C2
X_10 => J(10), -- 1C1
X_11 => J(1), -- 1D4
X_12 => J(2), -- 1D3
X_13 => J(3), -- 1D2
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_670.vhd
0,0 → 1,132
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS670N: 4 X 4 register file (3-state) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_670 is -- Top-level bench
generic(
OC : boolean := true;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_670 is
subtype T_quad is std_logic_vector(4 downto 1);
type T_mem is array(3 downto 0) of T_quad;
subtype T_addr is natural range 3 downto 0;
 
signal J, B : unsigned(5 downto 0); -- Unused
signal D, E : T_quad; -- Expected & actual results
signal CLK, RS : std_logic;
signal RA, WA : unsigned(1 downto 0) := (others => '0');
signal DI : unsigned(4 downto 0);
signal RE, WE : std_logic := '1';
signal Phase : natural;
 
begin
RA <= J(1 downto 0);
WA <= B(1 downto 0);
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
variable ER : std_logic;
begin
ER := '1';
WE <= '1';
if RS = '0' then
DI <= (others => '0');
elsif rising_edge(CLK) then
DI <= DI + 1;
case to_integer(DI) is
when 5 | 6 | 7 | 8 => WE <= '0' after 15 ns;
when 9 |10 | 11 | 12 => ER := '0';
when 16 => DI <= (others => '0');
when others => null;
end case;
RE <= ER;
end if;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable mem : T_mem; -- Testbench memory
variable AR, AW : natural;
variable QI : T_quad;
begin
AR := TTL_to_integer(RA);
AW := TTL_to_integer(WA);
D <= (others => 'Z');
if WE = '0' then
mem(AW) := std_logic_vector(DI(3 downto 0));
end if;
if RE = '0' then
QI := mem(AR);
for i in D'range loop
D(i) <= QI(i);
end loop;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS670N
port map(
X_1 => DI(1), -- D2
X_2 => DI(2), -- D3
X_3 => DI(3), -- D4
X_4 => RA(1), -- RA1
X_5 => RA(0), -- RA0
X_6 => E(4), -- Q4
X_7 => E(3), -- Q3
X_8 => open, -- GND
X_9 => E(2), -- Q2
X_10 => E(1), -- Q1
X_11 => RE, -- RE\
X_12 => WE, -- WE\
X_13 => WA(1), -- WA1
X_14 => WA(0), -- WA0
X_15 => DI(0), -- D1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_68.vhd
0,0 → 1,125
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS68N: Dual 4-bit decade counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_68 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_68 is
signal RS, C0 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
-- Low bits: the 2+5 counter
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '0' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '0' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
case TTL_to_integer(Q31) is
when 4 to 7 => Q31 := Q31 - 4;
when others => Q31 := Q31 + 1;
end case;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-- High bits: straight BCD counter
process(B, RS) is
variable Q30 : unsigned(3 downto 0);
begin
if RS = '0' then
Q30 := (others => '0');
elsif falling_edge(B(1)) then
case TTL_to_integer(Q30) is
when 9 => Q30 := "0000";
when 11 => Q30 := "0010";
when 13 => Q30 := "0100";
when 15 => Q30 := "0110";
when others => Q30 := Q30 + 1;
end case;
end if;
D(7 downto 4) <= std_logic_vector(Q30);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS68N
port map(
X_1 => B(0), -- 1CLKA
X_2 => E(1), -- 1QB
X_3 => E(3), -- 1QD
X_4 => RS, -- \1CLR
X_5 => E(6), -- 2QC
--
X_7 => E(4), -- 2QA
X_8 => open, -- GND
X_9 => B(1), -- 2CLK
X_10 => E(5), -- 2QB
X_11 => RS, -- \2CLR
X_12 => E(7), -- 2QD
X_13 => E(2), -- 1QC
X_14 => C0, -- 1QA
X_15 => C0, -- 1CLKB
X_16 => open -- Vcc
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_69.vhd
0,0 → 1,116
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS69N: Dual 4-bit binary counter --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_69 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_69 is
signal RS, C0 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
-- Low bits: the 2+8 counter
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '0' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '0' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
Q31 := Q31 + 1;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-- High bits: straight binary counter
process(B, RS) is
variable Q30 : unsigned(3 downto 0);
begin
if RS = '0' then
Q30 := (others => '0');
elsif falling_edge(B(1)) then
Q30 := Q30 + 1;
end if;
D(7 downto 4) <= std_logic_vector(Q30);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS69N
port map(
X_1 => B(0), -- 1CLKA
X_2 => E(1), -- 1QB
X_3 => E(3), -- 1QD
X_4 => RS, -- \1CLR
X_5 => E(6), -- 2QC
--
X_7 => E(4), -- 2QA
X_8 => open, -- GND
X_9 => B(1), -- 2CLK
X_10 => E(5), -- 2QB
X_11 => RS, -- \2CLR
X_12 => E(7), -- 2QD
X_13 => E(2), -- 1QC
X_14 => C0, -- 1QA
X_15 => C0, -- 1CLKB
X_16 => open -- Vcc
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_70.vhd
0,0 → 1,99
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS70N: JK edge-triggered flipflop (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_70 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_70 is
signal RS, CLK : std_logic;
signal J, K : std_logic;
signal JC, BC : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(0) <= '0';
elsif rising_edge(CLK) then
JK := J & K;
case JK is
when "00" => null;
when "01" => D(0) <= '0';
when "10" => D(0) <= '1';
when "11" => D(0) <= not D(0);
when others => null;
end case;
end if;
end process;
D(1) <= not D(0);
J <= BC(0) and BC(1) and not BC(2);
K <= BC(3) and BC(4) and not BC(5);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS70N
port map(
--
X_2 => RS, -- CD\
X_3 => BC(0), -- J1
X_4 => BC(1), -- J2
X_5 => BC(2), -- J3\
X_6 => E(1), -- Q\
X_7 => open, -- GND
X_8 => E(0), -- Q
X_9 => BC(5), -- K3\
X_10 => BC(3), -- K1
X_11 => BC(4), -- K2
X_12 => CLK, -- CP
X_13 => '1', -- SD\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_71.vhd
0,0 → 1,99
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS71N: JK master-slave flipflop (AND/OR inputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_71 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_71 is
signal RS, J, K : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then -- Here, set
D(0) <= '1';
elsif falling_edge(CLK) then
JK := J & K;
case JK is
when "00" => null;
when "01" => D(0) <= '0';
when "10" => D(0) <= '1';
when "11" => D(0) <= not D(0);
when others => null;
end case;
end if;
end process;
D(1) <= not D(0);
J <= (BC(0) and BC(1)) or (BC(2) and BC(3));
K <= (BC(4) and BC(5)) or (BC(6) and BC(7));
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS71N
port map(
X_1 => BC(0), -- J1A
X_2 => BC(1), -- J1B
X_3 => BC(2), -- J2A
X_4 => BC(3), -- J2B
X_5 => RS, -- SD\
X_6 => E(0), -- Q
X_7 => open, -- GND
X_8 => E(1), -- Q\
X_9 => BC(4), -- K1A
X_10 => BC(5), -- K1B
X_11 => BC(6), -- K2A
X_12 => BC(7), -- K2B
X_13 => CLK, -- CP
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_72.vhd
0,0 → 1,99
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS72N: JK master-slave flipflop (AND inputs) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_72 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_72 is
signal RS, J, K : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(0) <= '0';
elsif falling_edge(CLK) then
JK := J & K;
case JK is
when "00" => null;
when "01" => D(0) <= '0';
when "10" => D(0) <= '1';
when "11" => D(0) <= not D(0);
when others => null;
end case;
end if;
end process;
D(1) <= not D(0);
J <= BC(0) and BC(1) and BC(2);
K <= BC(3) and BC(4) and BC(5);
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS72N
port map(
--
X_2 => RS, -- CD\
X_3 => BC(0), -- J1
X_4 => BC(1), -- J2
X_5 => BC(2), -- J3
X_6 => E(1), -- Q\
X_7 => open, -- GND
X_8 => E(0), -- Q
X_9 => BC(3), -- K1
X_10 => BC(4), -- K2
X_11 => BC(5), -- K3
X_12 => CLK, -- CP\
X_13 => '1', -- SD\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_73.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS73N: Dual JK flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_73 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_73 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS73N
port map(
X_1 => CLK, -- CP1\
X_2 => RS, -- CD1\
X_3 => BC(2), -- K1
X_4 => open, -- Vcc
X_5 => CLK, -- CP2\
X_6 => RS, -- CD2\
X_7 => BC(1), -- J2
X_8 => E(3), -- Q2\
X_9 => E(1), -- Q2
X_10 => BC(3), -- K2
X_11 => open, -- GND
X_12 => E(0), -- Q1
X_13 => E(2), -- Q1\
X_14 => BC(0) -- J1
);
end architecture Test;
/trunk/Testbench/Testbench_74.vhd
0,0 → 1,90
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS74N: Dual D-type +ve edge-triggered flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_74 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_74 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
begin
if RS = '0' then
D(i) <= '0';
elsif rising_edge(CLK) then
D(i) <= BC(i);
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS74N
port map(
X_1 => RS, -- CD1\
X_2 => BC(0), -- D1
X_3 => CLK, -- CP1
X_4 => '1', -- SD1\
X_5 => E(0), -- Q1
X_6 => E(2), -- Q1\
X_7 => open, -- GND
X_8 => E(3), -- Q2\
X_9 => E(1), -- Q2
X_10 => '1', -- SD2\
X_11 => CLK, -- CP2
X_12 => BC(1), -- D2
X_13 => RS, -- CD2\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_75.vhd
0,0 → 1,100
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS75N: 4-bit bistable latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_75 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_75 is
signal CLK : std_logic;
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(7 downto 0); -- Expected & actual results
signal S : std_logic_vector(3 downto 0);
signal E12, E34 : std_logic;
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
begin
if falling_edge(CLK) then
E12 <= J(4), '0' after 45 ns;
E34 <= J(5), '0' after 45 ns;
end if;
end process;
S <= (E34, E34, E12, E12);
G1: for i in 3 downto 0 generate
begin
process(S, J) is
begin
if S(i) = '1' then
D(i) <= J(i);
D(i+4) <= not J(i);
end if;
end process;
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS75N
port map(
X_1 => E(4), -- Q1\
X_2 => J(0), -- D1
X_3 => J(1), -- D2
X_4 => E34, -- E34
X_5 => open, -- Vcc
X_6 => J(2), -- D3
X_7 => J(3), -- D4
X_8 => E(7), -- Q4\
X_9 => E(3), -- Q4
X_10 => E(6), -- Q3\
X_11 => E(2), -- Q3
X_12 => open, -- GND
X_13 => E12, -- E12
X_14 => E(5), -- Q2\
X_15 => E(1), -- Q2
X_16 => E(0) -- Q1
);
end architecture Test;
/trunk/Testbench/Testbench_76.vhd
0,0 → 1,100
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS76N: Dual JK flipflop --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_76 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_76 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS76N
port map(
X_1 => CLK, -- CP1\
X_2 => '1', -- SD1\
X_3 => RS, -- CD1\
X_4 => BC(0), -- J1
X_5 => open, -- Vcc
X_6 => CLK, -- CP2\
X_7 => '1', -- SD2\
X_8 => RS, -- CD2\
X_9 => BC(1), -- J2
X_10 => E(3), -- Q2\
X_11 => E(1), -- Q2
X_12 => BC(3), -- K2
X_13 => open, -- GND
X_14 => E(2), -- Q1\
X_15 => E(0), -- Q1
X_16 => BC(2) -- K1
);
end architecture Test;
/trunk/Testbench/Testbench_77.vhd
0,0 → 1,87
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS77N: Quad D-type latch --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_77 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_77 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal S : std_logic_vector(3 downto 0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
S <= (J(5), J(5), J(4), J(4));
G1: for i in 3 downto 0 generate
begin
process(S, J) is
begin
if S(i) = '1' then
D(i) <= J(i);
end if;
end process;
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS77N
port map(
X_1 => J(0), -- D1
X_2 => J(1), -- D2
X_3 => J(5), -- E34
X_4 => open, -- Vcc
X_5 => J(2), -- D3
X_6 => J(3), -- D4
--
X_8 => E(3), -- Q4
X_9 => E(2), -- Q3
--
X_11 => open, -- GND
X_12 => J(4), -- E12
X_13 => E(1), -- Q2
X_14 => E(0) -- Q1
);
end architecture Test;
/trunk/Testbench/Testbench_78.vhd
0,0 → 1,98
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS78N: Dual JK flipflop (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_78 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_78 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
G: for i in 1 downto 0 generate
begin
SIM: process(CLK, RS) is
variable JK : std_logic_vector(1 downto 0);
begin
if RS = '0' then
D(i) <= '0';
elsif falling_edge(CLK) then
JK := BC(i) & BC(2+i);
case JK is
when "00" => null;
when "01" => D(i) <= '0';
when "10" => D(i) <= '1';
when "11" => D(i) <= not D(i);
when others => null;
end case;
end if;
end process;
D(i+2) <= not D(i);
end generate;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS78N
port map(
X_1 => BC(2), -- K1
X_2 => E(0), -- Q1
X_3 => E(2), -- Q1\
X_4 => BC(0), -- J1
X_5 => E(3), -- Q2\
X_6 => E(1), -- Q2
X_7 => open, -- GND
X_8 => BC(3), -- K2
X_9 => CLK, -- CP\
X_10 => '1', -- SD2\
X_11 => BC(1), -- J2
X_12 => RS, -- CD\
X_13 => '1', -- SD1\
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_80.vhd
0,0 → 1,96
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7480N: Gated full adder (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_80 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_80 is
signal JC, BC : unsigned(6 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(BC) is
variable AX, BX, A, B : std_logic;
variable IP : std_logic_vector(2 downto 0);
begin
AX := not (BC(3) and BC(4));
BX := not (BC(5) and BC(6));
A := not (AX and BC(1));
B := not (BX and BC(2));
IP := (BC(0), B, A);
case IP is
when "000" => D(2) <= '1'; D(1) <= '1'; D(0) <= '0';
when "001" => D(2) <= '1'; D(1) <= '0'; D(0) <= '1';
when "010" => D(2) <= '1'; D(1) <= '0'; D(0) <= '1';
when "011" => D(2) <= '0'; D(1) <= '1'; D(0) <= '0';
when "100" => D(2) <= '0'; D(1) <= '0'; D(0) <= '1';
when "101" => D(2) <= '1'; D(1) <= '1'; D(0) <= '0';
when "110" => D(2) <= '1'; D(1) <= '1'; D(0) <= '0';
when "111" => D(2) <= '0'; D(1) <= '0'; D(0) <= '1';
when others => D <= (others => 'X');
end case;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7480N
port map(
-- BX
X_2 => BC(2), -- BC
X_3 => BC(0), -- CN
X_4 => E(2), -- CNP1\
X_5 => E(0), -- S
X_6 => E(1), -- S\
X_7 => open, -- GND
X_8 => BC(3), -- A1
X_9 => BC(4), -- A2
-- AX
X_11 => BC(1), -- AC
X_12 => BC(5), -- B1
X_13 => BC(6), -- B2
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_82.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN7482N: 2-bit full adder --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_82 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_82 is
signal JC, BC : unsigned(4 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(BC) is
variable A, B, C : unsigned(2 downto 0);
begin
A := ('0', BC(1), BC(3));
B := ('0', BC(0), BC(2));
C := A + B + BC(4);
(D(2), D(0), D(1)) <= C;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN7482N
port map(
X_1 => E(1), -- S1
X_2 => BC(3), -- A1
X_3 => BC(2), -- B1
X_4 => open, -- Vcc
X_5 => BC(4), -- CIN
--
--
--
--
X_10 => E(2), -- C2
X_11 => open, -- GND
X_12 => E(0), -- S2
X_13 => BC(0), -- B2
X_14 => BC(1) -- A2
);
end architecture Test;
/trunk/Testbench/Testbench_83.vhd
0,0 → 1,89
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS83AN: 4-bit binary full adder (fast carry) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_83 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_83 is
signal JC, BC : unsigned(8 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(JC) is
variable X, Y, Z : natural := 0;
begin
if now > 1 ns then -- Meaningless to run at T=0
X := TTL_to_integer(JC(7 downto 4));
Y := TTL_to_integer(JC(3 downto 0));
Z := TTL_to_integer(JC(8 downto 8));
Z := Z + X + Y;
end if;
D <= std_logic_vector(to_unsigned(Z, D'length));
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS83AN
port map(
X_1 => JC(3), -- A3
X_2 => E(2), -- S2
X_3 => JC(2), -- A2
X_4 => JC(6), -- B2
X_5 => open, -- Vcc
X_6 => E(1), -- S1
X_7 => JC(5), -- B1
X_8 => JC(1), -- A1
X_9 => E(0), -- S0
X_10 => JC(0), -- A0
X_11 => JC(4), -- B0
X_12 => open, -- GND
X_13 => JC(8), -- C0
X_14 => E(4), -- C4
X_15 => E(3), -- S3
X_16 => JC(7) -- B3
);
end architecture Test;
/trunk/Testbench/Testbench_85.vhd
0,0 → 1,105
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS85N: 4-bit magnitude comparator --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_85 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_85 is
signal JC, BC : unsigned(10 downto 0); -- Test stimuli
signal D, E : std_logic_vector(2 downto 0); -- Expected & actual results
alias inLT is JC(10);
alias inEQ is JC( 9);
alias inGT is JC( 8);
alias A is JC(7 downto 4);
alias B is JC(3 downto 0);
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(JC) is
variable LT, EQ, GT : std_logic;
variable INCOND : std_logic_vector(2 downto 0);
begin
LT := '0';
EQ := '0';
GT := '0';
if A < B then LT := '1';
elsif A > B then GT := '1';
else
INCOND := inGT & inLT & inEQ;
case INCOND is
when "100" => GT := '1';
when "010" => LT := '1';
when "000" => GT := '1'; LT := '1';
when "110" => null;
when others => EQ := '1';
end case;
end if;
D <= (LT, EQ, GT);
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS85N
port map(
X_1 => JC(3), -- B3
X_2 => inLT, -- IA<B
X_3 => inEQ, -- IA=B
X_4 => inGT, -- IA>B
X_5 => E(0), -- OA>B
X_6 => E(1), -- OA=B
X_7 => E(2), -- OA<B
X_8 => open, -- GND
X_9 => JC(0), -- B0
X_10 => JC(4), -- A0
X_11 => JC(1), -- B1
X_12 => JC(5), -- A1
X_13 => JC(6), -- A2
X_14 => JC(2), -- B2
X_15 => JC(7), -- A3
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_86.vhd
0,0 → 1,79
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS86N: Quad 2-input XOR gate --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_86 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_86 is
signal J, B : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
D(0) <= J(0) xor J(1);
D(1) <= J(2) xor J(3);
D(2) <= J(4) xor J(5);
D(3) <= J(6) xor J(7);
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS86N
port map(
X_1 => J(0), -- 1A
X_2 => J(1), -- 1B
X_3 => E(0), -- 1Y\
X_4 => J(2), -- 2A
X_5 => J(3), -- 2B
X_6 => E(1), -- 2Y\
X_7 => open, -- GND
X_8 => E(2), -- 3Y\
X_9 => J(4), -- 3B
X_10 => J(5), -- 3A
X_11 => E(3), -- 4Y\
X_12 => J(6), -- 4B
X_13 => J(7), -- 4A
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_87.vhd
0,0 → 1,84
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74H87N: 4-bit true/complement, zero-one element --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_87 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '0';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_87 is
signal J, B : unsigned(5 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => open,
RS => open,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(J) is
variable S1, S2 : std_logic;
begin
S1 := not J(0);
S2 := J(1);
for i in E'range loop
D(i) <= S2 xor (not(S1 and J(i+2)));
end loop;
end process;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74H87N
port map(
X_1 => J(1), -- S2
X_2 => J(2), -- I1
X_3 => E(0), -- Q1
--
X_5 => J(3), -- I2
X_6 => E(1), -- Q2
X_7 => open, -- GND
X_8 => J(0), -- S1
X_9 => E(2), -- Q3
X_10 => J(4), -- I3
--
X_12 => E(3), -- Q4
X_13 => J(5), -- I4
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_89.vhd
0,0 → 1,153
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS89N: 64-bit RAM (open collector) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_89 is -- Top-level bench
generic(
OC : boolean := true;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_89 is
signal J, B : unsigned(5 downto 0); -- Unused
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TTLword := (others => '0');
signal DI, Q, QQ : TTLquad;
signal CE, WE : std_logic;
 
signal W : std_logic;
signal Phase : natural;
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1;
when 1 => WR <= W; Phase <= 2;
when 2 => WR <= '1'; Phase <= 3;
when others => CS <= '1'; WR <= '1'; Phase <= 0;
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(3 downto 0);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := "0110";
elsif rising_edge(CLK) and Phase = 3 then
if AD = "1111" then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
for i in TD'range loop
DI(i+1) <= TD(i);
end loop;
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
CE <= WR and not CS;
WE <= not(WR or CS);
process(CE, WE, AD, DI) is
variable mem : TTLmem; -- Testbench memory
variable adr : TTLaddr;
variable QI : TTLquad;
begin
adr := TTL_to_integer(AD);
if WE'event and WE = '1' then
mem(adr) := not DI; -- Data is output inverted
end if;
if CE = '1' then
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then
for i in Q'range loop
Q(i) <= TTL_OC(QI(i));
end loop;
else
Q <= QI;
end if;
end process;
D <= Q;
E <= QQ;
 
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS89N
port map(
X_1 => AD(0), -- A0
X_2 => CS, -- CS\
X_3 => WR, -- WE\
X_4 => DI(1), -- D1
X_5 => QQ(1), -- Q1\
X_6 => DI(2), -- D2
X_7 => QQ(2), -- Q2\
X_8 => open, -- GND
X_9 => QQ(3), -- Q3\
X_10 => DI(3), -- D3
X_11 => QQ(4), -- Q4\
X_12 => DI(4), -- D4
X_13 => AD(3), -- A3
X_14 => AD(2), -- A2
X_15 => AD(1), -- A1
X_16 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_90.vhd
0,0 → 1,106
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS90AN: Decade counter (ripple) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_90 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_90 is
signal RS, NRS, C0 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '1' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '1' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
case TTL_to_integer(Q31) is
when 4 to 7 => Q31 := Q31 - 4;
when others => Q31 := Q31 + 1;
end case;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS90AN
port map(
X_1 => C0, -- CP1\
X_2 => RS, -- MR1
X_3 => RS, -- MR2
--
X_5 => open, -- Vcc
X_6 => '0', -- MS1
X_7 => '0', -- MS2
X_8 => E(2), -- Q2
X_9 => E(1), -- Q1
X_10 => open, -- GND
X_11 => E(3), -- Q3
X_12 => C0, -- Q0
--
X_14 => B(0) -- CP0\
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_91.vhd
0,0 → 1,86
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS91AN: 8-bit shift register (Pinout A) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_91 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_91 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(2 downto 0); -- Test stimuli
signal D, E : std_logic_vector(1 downto 0); -- Expected & actual results
 
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK) is
variable SR : std_logic_vector(7 downto 0) := (others => 'U');
begin
if rising_edge(CLK) then
SR := SR(6 downto 0) & nand_reduce(std_logic_vector(JC(1 downto 0)));
D(0) <= SR(7);
D(1) <= not SR(7);
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS91AN
port map(
--
--
--
--
X_5 => open, -- Vcc
--
--
--
X_9 => CLK, -- CP
X_10 => open, -- GND
X_11 => JC(1), -- B
X_12 => JC(0), -- A
X_13 => E(0), -- Q
X_14 => E(1) -- Q\
);
end architecture Test;
/trunk/Testbench/Testbench_92.vhd
0,0 → 1,107
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS92N: Divide-by-12 counter (ripple) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_92 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_92 is
signal RS, NRS, C0 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '1' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '1' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
case TTL_to_integer(Q31) is
when 3 | 6 => Q31 := "000";
when 2 => Q31 := "100";
when others => Q31 := Q31 + 1;
end case;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS92N
port map(
X_1 => C0, -- CP1\
--
--
--
X_5 => open, -- Vcc
X_6 => RS, -- MR1
X_7 => RS, -- MR2
X_8 => E(3), -- Q3
X_9 => E(2), -- Q2
X_10 => open, -- GND
X_11 => E(1), -- Q1
X_12 => C0, -- Q0
--
X_14 => B(0) -- CP0\
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_93.vhd
0,0 → 1,103
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS93N: Divide-by-16 (binary) counter (ripple) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_93 is -- Top-level bench
generic(
StimClk : std_logic := '0';
CheckClk : std_logic := '1';
Period : time := 150 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_93 is
signal RS, NRS, C0 : std_logic;
signal CLK : std_logic;
signal J, B : unsigned(1 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
 
begin
RS <= not NRS;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => NRS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(B, RS) is
variable Q0 : std_logic;
begin
if RS = '1' then
Q0 := '0';
elsif falling_edge(B(0)) then
Q0 := not Q0;
end if;
D(0) <= Q0;
end process;
process(D, RS) is
variable Q31 : unsigned(2 downto 0);
begin
if RS = '1' then
Q31 := (others => '0');
elsif falling_edge(D(0)) then
Q31 := Q31 + 1;
end if;
D(3 downto 1) <= std_logic_vector(Q31);
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS93N
port map(
X_1 => C0, -- CP1\
X_2 => RS, -- MR1
X_3 => RS, -- MR2
--
X_5 => open, -- Vcc
--
--
X_8 => E(2), -- Q2
X_9 => E(1), -- Q1
X_10 => open, -- GND
X_11 => E(3), -- Q3
X_12 => C0, -- Q0
--
X_14 => B(0) -- CP0\
);
E(0) <= C0;
end architecture Test;
/trunk/Testbench/Testbench_94.vhd
0,0 → 1,118
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS94N: 4-bit shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_94 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_94 is
signal RS, RSH : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(0 downto 0); -- Expected & actual results
signal L1, L2 : std_logic;
signal P1, P2, LR : std_logic_vector(3 downto 0);
alias DS is BC(0);
begin
RSH <= not RS;
P1 <= std_logic_vector(BC(3 downto 0));
P2 <= std_logic_vector(BC(7 downto 4));
process(RS, CLK) is
variable X : unsigned(5 downto 0);
begin
if RSH = '1' then
L1 <= '0';
L2 <= '0';
elsif falling_edge(CLK) then -- Inactive clock edge
X := BC(5 downto 0);
case X is
when "010101" => L1 <= '1';
when "101010" => L2 <= '1';
when others => L1 <= '0'; L2 <= '0';
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RS, L1, L2) is
variable SR : std_logic_vector(3 downto 0);
begin
if RS = '0' then
SR := (others => '0');
elsif (L1 or L2) = '1' then -- Asynchronous load
for i in SR'range loop
SR(i) := SR(i) or (L1 and P1(i)) or (L2 and P2(i));
end loop;
elsif rising_edge(CLK) then
SR := SR(2 downto 0) & DS;
end if;
D(0) <= SR(3);
LR <= SR; -- Visibility
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS94N
port map(
X_1 => P1(0), -- P1A
X_2 => P1(1), -- P1B
X_3 => P1(2), -- P1C
X_4 => P1(3), -- P1D
X_5 => open, -- Vcc
X_6 => L1, -- PL1
X_7 => DS, -- DS
X_8 => CLK, -- CP
X_9 => E(0), -- QD
X_10 => RSH, -- CL
X_11 => P2(3), -- P2D
X_12 => open, -- GND
X_13 => P2(2), -- P2C
X_14 => P2(1), -- P2B
X_15 => L2, -- PL2
X_16 => P2(0) -- P2A
);
end architecture Test;
/trunk/Testbench/Testbench_95.vhd
0,0 → 1,114
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS95N: 4-bit right/left shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_95 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_95 is
signal RS : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(3 downto 0); -- Test stimuli
signal D, E : std_logic_vector(3 downto 0); -- Expected & actual results
signal P : std_logic_vector(3 downto 0);
signal CP1, CP2, PE, DS : std_logic := '1';
begin
P <= std_logic_vector(JC(3 downto 0));
DS <= JC(1);
process(CLK, RS) is -- Generate special clocks, etc.
variable X : unsigned(3 downto 0);
variable IPE, IC1, IC2 : std_logic := '1';
begin
if rising_edge(CLK) then
CP1 <= IC1;
CP2 <= IC2;
IC1 := '1';
IC2 := '1';
X := BC(X'range);
if (X = "1000") or (RS = '0') then
IPE := '1';
IC2 := '0'; -- Load
else
IPE := '0';
IC1 := '0'; -- Shift
end if;
elsif falling_edge(CLK) then
CP1 <= '1';
CP2 <= '1';
PE <= IPE;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CP1, CP2) is
begin
if falling_edge(CP1) and PE = '0' then
D <= D(2 downto 0) & DS;
elsif falling_edge(CP2) and PE = '1' then
D <= P;
end if;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS95N
port map(
X_1 => DS, -- DS
X_2 => P(0), -- P0
X_3 => P(1), -- P1
X_4 => P(2), -- P2
X_5 => P(3), -- P3
X_6 => PE, -- PE
X_7 => open, -- GND
X_8 => CP2, -- CP2\
X_9 => CP1, -- CP1\
X_10 => E(3), -- Q3
X_11 => E(2), -- Q2
X_12 => E(1), -- Q1
X_13 => E(0), -- Q0
X_14 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_96.vhd
0,0 → 1,114
-----------------------------------------------------------------------
-- Bipolar TTL models (VHDL) --
-- David R Brooks --
-- June, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for SN74LS96N: 5-bit shift register --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use work.LSTTL.all;
use work.TTLPrivate.all;
entity Testbench_96 is -- Top-level bench
generic(
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 120 ns;
Finish : time := 20 us;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_96 is
signal RS, RSX : std_logic;
signal CLK : std_logic;
signal JC, BC : unsigned(7 downto 0); -- Test stimuli
signal D, E : std_logic_vector(4 downto 0); -- Expected & actual results
signal L : std_logic := '0';
signal P : std_logic_vector(4 downto 0);
alias DS is BC(0);
begin
P <= std_logic_vector(BC(4 downto 0));
process(RS, CLK) is
variable X : unsigned(5 downto 0);
begin
if RS = '0' then
RSX <= '0';
L <= '0';
elsif falling_edge(CLK) then
X := BC(5 downto 0);
case X is
when "000010" => RSX <= '1';
when "001111" => RSX <= '0', '1' after 50 ns;
when "010011" => L <= '1', '0' after 50 ns; -- Just a short pulse
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => JC,
B => BC,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(CLK, RSX, L) is
variable SR : std_logic_vector(4 downto 0);
begin
if RSX = '0' then
SR := (others => '0');
elsif L = '1' then -- Asynchronous load
SR := SR or P;
elsif rising_edge(CLK) then
SR := SR(3 downto 0) & DS;
end if;
D <= SR;
end process;
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: SN74LS96N
port map(
X_1 => CLK, -- CP
X_2 => P(0), -- P0
X_3 => P(1), -- P1
X_4 => P(2), -- P2
X_5 => open, -- Vcc
X_6 => P(3), -- P3
X_7 => P(4), -- P4
X_8 => L, -- PL
X_9 => DS, -- DS
X_10 => E(4), -- Q4
X_11 => E(3), -- Q3
X_12 => open, -- GND
X_13 => E(2), -- Q2
X_14 => E(1), -- Q1
X_15 => E(0), -- Q0
X_16 => RSX -- CL\
);
end architecture Test;
/trunk/Testbench/Testbench_CY7C1021.vhd
0,0 → 1,210
-----------------------------------------------------------------------
-- Basic SRAM models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for CY7C1021: 64k x 16 SRAM (Cypress, 10 ns) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
 
use work.TTLPrivate.all;
use work.Memories.all;
entity Testbench_CY7C1021 is -- Top-level bench
generic(
OC : boolean := false;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 30 ms;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_CY7C1021 is
subtype TDATA is std_logic_vector(15 downto 0);
subtype TADDR is unsigned(15 downto 0);
constant KADTOP : natural := (2**(TADDR'high+1))-1;
subtype TADNUM is natural range KADTOP downto 0;
type TMEM is array(KADTOP downto 0) of TDATA;
 
signal J, B : unsigned(10 downto 0); -- Unused
signal D, E : TDATA; -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TADDR := (others => '0');
signal DI : TDATA;
signal W : std_logic;
signal Phase : natural;
signal OE : std_logic;
signal BHE, BLE : std_logic;
constant AD1 : TADDR := (others => '1');
constant ID1 : unsigned(TDATA'range) := "0000000000000010";
begin
BHE <= '0';
BLE <= '0';
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
OE <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1; OE <= '1';
when 1 => WR <= W; Phase <= 2; OE <= not W;
when 2 => WR <= '1'; Phase <= 3; OE <= '1';
when others => CS <= '1'; WR <= '1'; Phase <= 0; OE <= '1';
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(TDATA'range);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := ID1;
elsif rising_edge(CLK) and Phase = 3 then
if AD = AD1 then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
DI <= TDATA(TD);
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable mem : TMEM; -- Testbench memory
variable adr : TADNUM;
variable QI : TDATA;
begin
D <= E; -- Default, if not active
if CS = '0' then -- Device active
adr := TTL_to_integer(AD);
if rising_edge(WR) then -- Rising (ie trailing) edge
mem(adr) := DI;
end if;
if OE = '0' then -- Reading
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then -- Simulate open collector
for i in D'range loop
D(i) <= TTL_OC(QI(i));
end loop;
else
D <= QI;
end if;
end if;
end process;
process(CLK) is -- During writes, mimic the data
begin
if falling_edge(CLK) then
if W = '0' then
case Phase is
when 1 | 2 => D <= E;
when others => D <= (others => 'Z');
end case;
end if;
end if;
end process;
E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: CY7C1021
generic map(
fnevn => "", -- Name of even-byte initialisation file (if any)
fnodd => "" -- Name of odd-byte initialisation file (if any)
)
port map(
X_1 => AD(4), -- A4
X_2 => AD(3), -- A3
X_3 => AD(2), -- A2
X_4 => AD(1), -- A1
X_5 => AD(0), -- A0
X_6 => CS, -- CE\
X_7 => E(0), -- IO0
X_8 => E(1), -- IO1
X_9 => E(2), -- IO2
X_10 => E(3), -- IO3
X_11 => open, -- Vcc
X_12 => open, -- GND
X_13 => E(4), -- IO4
X_14 => E(5), -- IO5
X_15 => E(6), -- IO6
X_16 => E(7), -- IO7
X_17 => WR, -- WE\
X_18 => AD(15), -- A15
X_19 => AD(14), -- A14
X_20 => AD(13), -- A13
X_21 => AD(12), -- A12
-- X_22
-- X_23
X_24 => AD(11), -- A11
X_25 => AD(10), -- A10
X_26 => AD(9), -- A9
X_27 => AD(8), -- A8
-- X_28
X_29 => E(8), -- IO8
X_30 => E(9), -- IO9
X_31 => E(10), -- IO10
X_32 => E(11), -- IO11
X_33 => open, -- VCC
X_34 => open, -- GND
X_35 => E(12), -- IO12
X_36 => E(13), -- IO13
X_37 => E(14), -- IO14
X_38 => E(15), -- IO15
X_39 => BLE, -- BLE\
X_40 => BHE, -- BHE\
X_41 => OE, -- OE\
X_42 => AD(7), -- A7
X_43 => AD(6), -- A6
X_44 => AD(5) -- A5
);
end architecture Test;
/trunk/Testbench/Testbench_HM6116.vhd
0,0 → 1,186
-----------------------------------------------------------------------
-- Basic SRAM models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for HM6116: 2k x 8 SRAM --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
 
use work.TTLPrivate.all;
use work.Memories.all;
entity Testbench_HM6116 is -- Top-level bench
generic(
OC : boolean := false;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 2 ms;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_HM6116 is
subtype TDATA is std_logic_vector(7 downto 0);
subtype TADDR is unsigned(10 downto 0);
constant KADTOP : natural := (2**(TADDR'high+1))-1;
subtype TADNUM is natural range KADTOP downto 0;
type TMEM is array(KADTOP downto 0) of TDATA;
 
signal J, B : unsigned(10 downto 0); -- Unused
signal D, E : TDATA; -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TADDR := (others => '0');
signal DI : TDATA;
signal W : std_logic;
signal Phase : natural;
signal OE : std_logic;
constant AD1 : TADDR := (others => '1');
constant ID1 : unsigned(TDATA'range) := "00000010";
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
OE <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1; OE <= '1';
when 1 => WR <= W; Phase <= 2; OE <= not W;
when 2 => WR <= '1'; Phase <= 3; OE <= '1';
when others => CS <= '1'; WR <= '1'; Phase <= 0; OE <= '1';
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(TDATA'range);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := ID1;
elsif rising_edge(CLK) and Phase = 3 then
if AD = AD1 then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
DI <= TDATA(TD);
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable mem : TMEM; -- Testbench memory
variable adr : TADNUM;
variable QI : TDATA;
begin
D <= E; -- Default, if not active
if CS = '0' then -- Device active
adr := TTL_to_integer(AD);
if rising_edge(WR) then -- Rising (ie trailing) edge
mem(adr) := DI;
end if;
if OE = '0' then -- Reading
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then -- Simulate open collector
for i in D'range loop
D(i) <= TTL_OC(QI(i));
end loop;
else
D <= QI;
end if;
end if;
end process;
process(CLK) is -- During writes, mimic the data
begin
if falling_edge(CLK) then
if W = '0' then
case Phase is
when 1 | 2 => D <= E;
when others => D <= (others => 'Z');
end case;
end if;
end if;
end process;
E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: HM6116
generic map(
fname => "" -- Name of initialisation file (if any)
)
port map(
X_1 => AD(7), -- A7
X_2 => AD(6), -- A6
X_3 => AD(5), -- A5
X_4 => AD(4), -- A4
X_5 => AD(3), -- A3
X_6 => AD(2), -- A2
X_7 => AD(1), -- A1
X_8 => AD(0), -- A0
X_9 => E(0), -- IO0
X_10 => E(1), -- IO1
X_11 => E(2), -- IO2
X_12 => open, -- GND
X_13 => E(3), -- IO3
X_14 => E(4), -- IO4
X_15 => E(5), -- IO5
X_16 => E(6), -- IO6
X_17 => E(7), -- IO7
X_18 => CS, -- CS\
X_19 => AD(10), -- A10
X_20 => OE, -- OE\
X_21 => WR, -- WE\
X_22 => AD(9), -- A9
X_23 => AD(8), -- A8
X_24 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_IS61C1024.vhd
0,0 → 1,194
-----------------------------------------------------------------------
-- Basic SRAM models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for IS61C1024: 128k x 8 SRAM (ISSI, 20 ns) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
 
use work.TTLPrivate.all;
use work.Memories.all;
entity Testbench_IS61C1024 is -- Top-level bench
generic(
OC : boolean := false;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 50 ns;
Finish : time := 53 ms;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_IS61C1024 is
subtype TDATA is std_logic_vector(7 downto 0);
subtype TADDR is unsigned(16 downto 0);
constant KADTOP : natural := (2**(TADDR'high+1))-1;
subtype TADNUM is natural range KADTOP downto 0;
type TMEM is array(KADTOP downto 0) of TDATA;
 
signal J, B : unsigned(10 downto 0); -- Unused
signal D, E : TDATA; -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TADDR := (others => '0');
signal DI : TDATA;
signal W : std_logic;
signal Phase : natural;
signal OE : std_logic;
constant AD1 : TADDR := (others => '1');
constant ID1 : unsigned(TDATA'range) := "00000010";
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
OE <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1; OE <= '1';
when 1 => WR <= W; Phase <= 2; OE <= not W;
when 2 => WR <= '1'; Phase <= 3; OE <= '1';
when others => CS <= '1'; WR <= '1'; Phase <= 0; OE <= '1';
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(TDATA'range);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := ID1;
elsif rising_edge(CLK) and Phase = 3 then
if AD = AD1 then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
DI <= TDATA(TD);
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable mem : TMEM; -- Testbench memory
variable adr : TADNUM;
variable QI : TDATA;
begin
D <= E; -- Default, if not active
if CS = '0' then -- Device active
adr := TTL_to_integer(AD);
if rising_edge(WR) then -- Rising (ie trailing) edge
mem(adr) := DI;
end if;
if OE = '0' then -- Reading
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then -- Simulate open collector
for i in D'range loop
D(i) <= TTL_OC(QI(i));
end loop;
else
D <= QI;
end if;
end if;
end process;
process(CLK) is -- During writes, mimic the data
begin
if falling_edge(CLK) then
if W = '0' then
case Phase is
when 1 | 2 => D <= E;
when others => D <= (others => 'Z');
end case;
end if;
end if;
end process;
E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: IS61C1024
generic map(
fname => "" -- Name of initialisation file (if any)
)
port map(
-- X_1
X_2 => AD(16), -- A16
X_3 => AD(14), -- A14
X_4 => AD(12), -- A12
X_5 => AD(7), -- A7
X_6 => AD(6), -- A6
X_7 => AD(5), -- A5
X_8 => AD(4), -- A4
X_9 => AD(3), -- A3
X_10 => AD(2), -- A2
X_11 => AD(1), -- A1
X_12 => AD(0), -- A0
X_13 => E(0), -- IO0
X_14 => E(1), -- IO1
X_15 => E(2), -- IO2
X_16 => open, -- GND
X_17 => E(3), -- IO3
X_18 => E(4), -- IO4
X_19 => E(5), -- IO5
X_20 => E(6), -- IO6
X_21 => E(7), -- IO7
X_22 => CS, -- CE1\
X_23 => AD(10), -- A10
X_24 => OE, -- OE\
X_25 => AD(11), -- A11
X_26 => AD(9), -- A9
X_27 => AD(8), -- A8
X_28 => AD(13), -- A13
X_29 => WR, -- WE\
X_30 => '1', -- CE2
X_31 => AD(15), -- A15
X_32 => open -- Vcc
);
end architecture Test;
/trunk/Testbench/Testbench_MB84256.vhd
0,0 → 1,191
-----------------------------------------------------------------------
-- Basic SRAM models (VHDL) --
-- David R Brooks --
-- December, 2016. Perth, Australia --
-- Compliance: VHDL 2008 --
-- Testbench for MB84256: 32k x 8 SRAM (Fujitsu, 100 ns) --
-----------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
 
use work.TTLPrivate.all;
use work.Memories.all;
entity Testbench_MB84256 is -- Top-level bench
generic(
OC : boolean := false;
StimClk : std_logic := '1';
CheckClk : std_logic := '1';
Period : time := 100 ns;
Finish : time := 30 ms;
SevLevel : severity_level := failure
);
end entity;
 
architecture Test of Testbench_MB84256 is
subtype TDATA is std_logic_vector(7 downto 0);
subtype TADDR is unsigned(14 downto 0);
constant KADTOP : natural := (2**(TADDR'high+1))-1;
subtype TADNUM is natural range KADTOP downto 0;
type TMEM is array(KADTOP downto 0) of TDATA;
 
signal J, B : unsigned(10 downto 0); -- Unused
signal D, E : TDATA; -- Expected & actual results
signal CLK, RS : std_logic;
signal CS, WR : std_logic := '1';
signal AD : TADDR := (others => '0');
signal DI : TDATA;
signal W : std_logic;
signal Phase : natural;
signal OE : std_logic;
constant AD1 : TADDR := (others => '1');
constant ID1 : unsigned(TDATA'range) := "00000010";
begin
-----------------------------------------------------------------------
-- Standard testbench components
-----------------------------------------------------------------------
TB: TTLBench
generic map(
StimClk => StimClk,
CheckClk => CheckClk,
Period => Period,
Finish => Finish,
SevLevel => SevLevel
)
port map(
J => J,
B => B,
CLK => CLK,
RS => RS,
D => D,
E => E
);
-----------------------------------------------------------------------
-- Generate RAM-specific stimuli
-----------------------------------------------------------------------
CLKX: process(CLK, RS) is
begin
if RS = '0' then
Phase <= 0;
CS <= '1';
WR <= '1';
OE <= '1';
elsif rising_edge(CLK) then
case Phase is
when 0 => CS <= '0'; Phase <= 1; OE <= '1';
when 1 => WR <= W; Phase <= 2; OE <= not W;
when 2 => WR <= '1'; Phase <= 3; OE <= '1';
when others => CS <= '1'; WR <= '1'; Phase <= 0; OE <= '1';
end case;
end if;
end process;
UPDATE: process(CLK, RS) is
variable TD : unsigned(TDATA'range);
begin
if RS = '0' then
W <= '0';
AD <= (others => '0');
TD := ID1;
elsif rising_edge(CLK) and Phase = 3 then
if AD = AD1 then
W <= not W; -- Alternate read/write cycles
end if;
AD <= AD + 1;
TD := TD + 1;
end if;
DI <= TDATA(TD);
end process;
-----------------------------------------------------------------------
-- Generate expected results (with zero delays)
-----------------------------------------------------------------------
process(all) is
variable mem : TMEM; -- Testbench memory
variable adr : TADNUM;
variable QI : TDATA;
begin
D <= E; -- Default, if not active
if CS = '0' then -- Device active
adr := TTL_to_integer(AD);
if rising_edge(WR) then -- Rising (ie trailing) edge
mem(adr) := DI;
end if;
if OE = '0' then -- Reading
QI := mem(adr);
else
QI := (others => 'Z');
end if;
if OC then -- Simulate open collector
for i in D'range loop
D(i) <= TTL_OC(QI(i));
end loop;
else
D <= QI;
end if;
end if;
end process;
process(CLK) is -- During writes, mimic the data
begin
if falling_edge(CLK) then
if W = '0' then
case Phase is
when 1 | 2 => D <= E;
when others => D <= (others => 'Z');
end case;
end if;
end if;
end process;
E <= DI when (W = '0') and (Phase = 1 or Phase = 2) else (others => 'Z');
-----------------------------------------------------------------------
-- Device Under Test...
-----------------------------------------------------------------------
DUT: MB84256
generic map(
fname => "" -- Name of initialisation file (if any)
)
port map(
X_1 => AD(14), -- A14
X_2 => AD(12), -- A12
X_3 => AD(7), -- A7
X_4 => AD(6), -- A6
X_5 => AD(5), -- A5
X_6 => AD(4), -- A4
X_7 => AD(3), -- A3
X_8 => AD(2), -- A2
X_9 => AD(1), -- A1
X_10 => AD(0), -- A0
X_11 => E(0), -- IO0
X_12 => E(1), -- IO1
X_13 => E(2), -- IO2
X_14 => open, -- GND
X_15 => E(3), -- IO3
X_16 => E(4), -- IO4
X_17 => E(5), -- IO5
X_18 => E(6), -- IO6
X_19 => E(7), -- IO7
X_20 => CS, -- CS\
X_21 => AD(10), -- A10
X_22 => OE, -- OE\
X_23 => AD(11), -- A11
X_24 => AD(9), -- A9
X_25 => AD(8), -- A8
X_26 => AD(13), -- A13
X_27 => WR, -- WE\
X_28 => open -- Vcc
);
end architecture Test;

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