URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/turbo8051/trunk/rtl/core
- from Rev 56 to Rev 57
- ↔ Reverse comparison
Rev 56 → Rev 57
/core.v
452,7 → 452,7
// Reg Bus Interface Signal |
. reg_cs (reg_mac_cs ), |
. reg_wr (reg_mac_wr ), |
. reg_addr (reg_mac_addr[12:2] ), |
. reg_addr (reg_mac_addr[5:2] ), |
. reg_wdata (reg_mac_wdata ), |
. reg_be (reg_mac_be ), |
|
532,7 → 532,7
.desc_q_empty (tx_q_empty ), |
|
// Master Interface Signal |
.mem_taddr ( 1 ), |
.mem_taddr ( 4'h1 ), |
.mem_full (app_txfifo_full_o ), |
.mem_afull (app_txfifo_afull_o ), |
.mem_wr (app_txfifo_wren_i ), |
559,7 → 559,7
|
|
// Master Interface Signal |
.mem_taddr ( 1 ), |
.mem_taddr ( 4'h1 ), |
.mem_addr (app_rxfifo_addr ), |
.mem_empty (app_rxfifo_empty_o ), |
.mem_aempty (app_rxfifo_aempty_o ), |
602,7 → 602,7
// Reg Bus Interface Signal |
. reg_cs (reg_uart_cs ), |
. reg_wr (reg_uart_wr ), |
. reg_addr (reg_uart_addr[4:2] ), |
. reg_addr (reg_uart_addr[5:2] ), |
. reg_wdata (reg_uart_wdata ), |
. reg_be (reg_uart_be ), |
|
632,7 → 632,7
// Reg Bus Interface Signal |
. reg_cs (reg_spi_cs ), |
. reg_wr (reg_spi_wr ), |
. reg_addr (reg_spi_addr[12:2] ), |
. reg_addr (reg_spi_addr[5:2] ), |
. reg_wdata (reg_spi_wdata ), |
. reg_be (reg_spi_be ), |
|