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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

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  • This comparison shows the changes necessary to convert path 
    /turbo8051/trunk/rtl/gmac/mac
    from Rev 70 to Rev 76
    ↔ Reverse comparison
  •

Rev 70 → Rev 76

/byte_reg.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
/dble_reg.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
46,7 → 48,6
Synchronizes the pulse from one clock to another
* clock domain
***********************************************************************/
//`timescale 1ns/100ps
module half_dup_dble_reg (
//outputs
sync_out_pulse,
/g_cfg_mgmt.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
46,7 → 48,6
read from any location. But can write to a limited set of locations,
Please refer to the design data sheets for register locations
***********************************************************************/
//`timescale 1ns/100ps
module g_cfg_mgmt (
//List of Inputs
 
/g_deferral.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
/***************************************************************
Description:
/g_deferral_rx.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
/g_mac_core.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
module g_mac_core (
scan_mode,
s_reset_n,
/g_md_intf.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
/***************************************************************
Description:
/g_mii_intf.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
/***************************************************************
Description:
/g_rx_fsm.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
52,7 → 54,6
***************************************************************/
/************** MODULE DECLARATION ****************************/
//`timescale 1ns/100ps
module g_rx_fsm(
// Status information to Applications
rx_sts_vld,
1105,4 → 1106,4
end // else: !if(!reset_n)
end // always @ (posedge phy_rx_clk...
endmodule
endmodule
/g_rx_top.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
module g_rx_top(
app_reset_n,
/g_tx_fsm.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
/***************************************************************
Description:
/g_tx_top.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
40,7 → 42,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//`timescale 1ns/100ps
 
/***************************************************************
Description:
/s2f_sync.v
14,6 → 14,8
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : Mar 2, 2011 ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
45,7 → 47,6
Synchronizes the pulse from one clock to another
* clock domain
***********************************************************************/
//`timescale 1ns/100ps
module s2f_sync (
//outputs
sync_out_pulse,

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