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    /turbo8051/trunk/rtl
    from Rev 34 to Rev 36
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Rev 34 → Rev 36

/gmac/mac/g_mac_core.v
102,7 → 102,13
mdio_clk,
mdio_in,
mdio_out_en,
mdio_out
mdio_out,
 
// configuration output
cf_mac_sa,
cfg_ip_sa,
cfg_mac_filter
 
);
parameter mac_mdio_en = 1'b1;
188,6 → 194,9
output mdio_out_en;
output mdio_out;
output [47:0] cf_mac_sa;
output [31:0] cfg_ip_sa;
output [31:0] cfg_mac_filter;
//-----------------------------------------------------------------------
// RX-Clock Domain Status Signal
//-----------------------------------------------------------------------
215,9 → 224,9
// The packet after a packet that
// underran has 1 too few bytes .
 
wire[7:0] mi2rx_rx_byte,tx2mi_tx_byte;
wire [7:0] cf2df_dfl_single_rx;
wire [15:0] cf2rx_max_pkt_sz;
wire[7:0] mi2rx_rx_byte,tx2mi_tx_byte;
wire [7:0] cf2df_dfl_single_rx;
wire [15:0] cf2rx_max_pkt_sz;
 
g_rx_top u_rx_top(
//application
528,6 → 537,8
.cf2rx_runt_pkt_en (cf2rx_runt_pkt_en),
.cf2af_broadcast_disable (cf2af_broadcast_disable),
.cf_mac_sa (cf_mac_sa),
.cfg_ip_sa (cfg_ip_sa),
.cfg_mac_filter (cfg_mac_filter),
.cf2tx_pause_quanta (cf2tx_pause_quanta),
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
//MDIO CONTROL & DATA
/gmac/mac/g_cfg_mgmt.v
70,43 → 70,46
tx_sts,
 
// MDIO READ DATA FROM PHY
md2cf_cmd_done,
md2cf_status,
md2cf_data,
app_clk,
app_reset_n,
md2cf_cmd_done,
md2cf_status,
md2cf_data,
app_clk,
app_reset_n,
 
//List of Outputs
// MII Control
cf2mi_loopback_en,
cf_mac_mode,
cf_chk_rx_dfl,
cf2mi_rmii_en,
//List of Outputs
// MII Control
cf2mi_loopback_en,
cf_mac_mode,
cf_chk_rx_dfl,
cf2mi_rmii_en,
 
cfg_uni_mac_mode_change_i,
cfg_crs_flow_ctrl_enb_i,
 
//CHANNEL enable
cf2tx_ch_en,
//CHANNEL CONTROL TX
cf_silent_mode,
cf2df_dfl_single,
cf2df_dfl_single_rx,
cf2tx_pad_enable,
cf2tx_append_fcs,
//CHANNEL CONTROL RX
cf2rx_ch_en,
cf2rx_strp_pad_en,
cf2rx_snd_crc,
cf2rx_pause_en,
cf2rx_addrchk_en,
cf2rx_runt_pkt_en,
cf2af_broadcast_disable,
cf_mac_sa,
cf2tx_pause_quanta,
cf2rx_max_pkt_sz,
cf2tx_force_bad_fcs,
//CHANNEL enable
cf2tx_ch_en,
//CHANNEL CONTROL TX
cf_silent_mode,
cf2df_dfl_single,
cf2df_dfl_single_rx,
cf2tx_pad_enable,
cf2tx_append_fcs,
//CHANNEL CONTROL RX
cf2rx_ch_en,
cf2rx_strp_pad_en,
cf2rx_snd_crc,
cf2rx_pause_en,
cf2rx_addrchk_en,
cf2rx_runt_pkt_en,
cf2af_broadcast_disable,
cf_mac_sa,
cfg_ip_sa,
cfg_mac_filter,
 
cf2tx_pause_quanta,
cf2rx_max_pkt_sz,
cf2tx_force_bad_fcs,
cf2tx_tstate_mode,
//MDIO CONTROL & DATA
cf2md_datain,
152,6 → 155,8
output cf_mac_mode; // mac mode set this to 1 for 100Mbs/10Mbs
output cf_chk_rx_dfl; // Check for RX Deferal
output [47:0] cf_mac_sa;
output [31:0] cfg_ip_sa;
output [31:0] cfg_mac_filter;
output [15:0] cf2tx_pause_quanta;
output cf2tx_ch_en; //enable the TX channel
output cf_silent_mode; // PHY Inactive
424,7 → 429,7
// BIT[31:8] = Reserved
generic_register #(8,0 ) rx_cntrl_reg_1 (
.we ({8{sw_wr_en_1 &
wr_be[0] }} ),
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
451,7 → 456,7
 
generic_register #(8,0 ) dfl_params1_en_reg (
.we ({8{sw_wr_en_2 &
wr_be[0] }} ),
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
464,7 → 469,7
 
generic_register #(8,0 ) dfl_params_rx_en_reg (
.we ({8{sw_wr_en_2 &
wr_be[1] }} ),
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
516,7 → 521,7
 
generic_register #(8,0 ) mdio_cmd_reg_1 (
.we ({8{sw_wr_en_4 &
wr_be[0] }} ),
wr_be[0] }} ),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
527,7 → 532,7
 
generic_register #(8,0 ) mdio_cmd_reg_2 (
.we ({8{sw_wr_en_4 &
wr_be[1] }} ),
wr_be[1] }} ),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
807,13 → 812,95
. hware_req ({tx_sts,rx_sts[7:0]} ),
//outputs
. data_out (reg_14[8:0] )
. data_out (reg_13[8:0] )
);
 
 
// IP SA [31:0]
 
generic_register #(8,0 ) u_ip_sa_0 (
.we ({8{sw_wr_en_14 & wr_be[0] }}),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_ip_sa[7:0] )
);
 
generic_register #(8,0 ) u_ip_sa_1 (
.we ({8{sw_wr_en_14 & wr_be[1] }}),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_ip_sa[15:8] )
);
 
 
generic_register #(8,0 ) u_ip_sa_2 (
.we ({8{sw_wr_en_14 & wr_be[2] }}),
.data_in (reg_wdata[23:16] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_ip_sa[23:16] )
);
 
generic_register #(8,0 ) u_ip_sa_3 (
.we ({8{sw_wr_en_14 & wr_be[3] }}),
.data_in (reg_wdata[31:24] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_ip_sa[31:24] )
);
 
// Mac filter
 
generic_register #(8,0 ) u_mac_filter_0 (
.we ({8{sw_wr_en_15 & wr_be[0] }}),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_mac_filter[7:0] )
);
 
generic_register #(8,0 ) u_mac_filter_1 (
.we ({8{sw_wr_en_14 & wr_be[1] }}),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_mac_filter[15:8] )
);
 
 
generic_register #(8,0 ) u_mac_filter_2 (
.we ({8{sw_wr_en_14 & wr_be[2] }}),
.data_in (reg_wdata[23:16] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_mac_filter[23:16] )
);
 
generic_register #(8,0 ) u_mac_filter_3 (
.we ({8{sw_wr_en_14 & wr_be[3] }}),
.data_in (reg_wdata[31:24] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (cfg_mac_filter[31:24] )
);
endmodule
 
 
/gmac/top/filelist_top.f
15,6 → 15,7
g_rx_crc32.v
g_tx_crc32.v
async_fifo.v
eth_parser.v
-v registers.v
-v stat_counter.v
-v toggle_sync.v
/gmac/top/g_mac_top.v
214,6 → 214,35
wire tx_fifo_rdy;
wire [AW:0] tx_fifo_aval;
 
wire [47:0] cf_mac_sa;
wire [31:0] cfg_ip_sa;
wire [31:0] cfg_mac_filter;
 
 
g_eth_parser u_eth_parser (
.s_reset_n (app_reset_n),
.app_clk (app_clk),
 
// Configuration
.cfg_filters (cfg_filters),
.cfg_mac_sa (cf_mac_sa),
.cfg_ip_sa (cfg_ip_sa),
 
// Input Control Information
.eop (app_rxfifo_rdata_o[8]),
.dval (app_rxfifo_rden_i),
.data (app_rxfifo_rdata_o[7:0]),
// output status
.pkt_done (),
.pkt_len (),
.pkt_status (),
.pkt_drop_ind (),
.pkt_drop_reason ()
);
 
 
 
g_mac_core u_mac_core (
.scan_mode (scan_mode),
.s_reset_n (s_reset_n) ,
278,7 → 307,12
.mdio_clk (mdio_clk) ,
.mdio_in (mdio_in) ,
.mdio_out_en (mdio_out_en) ,
.mdio_out (mdio_out)
.mdio_out (mdio_out),
 
.cf_mac_sa (cf_mac_sa),
.cfg_ip_sa (cfg_ip_sa),
.cfg_mac_filter (cfg_mac_filter)
 
);
 
assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
/gmac/ctrl/eth_parser.v
0,0 → 1,293
//////////////////////////////////////////////////////////////////////
//// ////
//// Tubo 8051 cores MAC Interface Module ////
//// ////
//// This file is part of the Turbo 8051 cores project ////
//// http://www.opencores.org/cores/turbo8051/ ////
//// ////
//// Description ////
//// Turbo 8051 definitions. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// ------------------------------------------------------------------------
// Description :
// This module instantiates the Eth/Arp/IP/TCP/UDP Packet Parser
//
// ------------------------------------------------------------------------
module g_eth_parser (
s_reset_n,
app_clk,
 
// Configuration
cfg_filters,
cfg_mac_sa,
cfg_ip_sa,
 
// Input Control Information
eop,
dval,
data,
// output status
pkt_done,
pkt_len,
pkt_status,
pkt_drop_ind,
pkt_drop_reason
);
 
//------------------------------
// Global Input signal
//------------------------------
input s_reset_n; // Active low reset signal
input app_clk ; // Application clock
 
//------------------------------
// Configuration
//------------------------------
input [31:0] cfg_filters; // Filter rules
// [0] - filtering enabled
// [1] - allow local mac-da only
// [2] - allow local mac-da only + IP4 local ip-da
// [3] - allow local mac-da only + IP4 local ip-da + TCP
// [4] - allow local mac-da only + IP4 local ip-da + UDP
// [5] - allow local mac-da only + IP4 local ip-da + ICMP
// [6] - allow local mac-da only + ARP
 
input [47:0] cfg_mac_sa; // 48 bit mac DA
input [31:0] cfg_ip_sa; // 32 bit IP DA
 
//---------------------------
// Input Control Information
//---------------------------
input eop;
input dval;
input [7:0] data;
 
//-----------------------------
// output status
//-----------------------------
output [11:0] pkt_len; // Packet Length
output pkt_done; // Packet Processing done indication
output [6:0] pkt_status; // packet processing status
// [1:0] - MAC-DA
// 2'b00 - Broadcast frame
// 2'b01 - Multicast frame
// 2'b10 - unicast frame, other than local DA
// 2'b11 - unicast local DA frame
// [3:2] - MAC-SA
// 2'b00 - Broadcast frame
// 2'b01 - Multicast frame
// 2'b10 - unicast frame, other than local DA
// 2'b11 - unicast local DA frame
// [6:4] - 3'b000 - Unknown Ethernet frame
// 3'b001 - IP4 Frame
// 3'b010 - IP4 Frame + TCP
// 3'b011 - IP4 Frame + UDP
// 3'b100 - IP4 Frame + ICMP
// 3'b101 - ARP frame
output pkt_drop_ind; // Packet Drop Inidcation
 
output [7:0] pkt_drop_reason; // Reason for Frame Drop
// [0] - Non Local DA
// [1] - Local DA == Remote SA
// [2] - Non Local IP-DA
// [3] - Local IP-DA == Remote IP-SA
// [4] - Not Valid IP4/TCP/UDP/ARP/ICMP Frame
// [5] - L2 Check sum error
// [6] - L3 Check Sum Error
// [7] - L4 Check Sum Error
 
reg [11:0] bcnt ; // Byte counter
reg [11:0] pkt_len ; // packet length
reg pkt_done ; // packet complete indication + Packet Status Valid
 
always @(s_reset_n or posedge app_clk) begin
if(s_reset_n == 1'b0) begin
bcnt <= 0;
pkt_len <= 0;
pkt_done <= 0;
end
else begin
if(dval) begin
if(eop) begin
bcnt <= 0;
pkt_len <= bcnt +1;
pkt_done <= 1;
end else begin
bcnt <= bcnt +1;
pkt_done <= 0;
end
end else begin
pkt_done <= 0;
end
end
end
 
reg mac_da_bc ; // frame da is broad cast
reg mac_da_mc ; // frame da is multicast
reg mac_da_match ; // frame da match to local address
reg mac_sa_bc ; // frame sa is broadcast
reg mac_sa_mc ; // frame sa is multicast
reg mac_sa_match ; // frame sa match to local address
reg ipv4f ; // frame is ipv4
reg arpf ; // frame is arp
reg tcpf ; // frame is tcp
reg udpf ; // frame is udp
reg ip_sa_match ; // ip4 sa matches to local IP Address
reg ip_da_match ; // ip4 da matches to local IP Address
reg[6:0] pkt_status ; // Packet Status
 
always @(s_reset_n or posedge app_clk) begin
if(s_reset_n == 1'b0) begin
mac_da_bc <= 0;
mac_da_mc <= 0;
mac_da_match <= 0;
mac_sa_bc <= 0;
mac_sa_mc <= 0;
mac_sa_match <= 0;
ipv4f <= 0;
arpf <= 0;
tcpf <= 0;
udpf <= 0;
ip_sa_match <= 0;
ip_da_match <= 0;
pkt_status <= 0;
end
else begin
if(dval) begin
if(!eop) begin
// DA Analysis
// Broadcast Frame
mac_da_bc <= (bcnt == 0) ? (data == 8'hff) :
(bcnt == 1) ? (data == 8'hff) & mac_da_bc :
(bcnt == 2) ? (data == 8'hff) & mac_da_bc :
(bcnt == 3) ? (data == 8'hff) & mac_da_bc :
(bcnt == 4) ? (data == 8'hff) & mac_da_bc :
(bcnt == 5) ? (data == 8'hff) & mac_da_bc : mac_da_bc;
// multicast frame
mac_da_mc <= (bcnt == 0) ? (data[7] == 1'b1) : mac_da_mc & !mac_da_bc;
 
// local unicast frame
mac_da_match <= (bcnt == 0) ? (cfg_mac_sa[7:0] == data) :
(bcnt == 1) ? (cfg_mac_sa[15:8] == data) & mac_da_match :
(bcnt == 2) ? (cfg_mac_sa[23:16] == data) & mac_da_match :
(bcnt == 3) ? (cfg_mac_sa[31:24] == data) & mac_da_match :
(bcnt == 4) ? (cfg_mac_sa[39:32] == data) & mac_da_match :
(bcnt == 5) ? (cfg_mac_sa[47:40] == data) & mac_da_match :
mac_da_match;
 
 
// SA Analysis
mac_sa_bc <= (bcnt == 6) ? (data == 8'hff) :
(bcnt == 7) ? (data == 8'hff) & mac_sa_bc :
(bcnt == 8) ? (data == 8'hff) & mac_sa_bc :
(bcnt == 9) ? (data == 8'hff) & mac_sa_bc :
(bcnt == 10) ? (data == 8'hff) & mac_sa_bc :
(bcnt == 11) ? (data == 8'hff) & mac_sa_bc : mac_sa_bc;
 
mac_sa_mc <= (bcnt == 6) ? (data[7] == 1'b1) : mac_sa_mc & !mac_sa_bc;
 
mac_sa_match <= (bcnt == 6) ? (cfg_mac_sa[7:0] == data) :
(bcnt == 7) ? (cfg_mac_sa[15:8] == data) & mac_sa_match :
(bcnt == 8) ? (cfg_mac_sa[23:16] == data) & mac_sa_match :
(bcnt == 9) ? (cfg_mac_sa[31:24] == data) & mac_sa_match :
(bcnt == 10) ? (cfg_mac_sa[39:32] == data) & mac_sa_match :
(bcnt == 11) ? (cfg_mac_sa[47:40] == data) & mac_sa_match :
mac_sa_match;
 
// L3 Protocol Analysis
ipv4f <= (bcnt == 12) ? (data == 8'h08) :
(bcnt == 13) ? (data == 8'h00) & ipv4f : ipv4f;
 
arpf <= (bcnt == 12) ? (data == 8'h08) :
(bcnt == 13) ? (data == 8'h06) & arpf : arpf;
// L4 Protocol Analysis
tcpf <= (bcnt == 23) ? (data == 8'h06) & ipv4f: tcpf;
udpf <= (bcnt == 23) ? (data == 8'h11) & ipv4f: udpf;
// IP DA and SA Match
ip_sa_match <= (bcnt == 26) ? (data == cfg_ip_sa[7:0]) & ipv4f:
(bcnt == 27) ? (data == cfg_ip_sa[15:8]) & ipv4f & ip_sa_match:
(bcnt == 28) ? (data == cfg_ip_sa[23:16]) & ipv4f & ip_sa_match:
(bcnt == 29) ? (data == cfg_ip_sa[31:24]) & ipv4f & ip_sa_match:
ip_sa_match;
ip_da_match <= (bcnt == 26) ? (data == cfg_ip_sa[7:0]) & ipv4f:
(bcnt == 27) ? (data == cfg_ip_sa[15:8]) & ipv4f & ip_da_match:
(bcnt == 28) ? (data == cfg_ip_sa[23:16]) & ipv4f & ip_da_match:
(bcnt == 29) ? (data == cfg_ip_sa[31:24]) & ipv4f & ip_da_match:
ip_da_match;
 
end else begin // on EOP
 
if(&mac_da_match) begin
pkt_status[1:0] <= 2'b11; // Local DA
end else if(mac_da_bc) begin
pkt_status[1:0] <= 2'b00; // Broadcast frame
end else if(mac_da_mc) begin
pkt_status[1:0] <= 2'b01; // Multicase frame
end else
pkt_status[1:0] <= 2'b10; // Unknown Unicast frame
 
if(&mac_sa_match) begin
pkt_status[3:2] <= 2'b11; // Local DA
end else if(mac_sa_bc) begin
pkt_status[3:2] <= 2'b00; // Broadcast frame
end else if(mac_sa_mc) begin
pkt_status[3:2] <= 2'b01; // Multicast frame
end else
pkt_status[3:2] <= 2'b10; // Unknown Unicast frame
 
if(tcpf) begin
pkt_status[6:4] <= 3'b010; // IP4 Frame + TCP
end else if(udpf) begin
pkt_status[6:4] <= 3'b011; // IP4 Frame + UDP
end else if(arpf) begin
pkt_status[6:4] <= 3'b101; // ARP frame
end else
pkt_status[6:4] <= 2'b00; // UnKnown Ethernet frame
 
mac_da_match <= 0;
mac_sa_match <= 0;
mac_sa_bc <= 0;
mac_sa_mc <= 0;
mac_da_bc <= 0;
mac_da_mc <= 0;
end
end
end
end
 
 
endmodule

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