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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /turbo8051/trunk/verif/run
    from Rev 74 to Rev 76
    ↔ Reverse comparison
  •

Rev 74 → Rev 76

/compile.modelsim
15,12 → 15,7
+incdir+../lib \
+incdir+../testcase \
+incdir+../tb \
-v ../../rtl/lib/registers.v \
-v ../../rtl/lib/stat_counter.v \
-v ../../rtl/lib/toggle_sync.v \
-v ../../rtl/lib/double_sync_low.v \
-v ../../rtl/lib/async_fifo.v \
./time_scale.v \
time_scale.v \
../tb/tb_top.v \
../../verif/agents/ethernet/tb_eth_top.v \
../../verif/agents/ethernet/tb_mii.v \
33,7 → 28,7
../../verif/agents/spi/st_m25p20a/M25P20.v \
../../verif/model/oc8051_xram.v \
../../verif/model/oc8051_xrom.v \
../../rtl/core/core.v \
../../rtl/core/digital_core.v \
../../rtl/gmac/top/g_mac_top.v \
../../rtl/gmac/mac/dble_reg.v \
../../rtl/gmac/mac/g_tx_fsm.v \
50,7 → 45,6
../../rtl/gmac/ctrl/eth_parser.v \
../../rtl/gmac/crc32/g_rx_crc32.v \
../../rtl/gmac/crc32/g_tx_crc32.v \
../../rtl/lib/async_fifo.v \
../../rtl/lib/g_dpath_ctrl.v \
../../rtl/spi/spi_core.v \
../../rtl/spi/spi_ctl.v \
88,4 → 82,9
../../rtl/8051/oc8051_tc.v \
../../rtl/8051/oc8051_tc2.v \
../../rtl/8051/oc8051_sfr.v \
../../rtl/8051/oc8051_ram_256x8_two_bist.v
../../rtl/8051/oc8051_ram_256x8_two_bist.v \
-v ../../rtl/lib/registers.v \
-v ../../rtl/lib/stat_counter.v \
-v ../../rtl/lib/toggle_sync.v \
-v ../../rtl/lib/double_sync_low.v \
-v ../../rtl/lib/async_fifo.v
/cov_options.ccf
0,0 → 1,12
# cov_options.ccf
select_coverage -bet -instance tb_top.u_core.*
select_coverage -bet -instance tb_top.u_core.*.*
select_coverage -bet -instance tb_top.u_core.*.*.*
select_coverage -bet -instance tb_top.u_core.*.*.*.*
select_coverage -bet -instance tb_top.u_core.*.*.*.*.*
#deselect_coverage -be -module fred
#deselect_coverage -be -instance TbChipTop.mon_adpll
#deselect_coverage -be -instance TbChipTop.mon_rx
#deselect_coverage -be -instance TbChipTop.T_RegIf
#deselect_coverage -be -instance TbChipTop.U_Baseband_Intf
#
/filelist_rtl.f
1,107 → 1,65
 
$TURBO8051_PROJ/rtl/core/core.v
//----------------------------------
// GMAC File List
//---------------------------------
$TURBO8051_PROJ/rtl/gmac/top/g_mac_top.v
$TURBO8051_PROJ/rtl/gmac/mac/dble_reg.v
$TURBO8051_PROJ/rtl/gmac/mac/g_tx_fsm.v
$TURBO8051_PROJ/rtl/gmac/mac/g_deferral.v
$TURBO8051_PROJ/rtl/gmac/mac/g_tx_top.v
$TURBO8051_PROJ/rtl/gmac/mac/g_rx_fsm.v
$TURBO8051_PROJ/rtl/gmac/mac/g_cfg_mgmt.v
$TURBO8051_PROJ/rtl/gmac/mac/s2f_sync.v
$TURBO8051_PROJ/rtl/gmac/mac/g_md_intf.v
$TURBO8051_PROJ/rtl/gmac/mac/g_deferral_rx.v
$TURBO8051_PROJ/rtl/gmac/mac/g_rx_top.v
$TURBO8051_PROJ/rtl/gmac/mac/g_mii_intf.v
$TURBO8051_PROJ/rtl/gmac/mac/g_mac_core.v
$TURBO8051_PROJ/rtl/gmac/ctrl/eth_parser.v
$TURBO8051_PROJ/rtl/gmac/crc32/g_rx_crc32.v
$TURBO8051_PROJ/rtl/gmac/crc32/g_tx_crc32.v
$TURBO8051_PROJ/rtl/lib/async_fifo.v
$TURBO8051_PROJ/rtl/lib/g_dpath_ctrl.v
 
//-------------------------------------
// SPI File List
//-------------------------------------
$TURBO8051_PROJ/rtl/spi/spi_core.v
$TURBO8051_PROJ/rtl/spi/spi_ctl.v
$TURBO8051_PROJ/rtl/spi/spi_if.v
$TURBO8051_PROJ/rtl/spi/spi_cfg.v
 
//-------------------------------------
// UART File List
//-------------------------------------
$TURBO8051_PROJ/rtl/uart/uart_rxfsm.v
$TURBO8051_PROJ/rtl/uart/uart_txfsm.v
$TURBO8051_PROJ/rtl/uart/uart_core.v
$TURBO8051_PROJ/rtl/uart/uart_cfg.v
 
 
//-------------------------------------
// clkgen File List
//-------------------------------------
$TURBO8051_PROJ/rtl/clkgen/clkgen.v
$TURBO8051_PROJ/rtl/lib/clk_ctl.v
 
//------------------------------------
// Core Level Files
//-----------------------------------
$TURBO8051_PROJ/rtl/lib/wb_crossbar.v
$TURBO8051_PROJ/rtl/lib/wb_rd_mem2mem.v
$TURBO8051_PROJ/rtl/lib/wb_wr_mem2mem.v
 
 
//------------------------------------
// 8051 core file list
//-----------------------------------
// Source Files
+incdir+$TURBO8051_PROJ/rtl/8051/
$TURBO8051_PROJ/rtl/8051/oc8051_top.v
$TURBO8051_PROJ/rtl/8051/oc8051_alu_src_sel.v
$TURBO8051_PROJ/rtl/8051/oc8051_alu.v
$TURBO8051_PROJ/rtl/8051/oc8051_decoder.v
$TURBO8051_PROJ/rtl/8051/oc8051_divide.v
$TURBO8051_PROJ/rtl/8051/oc8051_multiply.v
$TURBO8051_PROJ/rtl/8051/oc8051_memory_interface.v
$TURBO8051_PROJ/rtl/8051/oc8051_ram_top.v
$TURBO8051_PROJ/rtl/8051/oc8051_acc.v
$TURBO8051_PROJ/rtl/8051/oc8051_comp.v
$TURBO8051_PROJ/rtl/8051/oc8051_sp.v
$TURBO8051_PROJ/rtl/8051/oc8051_dptr.v
$TURBO8051_PROJ/rtl/8051/oc8051_cy_select.v
$TURBO8051_PROJ/rtl/8051/oc8051_psw.v
$TURBO8051_PROJ/rtl/8051/oc8051_indi_addr.v
$TURBO8051_PROJ/rtl/8051/oc8051_ports.v
$TURBO8051_PROJ/rtl/8051/oc8051_b_register.v
$TURBO8051_PROJ/rtl/8051/oc8051_uart.v
$TURBO8051_PROJ/rtl/8051/oc8051_int.v
$TURBO8051_PROJ/rtl/8051/oc8051_tc.v
$TURBO8051_PROJ/rtl/8051/oc8051_tc2.v
$TURBO8051_PROJ/rtl/8051/oc8051_rom.v
//$TURBO8051_PROJ/rtl/8051/oc8051_icache.v
//$TURBO8051_PROJ/rtl/8051/oc8051_wb_iinterface.v
$TURBO8051_PROJ/rtl/8051/oc8051_sfr.v
$TURBO8051_PROJ/rtl/8051/oc8051_ram_256x8_two_bist.v
//$TURBO8051_PROJ/rtl/8051/oc8051_ram_64x32_dual_bist.v
 
//-------------------------------------
// Altera Library
//------------------------------------
$TURBO8051_PROJ/models/altera/altera_stargate_pll.v
-v /tools/altera/altera9.0/quartus/eda/sim_lib/altera_mf.v
 
 
//-------------------------------------
// Common Lib
//-------------------------------------
 
-v $TURBO8051_PROJ/rtl/lib/registers.v
-v $TURBO8051_PROJ/rtl/lib/stat_counter.v
-v $TURBO8051_PROJ/rtl/lib/toggle_sync.v
-v $TURBO8051_PROJ/rtl/lib/double_sync_low.v
-v $TURBO8051_PROJ/rtl/lib/async_fifo.v
 
//+lint=all
+v2k
+incdir+../defs \
+incdir+../../rtl/defs \
+incdir+../../rtl/8051 \
+incdir+../lib \
-v ../../rtl/lib/registers.v \
-v ../../rtl/lib/stat_counter.v \
-v ../../rtl/lib/toggle_sync.v \
-v ../../rtl/lib/double_sync_low.v \
-v ../../rtl/lib/async_fifo.v \
../../rtl/core/digital_core.v \
../../rtl/gmac/top/g_mac_top.v \
../../rtl/gmac/mac/dble_reg.v \
../../rtl/gmac/mac/g_tx_fsm.v \
../../rtl/gmac/mac/g_deferral.v \
../../rtl/gmac/mac/g_tx_top.v \
../../rtl/gmac/mac/g_rx_fsm.v \
../../rtl/gmac/mac/g_cfg_mgmt.v \
../../rtl/gmac/mac/s2f_sync.v \
../../rtl/gmac/mac/g_md_intf.v \
../../rtl/gmac/mac/g_deferral_rx.v \
../../rtl/gmac/mac/g_rx_top.v \
../../rtl/gmac/mac/g_mii_intf.v \
../../rtl/gmac/mac/g_mac_core.v \
../../rtl/gmac/ctrl/eth_parser.v \
../../rtl/gmac/crc32/g_rx_crc32.v \
../../rtl/gmac/crc32/g_tx_crc32.v \
../../rtl/lib/async_fifo.v \
../../rtl/lib/g_dpath_ctrl.v \
../../rtl/spi/spi_core.v \
../../rtl/spi/spi_ctl.v \
../../rtl/spi/spi_if.v \
../../rtl/spi/spi_cfg.v \
../../rtl/uart/uart_rxfsm.v \
../../rtl/uart/uart_txfsm.v \
../../rtl/uart/uart_core.v \
../../rtl/uart/uart_cfg.v \
../../rtl/clkgen/clkgen.v \
../../rtl/lib/clk_ctl.v \
../../rtl/lib/wb_crossbar.v \
../../rtl/lib/wb_rd_mem2mem.v \
../../rtl/lib/wb_wr_mem2mem.v \
../../rtl/8051/oc8051_top.v \
../../rtl/8051/oc8051_rom.v \
../../rtl/8051/oc8051_alu_src_sel.v \
../../rtl/8051/oc8051_alu.v \
../../rtl/8051/oc8051_decoder.v \
../../rtl/8051/oc8051_divide.v \
../../rtl/8051/oc8051_multiply.v \
../../rtl/8051/oc8051_memory_interface.v \
../../rtl/8051/oc8051_ram_top.v \
../../rtl/8051/oc8051_acc.v \
../../rtl/8051/oc8051_comp.v \
../../rtl/8051/oc8051_sp.v \
../../rtl/8051/oc8051_dptr.v \
../../rtl/8051/oc8051_cy_select.v \
../../rtl/8051/oc8051_psw.v \
../../rtl/8051/oc8051_indi_addr.v \
../../rtl/8051/oc8051_ports.v \
../../rtl/8051/oc8051_b_register.v \
../../rtl/8051/oc8051_uart.v \
../../rtl/8051/oc8051_int.v \
../../rtl/8051/oc8051_tc.v \
../../rtl/8051/oc8051_tc2.v \
../../rtl/8051/oc8051_sfr.v \
../../rtl/8051/oc8051_ram_256x8_two_bist.v
/filelist_tb.f
1,31 → 1,27
$TURBO8051_PROJ/verif/tb/tb_top.v
########################
# Ethernet Related TB
########################
+incdir+$TURBO8051_PROJ/verif/agents/ethernet
$TURBO8051_PROJ/verif/agents/ethernet/tb_eth_top.v
$TURBO8051_PROJ/verif/agents/ethernet/tb_mii.v
$TURBO8051_PROJ/verif/agents/ethernet/tb_rmii.v
 
##########################
# Uart Related TB
##########################
$TURBO8051_PROJ/verif/agents/uart/uart_agent.v
 
##########################
# SPI Related TB
##########################
+incdir+$TURBO8051_PROJ/verif/agents/spi
+incdir+$TURBO8051_PROJ/verif/agents/spi/st_m25p20a
$TURBO8051_PROJ/verif/agents/spi/atmel/AT45DBXXX_v2.0.3.v
$TURBO8051_PROJ/verif/agents/spi/st_m25p20a/acdc_check.v
$TURBO8051_PROJ/verif/agents/spi/st_m25p20a/internal_logic.v
$TURBO8051_PROJ/verif/agents/spi/st_m25p20a/memory_access.v
$TURBO8051_PROJ/verif/agents/spi/st_m25p20a/M25P20.v
 
##########################
# RAM/ROM Models
##########################
$TURBO8051_PROJ/verif/model/oc8051_xram.v
$TURBO8051_PROJ/verif/model/oc8051_xrom.v
 
+incdir+../defs \
+incdir+../../rtl/defs \
+incdir+../../rtl/8051 \
+incdir+../agents/spi \
+incdir+../agents/spi/st_m25p20a \
+incdir+../agents/ethernet \
+incdir+../lib \
+incdir+../testcase \
+incdir+../tb \
-v ../../rtl/lib/registers.v \
-v ../../rtl/lib/stat_counter.v \
-v ../../rtl/lib/toggle_sync.v \
-v ../../rtl/lib/double_sync_low.v \
-v ../../rtl/lib/async_fifo.v \
./time_scale.v \
../tb/tb_top.v \
../../verif/agents/ethernet/tb_eth_top.v \
../../verif/agents/ethernet/tb_mii.v \
../../verif/agents/ethernet/tb_rmii.v \
../../verif/agents/uart/uart_agent.v \
../../verif/agents/spi/atmel/AT45DBXXX_v2.0.3.v \
../../verif/agents/spi/st_m25p20a/acdc_check.v \
../../verif/agents/spi/st_m25p20a/internal_logic.v \
../../verif/agents/spi/st_m25p20a/memory_access.v \
../../verif/agents/spi/st_m25p20a/M25P20.v \
../../verif/model/oc8051_xram.v \
../../verif/model/oc8051_xrom.v
/run_vlog
2,21 → 2,34
#
# test all programs with ethernet controler
#
 
set COV = "1"
set failedi = 0;
set failedx = 0;
set all_testsi = 0;
set all_testsx = 0;
 
set internal_tests=(gmac_test_1 uart_test_1 spi_test_1)
set internal_tests=(uart_test_1)
 
set external_tests=(gmac_test_1 uart_test_1 spi_test_1)
 
echo " Compiling with VCS "
echo " Compiling with cadence tools - irun "
 
ncxlmode -sverilog -I -notice +libext+.v +systemverilogext+.sv -full64 -P /tools/novas/Novas-200704/share/PLI/vcsd2006.06/LINUX64/vcsd.tab /tools/novas/Novas-200704/share/PLI/vcsd2006.06/LINUX64/pli.a +define+SFLASH_SPDUP -f filelist_top.f -l ../log/complie.log
if (${COV} == 0) then
set VERILOG = "irun -64bit -sv -elaborate +access+rcw +nospecify +define+SFLASH_SDPUP -V93 -define S75"
set ELAB = "irun -64bit -R +access+rcw"
echo " Compiling with IES without coverage"
else
set VERILOG = "irun -64bit -sv -elaborate +access+rcw +define+SFLASH_SDPUP +nospecify -V93 -define S75 -covfile cov_options.ccf -covoverwrite"
set ELAB = "irun -64bit -R +access+rcw -covfile cov_options.ccf -covoverwrite"
echo " Compiling with IES with coverage"
 
endif
 
 
$VERILOG -f filelist_top.f -l ../log/complie.log
 
 
if ($status != 0) then
echo "#### Compile : FAILED"
echo ""
39,7 → 52,7
#echo ""
#echo "### Running test ${i}: ${internal_test}"
 
simv +DUMP +${internal_test} > ../log/run.log
$ELAB +DUMP +${internal_test} -l ../log/run.log
if ($status != 0) then
cat ../log/run.log
exit
/time_scale.v
1,2 → 1,7
 
`timescale 1ns/1ps

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