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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /turbo8051/trunk/verif/testcase
    from Rev 63 to Rev 74
    ↔ Reverse comparison
  •

Rev 63 → Rev 74

/spi_test1.v
4,8 → 4,8
 
 
task spi_test1;
begin
 
 
$display("############################################");
$display(" Testing ST Flash Read/Write Access ");
$display("############################################");
28,4 → 28,5
 
 
tb_top.spi_tb_status(); // SPI Tb Init
end
endtask
/uart_test1.v
1,50 → 1,60
task uart_test1;
 
reg [1:0] data_bit = 2'b11;
reg stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
reg stick_parity = 0; // 1: force even parity
reg parity_en = 1; // parity enable
reg even_odd_parity = 1; // 0: odd parity; 1: even parity
reg [1:0] data_bit ;
reg stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
reg stick_parity ; // 1: force even parity
reg parity_en ; // parity enable
reg even_odd_parity ; // 0: odd parity; 1: even parity
 
reg [7:0] data;
reg [15:0] divisor = 3; // divided by n * 16
reg [15:0] timeout = 500;// wait time limit
reg [15:0] divisor ; // divided by n * 16
reg [15:0] timeout ;// wait time limit
 
reg [15:0] rx_nu;
reg [15:0] tx_nu;
reg [7:0] write_data [0:39];
reg fifo_enable = 0; // fifo mode disable
reg fifo_enable ; // fifo mode disable
integer i,j;
begin
data_bit = 2'b11;
stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
stick_parity = 0; // 1: force even parity
parity_en = 1; // parity enable
even_odd_parity = 1; // 0: odd parity; 1: even parity
divisor = 3; // divided by n * 16
timeout = 500;// wait time limit
fifo_enable = 0; // fifo mode disable
 
tb_uart.uart_init;
tb_top.cpu_write('h3,8'h0,{27'h0,2'b10,1'b1,1'b1,1'b1});
 
 
for (i=0; i<40; i=i+1)
write_data[i] = $random;
 
 
tb_top.tb_uart.control_setup (data_bit, stop_bits, parity_en, even_odd_parity, stick_parity, timeout, divisor, fifo_enable);
 
 
fork
begin
for (i=0; i<40; i=i+1)
tb_uart.uart_init;
tb_top.cpu_write('h3,8'h0,{27'h0,2'b10,1'b1,1'b1,1'b1});
for (i=0; i<40; i=i+1)
write_data[i] = $random;
tb_top.tb_uart.control_setup (data_bit, stop_bits, parity_en, even_odd_parity, stick_parity, timeout, divisor, fifo_enable);
fork
begin
$display ("\n... Writing char %d ...", write_data[i]);
tb_top.tb_uart.write_char (write_data[i]);
for (i=0; i<40; i=i+1)
begin
$display ("\n... Writing char %d ...", write_data[i]);
tb_top.tb_uart.write_char (write_data[i]);
end
end
end
 
begin
for (j=0; j<40; j=j+1)
begin
tb_top.tb_uart.read_char_chk(write_data[j]);
for (j=0; j<40; j=j+1)
begin
tb_top.tb_uart.read_char_chk(write_data[j]);
end
end
end
join
 
#100
tb_top.tb_uart.report_status(rx_nu, tx_nu);
 
join
#100
tb_top.tb_uart.report_status(rx_nu, tx_nu);
end
endtask
/webserver.v
6,7 → 6,7
reg [7:0] iFrmCnt;
 
reg [31:0] outfile;
 
begin
//--------------------------
// Data Memory MAP
//-------------------------
115,6 → 115,6
if(`TB_AGENTS_GMAC.full_mii.receive_crc_err_count)
`TB_GLBL.test_err;
 
 
end
endtask
 
/gmac_test1.v
5,6 → 5,7
reg [9:0] desc_tx_qbase;
reg [7:0] iFrmCnt;
 
begin
//--------------------------
// Data Memory MAP
//-------------------------
76,6 → 77,6
if(`TB_AGENTS_GMAC.full_mii.receive_crc_err_count)
`TB_GLBL.test_err;
 
 
end
endtask
 
/gmac_test2.v
5,6 → 5,7
reg [9:0] desc_tx_qbase;
reg [7:0] iFrmCnt;
 
begin
//--------------------------
// Data Memory MAP
//-------------------------
73,6 → 74,6
if(`TB_AGENTS_GMAC.full_mii.receive_crc_err_count)
`TB_GLBL.test_err;
 
 
end
endtask
 

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