URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/turbo8051/trunk/verif
- from Rev 58 to Rev 59
- ↔ Reverse comparison
Rev 58 → Rev 59
/run/compile.modelsim
0,0 → 1,81
#!/bin/csh |
|
if(! -e work) then |
vlib work |
endif |
|
vlog -work work +define+SFLASH_SPDUP \ |
-v ../../rtl/lib/registers.v \ |
-v ../../rtl/lib/stat_counter.v \ |
-v ../../rtl/lib/toggle_sync.v \ |
-v ../../rtl/lib/double_sync_low.v \ |
-v ../../rtl/lib/async_fifo.v \ |
./time_scale.v \ |
../tb/tb_top.v \ |
../../verif/agents/ethernet/tb_eth_top.v \ |
../../verif/agents/ethernet/tb_mii.v \ |
../../verif/agents/ethernet/tb_rmii.v \ |
../../verif/agents/uart/uart_agent.v \ |
../../verif/agents/spi/atmel/AT45DBXXX_v2.0.3.v \ |
../../verif/agents/spi/st_m25p20a/acdc_check.v \ |
../../verif/agents/spi/st_m25p20a/internal_logic.v \ |
../../verif/agents/spi/st_m25p20a/memory_access.v \ |
../../verif/agents/spi/st_m25p20a/M25P20.v \ |
../../verif/model/oc8051_xram.v \ |
../../verif/model/oc8051_xrom.v \ |
../../rtl/core/core.v \ |
../../rtl/gmac/top/g_mac_top.v \ |
../../rtl/gmac/mac/dble_reg.v \ |
../../rtl/gmac/mac/g_tx_fsm.v \ |
../../rtl/gmac/mac/g_deferral.v \ |
../../rtl/gmac/mac/g_tx_top.v \ |
../../rtl/gmac/mac/g_rx_fsm.v \ |
../../rtl/gmac/mac/g_cfg_mgmt.v \ |
../../rtl/gmac/mac/s2f_sync.v \ |
../../rtl/gmac/mac/g_md_intf.v \ |
../../rtl/gmac/mac/g_deferral_rx.v \ |
../../rtl/gmac/mac/g_rx_top.v \ |
../../rtl/gmac/mac/g_mii_intf.v \ |
../../rtl/gmac/mac/g_mac_core.v \ |
../../rtl/gmac/ctrl/eth_parser.v \ |
../../rtl/gmac/crc32/g_rx_crc32.v \ |
../../rtl/gmac/crc32/g_tx_crc32.v \ |
../../rtl/lib/async_fifo.v \ |
../../rtl/lib/g_dpath_ctrl.v \ |
../../rtl/spi/spi_core.v \ |
../../rtl/spi/spi_ctl.v \ |
../../rtl/spi/spi_if.v \ |
../../rtl/spi/spi_cfg.v \ |
../../rtl/uart/uart_rxfsm.v \ |
../../rtl/uart/uart_txfsm.v \ |
../../rtl/uart/uart_core.v \ |
../../rtl/uart/uart_cfg.v \ |
../../rtl/clkgen/clkgen.v \ |
../../rtl/lib/clk_ctl.v \ |
../../rtl/lib/wb_crossbar.v \ |
../../rtl/lib/wb_rd_mem2mem.v \ |
../../rtl/lib/wb_wr_mem2mem.v \ |
../../rtl/8051/oc8051_top.v \ |
../../rtl/8051/oc8051_rom.v \ |
../../rtl/8051/oc8051_alu_src_sel.v \ |
../../rtl/8051/oc8051_alu.v \ |
../../rtl/8051/oc8051_decoder.v \ |
../../rtl/8051/oc8051_divide.v \ |
../../rtl/8051/oc8051_multiply.v \ |
../../rtl/8051/oc8051_memory_interface.v \ |
../../rtl/8051/oc8051_ram_top.v \ |
../../rtl/8051/oc8051_acc.v \ |
../../rtl/8051/oc8051_comp.v \ |
../../rtl/8051/oc8051_sp.v \ |
../../rtl/8051/oc8051_dptr.v \ |
../../rtl/8051/oc8051_cy_select.v \ |
../../rtl/8051/oc8051_psw.v \ |
../../rtl/8051/oc8051_indi_addr.v \ |
../../rtl/8051/oc8051_ports.v \ |
../../rtl/8051/oc8051_b_register.v \ |
../../rtl/8051/oc8051_uart.v \ |
../../rtl/8051/oc8051_int.v \ |
../../rtl/8051/oc8051_tc.v \ |
../../rtl/8051/oc8051_tc2.v \ |
../../rtl/8051/oc8051_sfr.v \ |
../../rtl/8051/oc8051_ram_256x8_two_bist.v |
run/compile.modelsim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run/run_modelsim
===================================================================
--- run/run_modelsim (nonexistent)
+++ run/run_modelsim (revision 59)
@@ -0,0 +1,147 @@
+#!/bin/csh -f
+#
+# test all programs with ethernet controler
+#
+
+set failedm = 0;
+set failedi = 0;
+set failedx = 0;
+set all_testsm = 0;
+set all_testsi = 0;
+set all_testsx = 0;
+
+set misc_tests=(gmac_test_2 gmac_test_1 uart_test_1 spi_test_1)
+#set misc_tests=( )
+
+set risc_ext_tests=(fib divmul sort gcd cast xram)
+
+set risc_int_tests=(fib divmul sort gcd cast xram)
+
+echo " Compiling with VCS "
+
+./compile.modelsim | tee ../log/complie.log
+
+
+if ($status != 0) then
+ echo "#### Compile : FAILED"
+ echo ""
+ cat ../log/complie.log
+ exit
+else
+ echo "#### Compile : PASSED"
+endif
+
+
+echo ""
+echo "###########################################"
+echo " Runing GMAC/SPI/UART test programs "
+echo "###########################################"
+
+set i = 0;
+ echo "###########################################"
+foreach misc_test ($misc_tests)
+ @ i += 1;
+ #echo ""
+ echo "### Running test ${i}: ${misc_test}"
+
+ vsim -do run.do -c tb_top +${misc_test} | tee ../log/run.log
+ if ($status != 0) then
+ cat ../log/run.log
+ exit
+ else if (`tail ../log/run.log | grep PASSED` == "") then
+ echo "### test ${i}: ${misc_test} --> FAILED"
+ @ failedm += 1;
+ @ all_testsm += 1;
+ else
+ echo "### test ${i}: ${misc_test} --> PASSED"
+ @ all_testsm += 1;
+ endif
+
+ mv ../log/run.log ../log/${misc_test}.log
+
+
+end
+ echo "###########################################"
+
+
+set i = 0;
+echo ""
+echo "###########################################"
+echo "### Test Logs "
+foreach misc_test ($misc_tests)
+ @ i += 1;
+ echo " test ${i}: ../log/${misc_test}.log"
+
+end
+ echo "###########################################"
+
+echo ""
+echo ""
+echo "###########################################"
+echo "### tesing 8051 programs from external rom"
+echo "###########################################"
+
+set i = 0;
+ echo "###########################################"
+foreach risc_ext_test ($risc_ext_tests)
+ @ i += 1;
+ #echo ""
+
+ \cp ../testcase/dat/${risc_ext_test}.dat ./dat/oc8051_xrom.in
+ vsim -do run.do -c tb_top +EXTERNAL_ROM | tee ../log/run.log
+ if ($status != 0) then
+ cat ../log/run.log
+ exit
+ else if (`tail ../log/run.log | grep Passed` == "") then
+ echo "### test ${i}: ${risc_ext_test} --> FAILED"
+ @ failedx += 1;
+ @ all_testsx += 1;
+ else
+ echo "### test ${i}: ${risc_ext_test} --> PASSED"
+ @ all_testsx += 1;
+ endif
+ mv ../log/run.log ../log/x_${risc_ext_test}.log
+
+end
+ echo "###########################################"
+
+
+echo ""
+echo ""
+echo "###########################################"
+echo "### tesing 8051 programs from internal rom"
+echo "###########################################"
+
+set i = 0;
+ echo "###########################################"
+foreach risc_int_test ($risc_int_tests)
+ @ i += 1;
+ #echo ""
+
+ \cp ../testcase/dat/${risc_int_test}.dat ./dat/oc8051_xrom.in
+ vsim -do run.do -c tb_top +INTERNAL_ROM | tee ../log/run.log
+ if ($status != 0) then
+ cat ../log/run.log
+ exit
+ else if (`tail ../log/run.log | grep Passed` == "") then
+ echo "### test ${i}: ${risc_int_test} --> FAILED"
+ @ failedi += 1;
+ @ all_testsi += 1;
+ else
+ echo "### test ${i}: ${risc_int_test} --> PASSED"
+ @ all_testsi += 1;
+ endif
+ mv ../log/run.log ../log/x_${risc_int_test}.log
+
+end
+ echo "###########################################"
+
+echo ""
+echo "###########################################"
+echo "### Test Summary "
+echo "### "
+echo "### Failed $failedm of $all_testsm misc tests"
+echo "### Failed $failedx of $all_testsx external rom tests"
+echo "### Failed $failedi of $all_testsi internal rom tests"
+echo "###########################################"
+
run/run_modelsim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property