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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

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    /turbo8051/trunk
    from Rev 36 to Rev 37
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  •

Rev 36 → Rev 37

/rtl/gmac/mac/filelist_mac.f
6,7 → 6,6
g_cfg_mgmt.v
s2f_sync.v
g_md_intf.v
g_ad_fltr.v
g_deferral_rx.v
g_rx_top.v
g_mii_intf.v
/rtl/gmac/mac/g_mac_core.v
50,9 → 50,6
app_reset_n,
 
app_clk,
app_send_pause_i,
app_send_pause_active_o,
app_send_jam_i,
 
// Reg Bus Interface Signal
reg_cs,
127,9 → 124,6
// Application Clock Related Declaration
//-----------------------------------------------------------------------
input app_clk;
input app_send_pause_i;
output app_send_pause_active_o;
input app_send_jam_i;
 
// Conntrol Bus Sync with Application Clock
//---------------------------------
251,8 → 245,6
.rx_commit_wr (rx_commit_wr_o),
.commit_write_done (rx_commit_write_done_o),
.rx_rewind_wr (rx_rewind_wr_o),
//transistor interface
.rx2tx_pause_tx (rx2tx_pause_o),
//mii interface
.phy_rx_clk (phy_rx_clk),
.mi2rx_strt_rcv (mi2rx_strt_rcv),
271,17 → 263,12
.cf2rx_rx_ch_en (cf2rx_ch_en),
.cf2rx_strp_pad_en (cf2rx_strp_pad_en),
.cf2rx_snd_crc (cf2rx_snd_crc),
.cf2rx_pause_en (cf2rx_pause_en),
.cf2rx_rcv_runt_pkt_en (cf2rx_runt_pkt_en),
.cf_macmode (cf_mac_mode_o),
.cf2df_dfl_single_rx (cf2df_dfl_single_rx),
.ap2rx_rx_fifo_err (rx_fifo_error_i),
//A200 change Port added for crs based flow control
.phy_crs (phy_crs),
//A200 change crs flow control enable signal
.crs_flow_control_enable (cfg_crs_flow_ctrl_enb_i),
//A200 change pause detected pulse for counter
.pause_frame_detected ()
.phy_crs (phy_crs)
);
wire [4:0] cf2md_regad,cf2md_phyad;
382,14 → 369,11
 
wire [7:0] cf2df_dfl_single;
wire [47:0] cf_mac_sa;
wire [15:0] cf2tx_pause_quanta;
wire cf2tx_force_bad_fcs;
wire cf2tx_tstate_mode;
wire set_fifo_undrn;
g_tx_top U_tx_top (
.app_clk (app_clk) ,
.send_pause_active (app_send_pause_active_o),
.set_fifo_undrn (tx_set_fifo_undrn_o),
//Outputs
414,14 → 398,8
.phy_tx_en (phy_tx_en),
.phy_tx_er (phy_tx_er),
//application
.app_send_pause (app_send_pause_i),
//rx_top
.rx2tx_pause (rx2tx_pause_o),
//configuration
.cf2tx_tstate_mode (cf2tx_tstate_mode),
.cf2tx_ch_en (cf2tx_ch_en),
.cf2df_dfl_single (cf2df_dfl_single),
.cf2tx_pad_enable (cf2tx_pad_enable),
428,7 → 406,6
.cf2tx_append_fcs (cf2tx_append_fcs),
.cf_mac_mode (cf_mac_mode_o),
.cf_mac_sa (cf_mac_sa),
.cf2tx_pause_quanta (cf2tx_pause_quanta),
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
//FIFO data
517,10 → 494,8
 
// Config In
.cfg_uni_mac_mode_change_i (cfg_uni_mac_mode_change_i),
.cfg_crs_flow_ctrl_enb_i (cfg_crs_flow_ctrl_enb_i),
 
//CHANNEL enable
.cf2tx_tstate_mode (cf2tx_tstate_mode),
.cf2tx_ch_en (cf2tx_ch_en),
//CHANNEL CONTROL TX
.cf2df_dfl_single (cf2df_dfl_single),
532,14 → 507,10
.cf2rx_ch_en (cf2rx_ch_en),
.cf2rx_strp_pad_en (cf2rx_strp_pad_en),
.cf2rx_snd_crc (cf2rx_snd_crc),
.cf2rx_pause_en (cf2rx_pause_en),
.cf2rx_addrchk_en (),
.cf2rx_runt_pkt_en (cf2rx_runt_pkt_en),
.cf2af_broadcast_disable (cf2af_broadcast_disable),
.cf_mac_sa (cf_mac_sa),
.cfg_ip_sa (cfg_ip_sa),
.cfg_mac_filter (cfg_mac_filter),
.cf2tx_pause_quanta (cf2tx_pause_quanta),
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
//MDIO CONTROL & DATA
.cf2md_datain (cf2md_datain),
589,7 → 560,6
// Signal from Application to transmit JAM
.df2rx_dfl_dn (df2rx_dfl_dn),
.app_send_jam (app_send_jam_i),
// Inputs from Transmit FSM
.tx2mi_strt_preamble (tx2mi_strt_preamble),
/rtl/gmac/mac/g_ad_fltr.v File deleted
/rtl/gmac/mac/g_rx_top.v
64,7 → 64,6
rx_commit_wr,
commit_write_done,
rx_rewind_wr,
rx2tx_pause_tx,
mi2rx_strt_rcv,
mi2rx_rcv_vld,
mi2rx_rx_byte,
77,7 → 76,6
cf2rx_rx_ch_en,
cf2rx_strp_pad_en,
cf2rx_snd_crc,
cf2rx_pause_en,
cf2df_dfl_single_rx,
cf2rx_rcv_runt_pkt_en,
cf_macmode,
85,11 → 83,7
df2rx_dfl_dn,
ap2rx_rx_fifo_err,
//A200 change Port added for crs based flow control
phy_crs,
//A200 change crs flow control enable signal
crs_flow_control_enable,
//A200 change pause detected pulse for counter
pause_frame_detected
phy_crs
);
 
input app_reset_n;
115,7 → 109,6
output rx_commit_wr;
output commit_write_done;
output rx_rewind_wr;
output rx2tx_pause_tx;
input mi2rx_strt_rcv;
input mi2rx_rcv_vld;
input [7:0] mi2rx_rx_byte;
128,7 → 121,6
input cf2rx_rx_ch_en;
input cf2rx_strp_pad_en;
input cf2rx_snd_crc;
input cf2rx_pause_en;
input cf2rx_rcv_runt_pkt_en;
input cf_macmode;
input [7:0] cf2df_dfl_single_rx;
138,11 → 130,7
 
//A200 change Port added for crs based flow control
input phy_crs;
//A200 change crs flow control enable signal
input crs_flow_control_enable;
 
//A200 change pause detected pulse for counter
output pause_frame_detected;
 
 
g_rx_fsm u_rx_fsm(
164,8 → 152,6
.rx2ap_commit_write(rx_commit_wr),
.rx2ap_rewind_write(rx_rewind_wr),
// To address filtering block
// Pause control to Tx block
.rx2tx_pause_tx(rx2tx_pause_tx),
.commit_write_done(commit_write_done),
// Global Signals
185,36 → 171,17
// Signal from CRC check block
.rc2rx_crc_ok(rc2rx_crc_ok),
// Signals from Address filtering block
.af2rx_pause_frame(af2rx_pause_frame),
// Signals from Config Management Block
.cf2rx_max_pkt_sz(cf2rx_max_pkt_sz),
.cf2rx_rx_ch_en(cf2rx_rx_ch_en),
.cf2rx_strp_pad_en(cf2rx_strp_pad_en),
.cf2rx_snd_crc(cf2rx_snd_crc),
.cf2rx_pause_en(cf2rx_pause_en),
.cf2rx_rcv_runt_pkt_en(cf2rx_rcv_runt_pkt_en),
.cf2rx_gigabit_xfr(cf_macmode),
//A200 change Port added for crs based flow control
.phy_crs(phy_crs),
//A200 change crs flow control enable signal
.crs_flow_control_enable(crs_flow_control_enable),
//A200 change pause detected pulse for counter
.pause_frame_detected(pause_frame_detected)
.phy_crs(phy_crs)
);
 
g_ad_fltr u_ad_fltr(
.phy_rx_clk(phy_rx_clk),
.rx_reset_n(rx_reset_n),
.app_clk(app_clk),
.scan_mode(scan_mode),
//MII Interface
.mi2af_rcv_vld(mi2rx_rcv_vld),
.mi2af_strt_rcv(mi2rx_strt_rcv),
.mi2af_end_rcv(mi2rx_end_rcv),
.mi2af_rx_data(mi2rx_rx_byte),
//RX_FSM Interface
.af2rf_pause_frame(af2rx_pause_frame)
);
g_rx_crc32 u_rx_crc32 (
// CRC Valid signal to rx_fsm
/rtl/gmac/mac/g_tx_top.v
55,7 → 55,6
***********************************************************************/
module g_tx_top(
app_clk,
send_pause_active,
set_fifo_undrn,
81,14 → 80,8
//MII interface
phy_tx_en,
phy_tx_er,
//application
app_send_pause,
//rx_top
rx2tx_pause,
//configuration
cf2tx_tstate_mode,
cf2tx_ch_en,
cf2df_dfl_single,
cf2tx_pad_enable,
95,7 → 88,6
cf2tx_append_fcs,
cf_mac_mode,
cf_mac_sa,
cf2tx_pause_quanta,
cf2tx_force_bad_fcs,
//FIFO data
app_tx_dt_in,
111,7 → 103,6
input tx_reset_n;
input tx_clk; // Transmit clock
input app_send_pause;
input [8:0] app_tx_dt_in;
input app_tx_fifo_empty;
input app_tx_rdy;
118,7 → 109,6
input phy_tx_en; // Transmit data Enable
input phy_tx_er; // Transmit Error
input cf2tx_tstate_mode; // OFN auth intf fix
input cf2tx_ch_en; // Transmit channel Enable
input [7:0] cf2df_dfl_single;
input cf2tx_pad_enable; // Padding Enabled
125,11 → 115,9
input cf2tx_append_fcs; // Append CRC to packets
input cf2tx_force_bad_fcs; // force bad fcs
input [47:0] cf_mac_sa; // MAC Source Address
input [15:0] cf2tx_pause_quanta; // Pause Quanta used when sending a pause frame
input cf_mac_mode; // Gigabit or 10/100
 
input rx2tx_pause;
input mi2tx_byte_ack; // Transmit byte ack from RMII
output tx_commit_read;
147,7 → 135,6
output tx_ch_en; // MANDAR
 
output send_pause_active; // condor fix
output set_fifo_undrn;// Description: At GMII Interface ,
// abug after a transmit fifo underun was found.
// The packet after a packet that
176,7 → 163,6
// Instantiate Transmit State machine block
g_tx_fsm U_tx_fsm(
.send_pause_active_out(send_pause_active), // condor fix
.app_clk(app_clk), // condor fix
.set_fifo_undrn(set_fifo_undrn), // E3C fix
 
203,19 → 189,14
.app_tx_fifo_empty(app_tx_fifo_empty),
//dfl and back off
.df2tx_dfl_dn(df2tx_dfl_dn),
.app_send_pause(app_send_pause),
//inputs from FCS
.tc2tx_fcs(tc2tx_fcs),
.cf2tx_tstate_mode(cf2tx_tstate_mode),
.cf2tx_ch_en(cf2tx_ch_en),
.cf2tx_pad_enable(cf2tx_pad_enable),
.cf2tx_append_fcs(cf2tx_append_fcs),
.cf_mac_mode(cf_mac_mode),
.cf_mac_sa(cf_mac_sa),
.cf2tx_pause_quanta(cf2tx_pause_quanta),
.cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
//RX pause frame received
.rx2tx_pause(rx2tx_pause),
//MII
.mi2tx_byte_ack(mi2tx_byte_ack),
.tx_clk(tx_clk),
/rtl/gmac/mac/g_mii_intf.v
94,7 → 94,6
cf_silent_mode,
 
// Signal from Application to transmit JAM
app_send_jam,
df2rx_dfl_dn,
 
// Inputs from Transmit FSM
152,7 → 151,6
input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
input cf_chk_rx_dfl; // Check for Deferal
input cf_silent_mode; // PHY Inactive
input app_send_jam; // Send a Jam Sequence (From the Application)
input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
// preamble on the line
179,8 → 177,6
/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
 
reg [4:0] tx_preamble_cnt_val;
reg [4:0] jam_count;
reg [4:0] jam_count_reg;
 
 
reg strt_rcv_in;
202,7 → 198,7
parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
mii_tx_jam_st = 4'd4, mii_tx_nibble_st = 4'd5,
mii_tx_nibble_st = 4'd5,
mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
mii_tx_dibit_end_st = 4'd8;
 
209,7 → 205,6
reg [3:0] mii_tx_cur_st;
reg [3:0] mii_tx_nxt_st;
wire send_jam;
wire receive_detect;
wire pre_condition;
wire sfd_condition;
223,12 → 218,9
reg tx_ext_in;
reg tx_pre_in;
reg tx_sfd_in;
reg tx_jam_in;
reg tx_xfr_ack_in;
reg inc_preamble_cntr;
reg rst_preamble_cntr;
reg inc_jam_cntr;
reg rst_jam_cntr;
reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
reg rx_dv;
reg rx_er;
308,8 → 300,8
 
always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
or jam_count or tx_xfr_cnt or send_jam or receive_detect
or receive_detect_pulse or jam_count_reg or jam_count or cfg_uni_mac_mode_change)
or tx_xfr_cnt or receive_detect
or receive_detect_pulse or cfg_uni_mac_mode_change)
begin
mii_tx_nxt_st = mii_tx_cur_st;
318,11 → 310,8
tx_sfd_in = 1'b0;
tx_err_in = 1'b0;
tx_ext_in = 1'b0;
tx_jam_in = 1'b0;
inc_preamble_cntr = 1'b0;
rst_preamble_cntr = 1'b0;
inc_jam_cntr = 1'b0;
rst_jam_cntr = 1'b0;
tx_xfr_ack_in = 1'b0;
casex(mii_tx_cur_st) // synopsys parallel_case full_case
422,24 → 411,6
end
end*/
mii_tx_jam_st:
begin
if(jam_count == jam_count_reg)
begin
tx_en_in = 1'b1;
tx_jam_in = 1'b1;
rst_jam_cntr = 1'b1;
mii_tx_nxt_st = mii_tx_idle_st;
end
else
begin
tx_en_in = 1'b1;
tx_jam_in = 1'b1;
inc_jam_cntr = 1'b1;
mii_tx_nxt_st = mii_tx_jam_st;
end
end
 
mii_tx_end_st:
// This state checks for the end of transfer
// and extend for carrier extension
590,29 → 561,17
begin
if (cf_mac_mode)
phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
8'b11010101 : ((tx_jam_in) ? 8'b11111111 :
((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte)));
8'b11010101 : ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte));
else if (!cf_mac_mode && !cf2mi_rmii_en)
phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
4'b1101 : ((tx_jam_in) ? 4'b1111 : tx_nibble_in)) ;
4'b1101 : tx_nibble_in) ;
else if (!cf_mac_mode && cf2mi_rmii_en)
phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
2'b11 : ((tx_jam_in) ? 2'b11 : tx_dibit_in)) ;
2'b11 : tx_dibit_in) ;
end
end
assign receive_detect_pulse = receive_detect && !d_receive_detect;
 
always @(posedge phy_tx_clk or negedge tx_reset_n)
begin
if(!tx_reset_n)
jam_count_reg <= 5'd0;
else if(cf_mac_mode)
jam_count_reg <= GMII_JAM_COUNT;
else if(cf2mi_rmii_en)
jam_count_reg <= RMII_JAM_COUNT;
else if(!cf2mi_rmii_en)
jam_count_reg <= MII_JAM_COUNT;
end
 
always @(posedge phy_tx_clk or negedge tx_reset_n)
begin
708,16 → 667,6
tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
end
// Jam Counter
always @(posedge phy_tx_clk or negedge tx_reset_n)
begin
if(!tx_reset_n)
jam_count <= 5'd0;
else if(rst_jam_cntr)
jam_count <= 5'd0;
else if(inc_jam_cntr)
jam_count <= jam_count + 1;
end
 
always @(posedge phy_rx_clk or negedge rx_reset_n)
1007,14 → 956,6
end
 
 
half_dup_dble_reg U_dble_reg0 (
//outputs
.sync_out_pulse(send_jam),
//inputs
.in_pulse(app_send_jam),
.dest_clk(phy_tx_clk),
.reset_n(tx_reset_n)
);
 
half_dup_dble_reg U_dble_reg1 (
//outputs
/rtl/gmac/mac/g_rx_fsm.v
72,8 → 72,6
rx2ap_commit_write,
rx2ap_rewind_write,
// To address filtering block
// Pause control to Tx block
rx2tx_pause_tx,
//commit
commit_write_done,
93,22 → 91,15
ap2rx_rx_fifo_err,
// Signal from CRC check block
rc2rx_crc_ok,
// Signals from Address filtering block
af2rx_pause_frame,
// Signals from Config Management Block
cf2rx_max_pkt_sz,
cf2rx_rx_ch_en,
cf2rx_strp_pad_en,
cf2rx_snd_crc,
cf2rx_pause_en,
cf2rx_rcv_runt_pkt_en,
cf2rx_gigabit_xfr,
//A200 change Port added for crs based flow control
phy_crs,
//A200 change crs flow control enable signal
crs_flow_control_enable,
//A200 change pause detected pulse for counter
pause_frame_detected
phy_crs
);
 
135,13 → 126,9
// in the FIFO has a error
// Ignore the packet and restart from the
// end of previous packet
output rx2tx_pause_tx; // pause frame detected pause transmit
output clr_rx_error_from_rx_fsm;
output commit_write_done;
 
output pause_frame_detected; //A200 change bringing out a pulse to count number
//pause frames received.
 
input reset_n; // reset from mac application interface
input phy_rx_clk; // Reference clock used for RX
160,8 → 147,6
input rc2rx_crc_ok; // CRC of the receiving packet is OK.
// Generated by CRC block
input af2rx_pause_frame; // Detected a pause frame
 
input [15:0] cf2rx_max_pkt_sz; // max packet size
input cf2rx_rx_ch_en; // Receive Enabled
169,7 → 154,6
input cf2rx_snd_crc; // Append CRC to the data
// ( This automatically means padding
// will be enabled)
input cf2rx_pause_en; // This is set when flow control is enabled
input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
input cf2rx_gigabit_xfr;
input mi2rx_extend;
176,8 → 160,6
 
//A200 change Port added for crs based flow control
input phy_crs;
//A200 change crs flow control enable signal
input crs_flow_control_enable;
/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
187,15 → 169,10
reg rx2ap_rx_fsm_wrt;
wire [31:0] rx_sts_dt;
reg [31:0] rx_sts;
wire rx2tx_pause_tx;
//Renamed to rx2tx_pause_tx_int as rx2tx_pause_tx is genrated in CRS
//condition also
reg rx2tx_pause_tx_int;
 
/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
reg commit_write;
reg rewind_write;
wire pause_dn;
wire look_at_length_field;
reg send_crc;
reg rcv_pad_data;
219,9 → 196,6
reg commit_write_done;
reg check_padding;
reg check_padding_in;
reg gen_pause_det;
reg pause_opcode_detected;
reg ld_pause_quanta_1,ld_pause_quanta_2;
reg [2:0] padding_len_reg;
reg [15:0] rcv_length_reg;
reg [15:0] length_counter;
228,10 → 202,6
reg [18:0] rx_fsm_cur_st;
reg [18:0] rx_fsm_nxt_st;
reg [15:0] pause_quanta;
reg [1:0] c_pause_ptr;
reg [15:0] pause_count;
reg [8:0] pause_quanta_count;
reg crc_stat_reg;
reg rx_runt_pkt_reg;
reg large_pkt_reg;
247,8 → 217,6
wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
reg lengthfield_error;
reg lengthfield_err_reg;
reg pause_frame_detected;
reg pause_seen;
reg addr_stat_chk;
reg clr_rx_error_from_rx_fsm;
266,11 → 234,7
rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
rx_fsm_updstat_st = 19'b0000000000001000000,
rx_fsm_chkval_st = 19'b0000000000010000000,
rx_fsm_pausectrl_st = 19'b0000000000100000000,
rx_fsm_extend_st = 19'b0000000100000000000,
rx_fsm_pausequanta_byte1_st = 19'b0000001000000000000,
rx_fsm_pausequanta_byte2_st = 19'b0000010000000000000,
rx_fsm_wt4_pause_end_st = 19'b0000100000000000000;
rx_fsm_extend_st = 19'b0000000100000000000;
/***************** WIRE ASSIGNMENTS *************************/
wire [6:0] dec_pad_length;
353,17 → 317,6
assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
 
 
always @(posedge phy_rx_clk or negedge reset_n) begin
if(!reset_n)
pause_opcode_detected <= 1'b0;
else
begin
if(rx_fsm_cur_st == rx_fsm_pausequanta_byte1_st)
pause_opcode_detected <= 1'b1;
else if(rx_fsm_cur_st == rx_fsm_idle_st)
pause_opcode_detected <= 1'b0;
end
end
// Following state machine is to receive nibbles from the RMII/MII
// block and packetize them to 32 bits with information of EOP and
370,16 → 323,15
// valid bytes. It also discards packets which are less than minimum
// frame size. It performs Address validity and Data validity.
always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
or cf2rx_snd_crc or cf2rx_pause_en or look_at_length_field
or cf2rx_snd_crc or look_at_length_field
or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
or inc_length_counter or rcv_length_reg or commit_write_done
or crc_count or shift_counter or bytes_to_fifo
or af2rx_pause_frame or cf2rx_rcv_runt_pkt_en
or cf2rx_rcv_runt_pkt_en
or inc_rcv_byte_count or send_runt_packet
or pause_frame_detected or rcv_byte_count or first_dword
or rcv_byte_count or first_dword
or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
//or pause_opcode_detected)
begin
rx_fsm_nxt_st = rx_fsm_cur_st;
set_tag1_flag = 1'b0;
400,18 → 352,13
gen_eop = 1'b0;
error = 1'b0;
byte_boundary= 1'b0;
gen_pause_det = 1'b0;
ld_pause_quanta_1 = 1'b0;
ld_pause_quanta_2 = 1'b0;
send_crc = 1'b0;
rcv_pad_data = 1'b0;
inc_shift_counter = 1'b0;
send_data_to_fifo = 1'b0;
lengthfield_error = 1'b0;
pause_seen = 1'b0;
addr_stat_chk = 1'b0;
clr_rx_error_from_rx_fsm = 1'b0;
//pause_opcode_detected = 1'b0;
 
 
casex(rx_fsm_cur_st) // synopsys parallel_case full_case
420,7 → 367,6
// Continues accepting data only if
// receive has been enabled
begin
//pause_opcode_detected = 1'b0;
if(ap2rx_rx_fifo_err)
begin
clr_rx_error_from_rx_fsm = 1'b1;
460,14 → 406,7
 
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
begin
if(cf2rx_pause_en && af2rx_pause_frame)
begin
pause_seen = 1;
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
rewind_write = 1'b1;
end
else
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
end
else
begin
501,9 → 440,6
end
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
begin
if(pause_frame_detected)
rx_fsm_nxt_st = rx_fsm_pausectrl_st;
else
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
end
else
788,122 → 724,6
rx_fsm_nxt_st = rx_fsm_idle_st;
end
rx_fsm_pausectrl_st:
// collecting odd nibbles of pause control
// in case of termination of packet
// or carrier sense error then generate eop
// and generate status
begin
if(mi2rx_end_rcv)
begin
set_incomplete_frm = 1'b1;
error = 1'b1;
gen_eop = 1'b1;
rx_fsm_nxt_st = rx_fsm_chkval_st;
if(cf2rx_rcv_runt_pkt_en)
commit_write = 1'b1;
else
rewind_write = 1'b1;
end
else if(mi2rx_rcv_vld)
case(inc_rcv_byte_count[1:0])
2'b01 : if(mi2rx_rx_byte != 8'h88)
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
2'b10 : if(mi2rx_rx_byte != 8'h08)
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
2'b11 : if(mi2rx_rx_byte != 8'h00)
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
2'b00 : begin
if(mi2rx_rx_byte != 8'h01)
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
else
rx_fsm_nxt_st = rx_fsm_pausequanta_byte1_st;
end
endcase
else
rx_fsm_nxt_st = rx_fsm_pausectrl_st;
end // case: rx_fsm_pausectrl_nib1_st
rx_fsm_pausequanta_byte1_st:
// This state collects the odd nibbles of the receive data
begin
//pause_opcode_detected = 1'b1;
if(ap2rx_rx_fifo_err)
begin
rewind_write = 1'b1;
rx_fsm_nxt_st = rx_fsm_idle_st;
end
else if(mi2rx_end_rcv)
begin
set_incomplete_frm = 1'b1;
error = 1'b1;
gen_eop = 1'b1;
rx_fsm_nxt_st = rx_fsm_chkval_st;
if(cf2rx_rcv_runt_pkt_en)
commit_write = 1'b1;
else
rewind_write = 1'b1;
end
else if(mi2rx_rcv_vld)
begin
ld_pause_quanta_1 = 1'b1;
rx_fsm_nxt_st = rx_fsm_pausequanta_byte2_st;
end
else
rx_fsm_nxt_st = rx_fsm_pausequanta_byte1_st;
end // case: rx_fsm_pausequanta_nib1_st
rx_fsm_pausequanta_byte2_st:
// This state collects the even nibbles of the receive data.
begin
//pause_opcode_detected = 1'b1;
if(ap2rx_rx_fifo_err)
begin
rewind_write = 1'b1;
rx_fsm_nxt_st = rx_fsm_idle_st;
end
else if(mi2rx_end_rcv)
begin
set_incomplete_frm = 1'b1;
error = 1'b1;
gen_eop = 1'b1;
rx_fsm_nxt_st = rx_fsm_chkval_st;
end
else if(mi2rx_rcv_vld )
begin
ld_pause_quanta_2 = 1'b1;
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
end
else
rx_fsm_nxt_st = rx_fsm_pausequanta_byte2_st;
end // case: rx_fsm_pausequanta_nib2_st
rx_fsm_wt4_pause_end_st:
begin
//pause_opcode_detected = 1'b1;
if(ap2rx_rx_fifo_err)
begin
rewind_write = 1'b1;
rx_fsm_nxt_st = rx_fsm_idle_st;
end
else if(mi2rx_end_rcv)
begin
if(rcv_byte_count[14:0] < 15'd64) // mfilardo
begin
lengthfield_error = 1;
rx_fsm_nxt_st = rx_fsm_idle_st;
end
else if(rc2rx_crc_ok)
begin
gen_pause_det = 1;
rx_fsm_nxt_st = rx_fsm_idle_st;
end
else
rx_fsm_nxt_st = rx_fsm_idle_st;
end
else
rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
end // case: rx_fsm_wt4_pause_end_st
default:
begin
rx_fsm_nxt_st = rx_fsm_idle_st;
963,77 → 783,8
assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
(rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
//
// Detect pause control frame
always @(posedge phy_rx_clk
or negedge reset_n)
begin
if(!reset_n)
pause_frame_detected <= 1'b0;
else if(mi2rx_end_rcv)
pause_frame_detected <= 1'b0;
else if(af2rx_pause_frame && cf2rx_pause_en && pause_seen)
pause_frame_detected <= 1'b1;
end // always @ (posedge phy_rx_clk...
// counter used for decrementing pause to transmit
always @(posedge phy_rx_clk
or negedge reset_n)
begin
if(!reset_n)
pause_count <= 16'b0;
else
begin
if(~cf2rx_pause_en)
pause_count <= 'h0;
else if(gen_pause_det & pause_opcode_detected)
pause_count <= pause_quanta;
//else if(pause_quanta_count == 9'd511)
else if( ( cf2rx_gigabit_xfr && (pause_quanta_count[5:0] == 6'd63 )) ||
(~cf2rx_gigabit_xfr && (pause_quanta_count[6:0] == 7'd127)) ) // mfilardo pause bit time fix. A pause quanta should be 512 bit times.
pause_count <= pause_count - 1;
end // else: !if(!reset_n)
end // always @ (posedge phy_rx_clk...
// counter used for decrementing pause quanta count
// which is 512 bit times
always @(posedge phy_rx_clk
or negedge reset_n)
begin
if(!reset_n)
pause_quanta_count <= 9'b0;
else
begin
if(pause_dn)
pause_quanta_count <= 9'b0;
else if(rx2tx_pause_tx_int)
pause_quanta_count <= pause_quanta_count + 1;
end // else: !if(!reset_n)
end
 
assign pause_dn = ~|pause_count & rx2tx_pause_tx_int;
//A200 change :
//When phy_crs input is asserted rx2tx_pause_tx which stops the
//frame transmission. Same function has been done on receiving pause
//frame so phy_crs is ored with pause receive signal when config is
//zero.
assign rx2tx_pause_tx = rx2tx_pause_tx_int |
(phy_crs & ~crs_flow_control_enable);
 
// Generation pause to tx_fsm
always @(posedge phy_rx_clk
or negedge reset_n)
begin
if(!reset_n)
rx2tx_pause_tx_int <= 1'b0;
else
begin
if(pause_dn)
rx2tx_pause_tx_int <= 1'b0;
else if(gen_pause_det)
rx2tx_pause_tx_int <= 1'b1;
end // else: !if(!reset_n)
end // always @ (posedge phy_rx_clk...
assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
1354,34 → 1105,4
end // else: !if(!reset_n)
end // always @ (posedge phy_rx_clk...
// This is used load the pause quanta value on received
// pause control frame
always @(posedge phy_rx_clk or negedge reset_n)
begin
if(!reset_n)
begin
pause_quanta <= 16'b0;
c_pause_ptr <= 2'b0;
end // if (reset_n)
else if (rx_ch_en)
begin
if(mi2rx_strt_rcv)
begin
pause_quanta <= 16'b0;
c_pause_ptr <= 2'b0;
end
else
begin
if(ld_pause_quanta_1)
begin
pause_quanta[15:8] <= mi2rx_rx_byte;
end
else if(ld_pause_quanta_2)
begin
pause_quanta[7:0] <= mi2rx_rx_byte;
end
end // else: !if(mi2rx_strt_rcv)
end // else: !if(!reset_n)
end
endmodule
/rtl/gmac/mac/g_tx_fsm.v
86,25 → 86,17
//dfl and back
df2tx_dfl_dn,
//application
app_send_pause,
//FCS
tc2tx_fcs,
//Configuration
cf2tx_tstate_mode,
cf2tx_ch_en,
cf2tx_pad_enable,
cf2tx_append_fcs,
cf_mac_mode,
cf_mac_sa,
cf2tx_pause_quanta,
cf2tx_force_bad_fcs,
 
//RX pause
rx2tx_pause,
send_pause_active_out,
app_clk,
set_fifo_undrn,
124,7 → 116,6
 
input cf2tx_ch_en; //transmit enable application clock
input cf2tx_tstate_mode; //used for OFN's tstate enable on authentication interface
input app_tx_rdy; //tx fifo management, enough buffer to tx
input tx_end_frame; //Current DWORD marks end of frame
input [7:0] app_tx_dt_in; //double word data from the TX fifo mgmt
131,7 → 122,6
input app_tx_fifo_empty; //TX fifo is empty, if there were a data
//data request when app_tx_fifo_empty is asserted
//would result in FIFO underrun and error cond
input app_send_pause;
input [31:0] tc2tx_fcs;
//defferral inputs
145,14 → 135,7
//irrespective of this signal
input cf_mac_mode; // 1 is GMII 0 10/100
input [47:0] cf_mac_sa;
input [15:0] cf2tx_pause_quanta;
input cf2tx_force_bad_fcs;
//RX pause frame received
input rx2tx_pause; //in full duplex mode, the RX has received
//a pause frame, hence the TX is requested to
//hold transfers after the transmission of the
//current transfer. level signal
//from MII or RMII
input mi2tx_byte_ack; //MII interface accepted last byte
input tx_clk;
input tx_reset_n;
180,7 → 163,6
input phy_tx_en; // mfilardo ofn auth fix.
input app_clk;
output send_pause_active_out;
output set_fifo_undrn; // Description: At GMII Interface ,
// abug after a transmit fifo underun was found.
// The packet after a packet that
197,9 → 179,6
parameter dt_xfr_st = 12'b000000000001;
parameter dt_pad_st = 12'b000000000010;
parameter dt_fcs_st = 12'b000000000100;
parameter dt_pause_xfr_st = 12'b000010000000;
parameter dt_pause_pad_st = 12'b000100000000;
parameter dt_pause_fcs_st = 12'b001000000000;
wire tx_commit_read;
249,12 → 228,7
reg clr_first_dfl, set_first_dfl;
wire tx_lst_xfr;
wire tx_pause_sync;
reg inc_pause_index, clr_pause_index;
reg send_pause_active;
wire send_pause_sync;
reg [4:0] pause_index;
reg tx_lst_xfr_fcs_reg;
wire [15:0] tx_byte_cntr_int;
263,20 → 237,7
 
reg app_tx_rdy_dly;
 
reg send_pause_active_s1;
reg send_pause_active_out;
 
always @(posedge app_clk or negedge app_reset_n) begin
if (!app_reset_n) begin
send_pause_active_s1 <= 1'b0;
send_pause_active_out <= 1'b0;
end
else begin
send_pause_active_s1 <= send_pause_active;
send_pause_active_out <= send_pause_active_s1;
end
end
 
always @(posedge tx_clk or negedge tx_reset_n) begin
if (!tx_reset_n) begin
app_tx_rdy_dly <= 1'b0;
300,8 → 261,7
assign tx_lst_xfr = tx_lst_xfr_dt || tx_lst_xfr_fcs;
//To take care of 1 less byte count when fcs is not appended.
assign tx_byte_cntr_int = ((curr_dt_st == dt_fcs_st) ||
(curr_dt_st == dt_pause_fcs_st)) ? tx_byte_cntr : tx_byte_cntr + 16'h1;
assign tx_byte_cntr_int = (curr_dt_st == dt_fcs_st) ? tx_byte_cntr : tx_byte_cntr + 16'h1;
always @(posedge tx_clk or negedge tx_reset_n)
begin
325,15 → 285,6
half_dup_dble_reg U_dble_reg1 (
//outputs
.sync_out_pulse(tx_pause_sync),
//inputs
.in_pulse(rx2tx_pause),
.dest_clk(tx_clk),
.reset_n(tx_reset_n)
);
half_dup_dble_reg U_dble_reg2 (
//outputs
.sync_out_pulse(tx_ch_en),
344,14 → 295,6
);
half_dup_dble_reg U_dble_reg3 (
//outputs
.sync_out_pulse(send_pause_sync),
//inputs
.in_pulse(app_send_pause),
.dest_clk(tx_clk),
.reset_n(tx_reset_n)
);
 
half_dup_dble_reg U_dble_reg4 (
//outputs
391,11 → 334,11
always @(curr_dt_st or mi2tx_byte_ack or app_tx_fifo_empty
or tx_end_frame_reg or commit_read_sent
or tx_byte_cntr or tx_fcs_dn_reg or cf2tx_pad_enable or tx_ch_en
or df2tx_dfl_dn or tx_pause_sync or app_tx_rdy
or df2tx_dfl_dn or app_tx_rdy
or strt_fcs_reg
or tx_end_frame or tx_clk
or cf2tx_append_fcs
or app_tx_rdy_dly or send_pause_sync or pause_index or cur_idle_st_del)
or app_tx_rdy_dly or cur_idle_st_del)
begin
nxt_dt_st = curr_dt_st;
tx_fsm_rd = 0;
413,9 → 356,6
clr_fifo_undrn = 0;
clr_first_dfl = 0;
set_first_dfl = 0;
send_pause_active = 0;
inc_pause_index = 0;
clr_pause_index = 0;
case (curr_dt_st)
dt_idle_st :
begin
428,22 → 368,16
//in the case of full duplex
if (tx_ch_en) //config, channel enable
begin
if (send_pause_sync && df2tx_dfl_dn)
begin
// this ifdef is a bug fix. A pending pause can cause ifg to be 1 cycle short.
nxt_dt_st = dt_pause_xfr_st;
strt_preamble = 1;
end
else if (app_tx_rdy && df2tx_dfl_dn && !tx_pause_sync)
begin
tx_fsm_rd = 1;
nxt_dt_st = dt_xfr_st;
strt_preamble = 1;
end
else
nxt_dt_st = dt_idle_st;
if (app_tx_rdy && df2tx_dfl_dn)
begin
tx_fsm_rd = 1;
nxt_dt_st = dt_xfr_st;
strt_preamble = 1;
end
else
nxt_dt_st = dt_idle_st;
end // if (tx_ch_en)
else
else
nxt_dt_st = dt_idle_st;
end // case: dt_idle_st
587,60 → 521,8
end // else: !if(tx_fcs_dn)
end // case: dt_fcs_st
dt_pause_xfr_st :
begin
tx_byte_valid = 1;
send_pause_active = 1;
// Send the Pause Frame out
if (mi2tx_byte_ack)
begin
if (pause_index == 5'd18)
begin
clr_pause_index = 1;
nxt_dt_st = dt_pause_pad_st;
end
else
begin
inc_pause_index = 1;
nxt_dt_st = dt_pause_xfr_st;
end
end
else
begin
nxt_dt_st = dt_pause_xfr_st;
end
end // case: dt_pause_xfr_st
dt_pause_pad_st :
begin
// Append Padding to the Packet
tx_byte_valid = 1;
set_pad_byte = 1;
if (mi2tx_byte_ack && (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
begin
strt_fcs = 1;
nxt_dt_st = dt_pause_fcs_st;
end // if (mi2tx_byte_ack &&
// (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
else
nxt_dt_st = dt_pause_pad_st;
end // case: dt_pause_pad_st
dt_pause_fcs_st :
begin
// Wait for the FCS to be sent
if (tx_fcs_dn_reg)
begin
e_tx_sts_vld = 1;
nxt_dt_st = dt_idle_st;
end
else
begin
nxt_dt_st = dt_pause_fcs_st;
end
end // case: dt_pause_fcs_st
default :
begin
nxt_dt_st = dt_idle_st;
838,19 → 720,6
end // else: !if(!tx_reset_n)
end // always @ (posedge tx_clk or negedge tx_reset_n)
//Pause index counters
always @(posedge tx_clk or negedge tx_reset_n)
begin
if (!tx_reset_n)
pause_index <= 5'd0;
else
begin
if (clr_pause_index)
pause_index <= 5'd0;
else if (inc_pause_index)
pause_index <= pause_index + 1;
end // else: !if(!tx_reset_n)
end // always @ (posedge tx_clk or negedge tx_reset_n)
//Data mux, is controlled either by the mux select from the
//primary data flow or from the FCS mux select. When PAD
857,60 → 726,15
//data option is used bytes of all zeros are transmitted
always @(fcs_active or app_tx_dt_in or tc2tx_fcs
or send_bad_fcs or fcs_mux_select or
set_pad_byte or tx_fsm_dt_reg or send_pause_active or pause_index
or cf_mac_sa or cf2tx_pause_quanta)
set_pad_byte or tx_fsm_dt_reg )
begin
if (send_pause_active)
begin
case (pause_index)
5'd0 :
tx_byte = 8'h01;
5'd1 :
tx_byte = 8'h80;
5'd2 :
tx_byte = 8'hc2;
5'd3 :
tx_byte = 8'h00;
5'd4 :
tx_byte = 8'h00;
5'd5 :
tx_byte = 8'h01;
5'd6 :
tx_byte = cf_mac_sa[7:0];
5'd7 :
tx_byte = cf_mac_sa[15:8];
5'd8 :
tx_byte = cf_mac_sa[23:16];
5'd9 :
tx_byte = cf_mac_sa[31:24];
5'd10 :
tx_byte = cf_mac_sa[39:32];
5'd11 :
tx_byte = cf_mac_sa[47:40];
5'd12 :
tx_byte = 8'h88;
5'd13 :
tx_byte = 8'h08;
5'd14 :
tx_byte = 8'h00;
5'd15 :
tx_byte = 8'h01;
5'd16 :
tx_byte = cf2tx_pause_quanta[15:8];
5'd17 :
tx_byte = cf2tx_pause_quanta[7:0];
default :
tx_byte = 8'h00;
endcase // case (mux_select)
end
else if (!fcs_active && !set_pad_byte)
begin
if (!fcs_active && !set_pad_byte)
begin
//primary data flow
tx_byte = tx_fsm_dt_reg[7:0];
// $stop;
end // if (!fcs_active)
tx_byte = tx_fsm_dt_reg[7:0];
end // if (!fcs_active)
else if (fcs_active)
begin
begin
tx_byte = tc2tx_fcs[7:0];
case (fcs_mux_select)
3'd0 :
/rtl/gmac/mac/g_cfg_mgmt.v
85,7 → 85,6
cf2mi_rmii_en,
 
cfg_uni_mac_mode_change_i,
cfg_crs_flow_ctrl_enb_i,
 
//CHANNEL enable
cf2tx_ch_en,
99,18 → 98,13
cf2rx_ch_en,
cf2rx_strp_pad_en,
cf2rx_snd_crc,
cf2rx_pause_en,
cf2rx_addrchk_en,
cf2rx_runt_pkt_en,
cf2af_broadcast_disable,
cf_mac_sa,
cfg_ip_sa,
cfg_mac_filter,
 
cf2tx_pause_quanta,
cf2rx_max_pkt_sz,
cf2tx_force_bad_fcs,
cf2tx_tstate_mode,
//MDIO CONTROL & DATA
cf2md_datain,
cf2md_regad,
125,68 → 119,62
//---------------------------------
// Reg Bus Interface Signal
//---------------------------------
input reg_cs ;
input reg_wr ;
input [3:0] reg_addr ;
input [31:0] reg_wdata ;
input [3:0] reg_be ;
input reg_cs ;
input reg_wr ;
input [3:0] reg_addr ;
input [31:0] reg_wdata ;
input [3:0] reg_be ;
// Outputs
output [31:0] reg_rdata ;
output reg_ack ;
output [31:0] reg_rdata ;
output reg_ack ;
 
input rx_sts_vld ; // rx status valid indication, sync w.r.t app clk
input [7:0] rx_sts ; // rx status bits
input rx_sts_vld ; // rx status valid indication, sync w.r.t app clk
input [7:0] rx_sts ; // rx status bits
 
input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
input tx_sts ; // tx status bits
input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
input tx_sts ; // tx status bits
 
//List of Inputs
 
input app_clk, app_reset_n;
input md2cf_cmd_done; // Read/Write MDIO completed
input md2cf_status; // MDIO transfer error
input [15:0] md2cf_data; // Data from PHY for a
// mdio read access
input app_clk ;
input app_reset_n ;
input md2cf_cmd_done ; // Read/Write MDIO completed
input md2cf_status ; // MDIO transfer error
input [15:0] md2cf_data ; // Data from PHY for a
// mdio read access
//List of Outputs
output cf2mi_rmii_en; // Working in RMII when set to 1
output cf_mac_mode; // mac mode set this to 1 for 100Mbs/10Mbs
output cf_chk_rx_dfl; // Check for RX Deferal
output [47:0] cf_mac_sa;
output [31:0] cfg_ip_sa;
output [31:0] cfg_mac_filter;
output [15:0] cf2tx_pause_quanta;
output cf2tx_ch_en; //enable the TX channel
output cf_silent_mode; // PHY Inactive
output [7:0] cf2df_dfl_single; //number of clk ticks for dfl
output [7:0] cf2df_dfl_single_rx; //number of clk ticks for dfl
output cf2mi_rmii_en ; // Working in RMII when set to 1
output cf_mac_mode ; // mac mode set this to 1 for 100Mbs/10Mbs
output cf_chk_rx_dfl ; // Check for RX Deferal
output [47:0] cf_mac_sa ;
output [31:0] cfg_ip_sa ;
output [31:0] cfg_mac_filter ;
output cf2tx_ch_en ; //enable the TX channel
output cf_silent_mode ; //PHY Inactive
output [7:0] cf2df_dfl_single ; //number of clk ticks for dfl
output [7:0] cf2df_dfl_single_rx ; //number of clk ticks for dfl
output cf2tx_tstate_mode; //used for OFN's tstate enable on authentication interface
output cf2tx_pad_enable; //enable padding, < 64 bytes
output cf2tx_append_fcs; //append CRC for TX frames
output cf2rx_ch_en; //Enable RX channel
output cf2rx_strp_pad_en; //strip the padded bytes on RX frame
output cf2rx_snd_crc; //send FCS to application, else strip
//the FCS before sending to application
output cf2rx_pause_en; //enable flow control for full duplex using
//pause control frames
output cf2mi_loopback_en; // TX to RX loop back enable
output cf2rx_addrchk_en; //check the destination address, filter
output cf2rx_runt_pkt_en; //don't throw packets less than 64 bytes
output cf2af_broadcast_disable;
output [15:0] cf2md_datain;
output [4:0] cf2md_regad;
output [4:0] cf2md_phyad;
output cf2md_op;
output cf2md_go;
output cf2tx_pad_enable ; //enable padding, < 64 bytes
output cf2tx_append_fcs; //append CRC for TX frames
output cf2rx_ch_en; //Enable RX channel
output cf2rx_strp_pad_en; //strip the padded bytes on RX frame
output cf2rx_snd_crc; //send FCS to application, else strip
//the FCS before sending to application
output cf2mi_loopback_en; // TX to RX loop back enable
output cf2rx_runt_pkt_en; //don't throw packets less than 64 bytes
output [15:0] cf2md_datain;
output [4:0] cf2md_regad;
output [4:0] cf2md_phyad;
output cf2md_op;
output cf2md_go;
 
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
output cf2tx_force_bad_fcs; //force bad fcs on tx
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
output cf2tx_force_bad_fcs; //force bad fcs on tx
 
output cfg_uni_mac_mode_change_i;
output cfg_crs_flow_ctrl_enb_i;
output cfg_uni_mac_mode_change_i;
 
// Wire assignments for output signals
231,13 → 219,9
wire [7:0] mac_sa_out_4;
wire [7:0] mac_sa_out_5;
wire [7:0] mac_sa_out_6;
wire [7:0] pause_quanta_out_1;
wire [7:0] pause_quanta_out_2;
wire [47:0] cf_mac_sa;
wire [15:0] cf2tx_pause_quanta;
wire [15:0] cf2rx_max_pkt_sz;
wire cf2tx_force_bad_fcs;
wire cf2tx_tstate_mode;
reg force_bad_fcs;
reg cont_force_bad_fcs;
wire [31:0] mdio_stat_out;
411,7 → 395,6
assign cf2tx_ch_en = tx_cntrl_out_1[0];
assign cf2tx_pad_enable = tx_cntrl_out_1[3];
assign cf2tx_append_fcs = tx_cntrl_out_1[4];
assign cf2tx_tstate_mode = tx_cntrl_out_1[6];
assign cf2tx_force_bad_fcs = tx_cntrl_out_1[7];
 
assign reg_0[15:0] = {tx_cntrl_out_2,tx_cntrl_out_1};
421,7 → 404,6
// BIT[0] = Receive Channel Enable
// BIT[1] = Strip Padding from the Receive data
// BIT[2] = Send CRC along with data to the host
// BIT[3] = Enable pause frame detect
// BIT[4] = Check RX Deferral
// BIT[5] = Receive Address Check Enable
// BIT[6] = Receive Runt Packet
441,11 → 423,8
assign cf2rx_ch_en = rx_cntrl_out_1[0];
assign cf2rx_strp_pad_en = rx_cntrl_out_1[1];
assign cf2rx_snd_crc = rx_cntrl_out_1[2];
assign cf2rx_pause_en = rx_cntrl_out_1[3];
assign cf_chk_rx_dfl = rx_cntrl_out_1[4];
assign cf2rx_addrchk_en = rx_cntrl_out_1[5];
assign cf2rx_runt_pkt_en = rx_cntrl_out_1[6];
assign cf2af_broadcast_disable = rx_cntrl_out_1[7];
 
 
assign reg_1[7:0] = {rx_cntrl_out_1};
506,7 → 485,6
assign cf2mi_rmii_en = mac_mode_out[1];
assign cf2mi_loopback_en = mac_mode_out[2];
assign cf_silent_mode = mac_mode_out[5];
assign cfg_crs_flow_ctrl_enb_i = mac_mode_out[6];
assign cfg_uni_mac_mode_change_i = mac_mode_out[7];
 
 
712,37 → 690,11
);
 
assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
//========================================================================//
//Pause Quanta Register 24
 
generic_register #(8,0 ) pause_quanta_reg_1 (
.we ({8{sw_wr_en_9 & wr_be[0] }}),
.data_in (reg_wdata[7:0] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (pause_quanta_out_1[7:0] )
);
 
generic_register #(8,0 ) pause_quanta_reg_2 (
.we ({8{sw_wr_en_9 & wr_be[1] }}),
.data_in (reg_wdata[15:8] ),
.reset_n (app_reset_n ),
.clk (app_clk ),
//List of Outs
.data_out (pause_quanta_out_2[7:0] )
);
assign reg_9 = 0; // free
 
 
assign cf2tx_pause_quanta = {pause_quanta_out_1 , pause_quanta_out_2};
 
 
assign reg_9[15:0] = cf2tx_pause_quanta;
 
 
 
//-----------------------------------------------------------------------
// RX-Clock Static Counter Status Signal
//-----------------------------------------------------------------------

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