URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/turbo8051/trunk
- from Rev 77 to Rev 78
- ↔ Reverse comparison
Rev 77 → Rev 78
/rtl/gmac/mac/g_mii_intf.v
446,7 → 446,7
end |
end*/ |
|
mii_tx_nibble_st: / |
mii_tx_nibble_st: |
// This state picks up a byte from the transmit block |
// before transmitting on the line |
begin |
/rtl/gmac/mac/g_tx_top.v
161,7 → 161,7
|
// Instantiate Transmit State machine block |
g_tx_fsm U_tx_fsm( |
.app_clk(app_clk), / |
.app_clk(app_clk), |
.set_fifo_undrn(set_fifo_undrn), |
|
//Outputs |
/verif/log/complie.log
1,95 → 1,93
-
-Model Technology ModelSim ACTEL vlog 10.1b Compiler 2012.04 Apr 27 2012
--- Compiling module tb_top
--- Compiling module tb_glbl
--- Compiling module tb_eth_top
--- Compiling module tb_mii
--- Compiling module tb_rmii
--- Compiling module uart_agent
--- Compiling module AT45DB321
--- Compiling module acdc_check
--- Compiling module internal_logic
--- Compiling module memory_access
--- Compiling module m25p20
--- Compiling module oc8051_xram
--- Compiling module oc8051_xrom
--- Compiling module digital_core
--- Compiling module g_mac_top
--- Compiling module half_dup_dble_reg
--- Compiling module g_tx_fsm
--- Compiling module g_deferral
--- Compiling module g_tx_top
--- Compiling module g_rx_fsm
--- Compiling module g_cfg_mgmt
--- Compiling module s2f_sync
--- Compiling module g_md_intf
--- Compiling module g_deferral_rx
--- Compiling module g_rx_top
--- Compiling module g_mii_intf
--- Compiling module g_mac_core
--- Compiling module g_eth_parser
--- Compiling module g_rx_crc32
--- Compiling module g_tx_crc32
--- Compiling module g_dpath_ctrl
--- Compiling module spi_core
--- Compiling module spi_ctl
--- Compiling module spi_if
--- Compiling module spi_cfg
--- Compiling module uart_rxfsm
--- Compiling module uart_txfsm
--- Compiling module uart_core
--- Compiling module uart_cfg
--- Compiling module clkgen
--- Compiling module clk_ctl
--- Compiling module wb_crossbar
--- Compiling module wb_rd_mem2mem
--- Compiling module wb_wr_mem2mem
--- Compiling module oc8051_top
--- Compiling module oc8051_rom
--- Compiling module oc8051_alu_src_sel
--- Compiling module oc8051_alu
--- Compiling module oc8051_decoder
--- Compiling module oc8051_divide
--- Compiling module oc8051_multiply
--- Compiling module oc8051_memory_interface
--- Compiling module oc8051_ram_top
--- Compiling module oc8051_acc
--- Compiling module oc8051_comp
--- Compiling module oc8051_sp
--- Compiling module oc8051_dptr
--- Compiling module oc8051_cy_select
--- Compiling module oc8051_psw
--- Compiling module oc8051_indi_addr
--- Compiling module oc8051_ports
--- Compiling module oc8051_b_register
--- Compiling module oc8051_uart
--- Compiling module oc8051_int
--- Compiling module oc8051_tc
--- Compiling module oc8051_tc2
--- Compiling module oc8051_sfr
--- Compiling module oc8051_ram_256x8_two_bist
--- Scanning library file '../../rtl/lib/registers.v'
--- Compiling module req_register
--- Compiling module stat_register
--- Compiling module generic_register
--- Compiling module generic_intr_stat_reg
--- Scanning library file '../../rtl/lib/stat_counter.v'
--- Compiling module stat_counter
--- Scanning library file '../../rtl/lib/toggle_sync.v'
--- Compiling module toggle_sync
--- Scanning library file '../../rtl/lib/double_sync_low.v'
--- Compiling module double_sync_low
--- Scanning library file '../../rtl/lib/async_fifo.v'
--- Compiling module async_fifo
--- Scanning library file '../../rtl/lib/registers.v'
--- Compiling module bit_register
--- Scanning library file '../../rtl/lib/stat_counter.v'
--- Scanning library file '../../rtl/lib/toggle_sync.v'
--- Scanning library file '../../rtl/lib/double_sync_low.v'
--- Scanning library file '../../rtl/lib/async_fifo.v'
-
-Top level modules:
- tb_top
- oc8051_rom
- oc8051_uart
+Model Technology ModelSim Microsemi vlog 2020.3 Compiler 2020.07 Jul 13 2020
+Start time: 13:03:31 on Nov 24,2022
+vlog -work work "+define+SFLASH_SPDUP" -sv "+incdir+../defs" "+incdir+../../rtl/defs" "+incdir+../../rtl/8051" "+incdir+../agents/spi" "+incdir+../agents/spi/st_m25p20a" "+incdir+../agents/ethernet" "+incdir+../lib" "+incdir+../testcase" "+incdir+../tb" time_scale.v ../tb/tb_top.v ../../verif/agents/ethernet/tb_eth_top.v ../../verif/agents/ethernet/tb_mii.v ../../verif/agents/ethernet/tb_rmii.v ../../verif/agents/uart/uart_agent.v ../../verif/agents/spi/atmel/AT45DBXXX_v2.0.3.v ../../verif/agents/spi/st_m25p20a/acdc_check.v ../../verif/agents/spi/st_m25p20a/internal_logic.v ../../verif/agents/spi/st_m25p20a/memory_access.v ../../verif/agents/spi/st_m25p20a/M25P20.v ../../verif/model/oc8051_xram.v ../../verif/model/oc8051_xrom.v ../../rtl/core/digital_core.v ../../rtl/gmac/top/g_mac_top.v ../../rtl/gmac/mac/dble_reg.v ../../rtl/gmac/mac/g_tx_fsm.v ../../rtl/gmac/mac/g_deferral.v ../../rtl/gmac/mac/g_tx_top.v ../../rtl/gmac/mac/g_rx_fsm.v ../../rtl/gmac/mac/g_cfg_mgmt.v ../../rtl/gmac/mac/s2f_sync.v ../../rtl/gmac/mac/g_md_intf.v ../../rtl/gmac/mac/g_deferral_rx.v ../../rtl/gmac/mac/g_rx_top.v ../../rtl/gmac/mac/g_mii_intf.v ../../rtl/gmac/mac/g_mac_core.v ../../rtl/gmac/ctrl/eth_parser.v ../../rtl/gmac/crc32/g_rx_crc32.v ../../rtl/gmac/crc32/g_tx_crc32.v ../../rtl/lib/g_dpath_ctrl.v ../../rtl/spi/spi_core.v ../../rtl/spi/spi_ctl.v ../../rtl/spi/spi_if.v ../../rtl/spi/spi_cfg.v ../../rtl/uart/uart_rxfsm.v ../../rtl/uart/uart_txfsm.v ../../rtl/uart/uart_core.v ../../rtl/uart/uart_cfg.v ../../rtl/clkgen/clkgen.v ../../rtl/lib/clk_ctl.v ../../rtl/lib/wb_crossbar.v ../../rtl/lib/wb_rd_mem2mem.v ../../rtl/lib/wb_wr_mem2mem.v ../../rtl/8051/oc8051_top.v ../../rtl/8051/oc8051_rom.v ../../rtl/8051/oc8051_alu_src_sel.v ../../rtl/8051/oc8051_alu.v ../../rtl/8051/oc8051_decoder.v ../../rtl/8051/oc8051_divide.v ../../rtl/8051/oc8051_multiply.v ../../rtl/8051/oc8051_memory_interface.v ../../rtl/8051/oc8051_ram_top.v ../../rtl/8051/oc8051_acc.v ../../rtl/8051/oc8051_comp.v ../../rtl/8051/oc8051_sp.v ../../rtl/8051/oc8051_dptr.v ../../rtl/8051/oc8051_cy_select.v ../../rtl/8051/oc8051_psw.v ../../rtl/8051/oc8051_indi_addr.v ../../rtl/8051/oc8051_ports.v ../../rtl/8051/oc8051_b_register.v ../../rtl/8051/oc8051_uart.v ../../rtl/8051/oc8051_int.v ../../rtl/8051/oc8051_tc.v ../../rtl/8051/oc8051_tc2.v ../../rtl/8051/oc8051_sfr.v ../../rtl/8051/oc8051_ram_256x8_two_bist.v -v ../../rtl/lib/registers.v -v ../../rtl/lib/stat_counter.v -v ../../rtl/lib/toggle_sync.v -v ../../rtl/lib/double_sync_low.v -v ../../rtl/lib/async_fifo.v
+-- Compiling module tb_top
+-- Compiling module tb_glbl
+-- Compiling module tb_eth_top
+-- Compiling module tb_mii
+-- Compiling module tb_rmii
+-- Compiling module uart_agent
+-- Compiling module AT45DB321
+-- Compiling module acdc_check
+-- Compiling module internal_logic
+-- Compiling module memory_access
+-- Compiling module m25p20
+-- Compiling module oc8051_xram
+-- Compiling module oc8051_xrom
+-- Compiling module digital_core
+-- Compiling module g_mac_top
+-- Compiling module half_dup_dble_reg
+-- Compiling module g_tx_fsm
+-- Compiling module g_deferral
+-- Compiling module g_tx_top
+-- Compiling module g_rx_fsm
+-- Compiling module g_cfg_mgmt
+-- Compiling module s2f_sync
+-- Compiling module g_md_intf
+-- Compiling module g_deferral_rx
+-- Compiling module g_rx_top
+-- Compiling module g_mii_intf
+-- Compiling module g_mac_core
+-- Compiling module g_eth_parser
+-- Compiling module g_rx_crc32
+-- Compiling module g_tx_crc32
+-- Compiling module g_dpath_ctrl
+-- Compiling module spi_core
+-- Compiling module spi_ctl
+-- Compiling module spi_if
+-- Compiling module spi_cfg
+-- Compiling module uart_rxfsm
+-- Compiling module uart_txfsm
+-- Compiling module uart_core
+-- Compiling module uart_cfg
+-- Compiling module clkgen
+-- Compiling module clk_ctl
+-- Compiling module wb_crossbar
+-- Compiling module wb_rd_mem2mem
+-- Compiling module wb_wr_mem2mem
+-- Compiling module oc8051_top
+-- Compiling module oc8051_rom
+-- Compiling module oc8051_alu_src_sel
+-- Compiling module oc8051_alu
+-- Compiling module oc8051_decoder
+-- Compiling module oc8051_divide
+-- Compiling module oc8051_multiply
+-- Compiling module oc8051_memory_interface
+-- Compiling module oc8051_ram_top
+-- Compiling module oc8051_acc
+-- Compiling module oc8051_comp
+-- Compiling module oc8051_sp
+-- Compiling module oc8051_dptr
+-- Compiling module oc8051_cy_select
+-- Compiling module oc8051_psw
+-- Compiling module oc8051_indi_addr
+-- Compiling module oc8051_ports
+-- Compiling module oc8051_b_register
+-- Compiling module oc8051_uart
+-- Compiling module oc8051_int
+-- Compiling module oc8051_tc
+-- Compiling module oc8051_tc2
+-- Compiling module oc8051_sfr
+-- Compiling module oc8051_ram_256x8_two_bist
+-- Scanning library file '../../rtl/lib/registers.v'
+-- Compiling module req_register
+-- Compiling module stat_register
+-- Compiling module generic_register
+-- Compiling module generic_intr_stat_reg
+-- Scanning library file '../../rtl/lib/stat_counter.v'
+-- Compiling module stat_counter
+-- Scanning library file '../../rtl/lib/toggle_sync.v'
+-- Compiling module toggle_sync
+-- Scanning library file '../../rtl/lib/double_sync_low.v'
+-- Compiling module double_sync_low
+-- Scanning library file '../../rtl/lib/async_fifo.v'
+-- Compiling module async_fifo
+-- Scanning library file '../../rtl/lib/registers.v'
+-- Compiling module bit_register
+
+Top level modules:
+ tb_top
+ oc8051_rom
+ oc8051_uart
+End time: 13:03:31 on Nov 24,2022, Elapsed time: 0:00:00
+Errors: 0, Warnings: 0
/verif/log/gmac_test_2.log
1,281 → 1,280
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl |
|
# 10.1b |
|
# vsim +gmac_test_2 -do run.do -c tb_top |
# // ModelSim ACTEL 10.1b Apr 27 2012 |
# // |
# // Copyright 1991-2012 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION |
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS |
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.wb_crossbar |
# Loading work.g_mac_top |
# Loading work.g_dpath_ctrl |
# Loading work.g_eth_parser |
# Loading work.g_mac_core |
# Loading work.g_rx_top |
# Loading work.g_rx_fsm |
# Loading work.half_dup_dble_reg |
# Loading work.g_rx_crc32 |
# Loading work.g_deferral_rx |
# Loading work.g_md_intf |
# Loading work.g_tx_top |
# Loading work.g_deferral |
# Loading work.g_tx_fsm |
# Loading work.g_tx_crc32 |
# Loading work.toggle_sync |
# Loading work.g_cfg_mgmt |
# Loading work.s2f_sync |
# Loading work.generic_register |
# Loading work.req_register |
# Loading work.stat_counter |
# Loading work.generic_intr_stat_reg |
# Loading work.g_mii_intf |
# Loading work.async_fifo |
# Loading work.wb_rd_mem2mem |
# Loading work.wb_wr_mem2mem |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
# Loading work.oc8051_multiply |
# Loading work.oc8051_divide |
# Loading work.oc8051_ram_top |
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
# Loading work.oc8051_sfr |
# Loading work.oc8051_acc |
# Loading work.oc8051_b_register |
# Loading work.oc8051_sp |
# Loading work.oc8051_dptr |
# Loading work.oc8051_psw |
# Loading work.oc8051_ports |
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.tb_eth_top |
# Loading work.tb_mii |
# Loading work.tb_rmii |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
# Loading work.acdc_check |
# Loading work.internal_logic |
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(397): [TOFD] - System task or function '$shm_open' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(398): [TOFD] - System task or function '$shm_probe' is not defined. |
# |
# Region: /tb_top |
# ** Warning: (vsim-3017) ../tb/tb_top.v(235): [TFMPC] - Too few port connections. Expected 50, found 44. |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_txd'. The port definition is at: ../../rtl/core/digital_core.v(29). |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_rxd'. The port definition is at: ../../rtl/core/digital_core.v(35). |
# |
# Region: /tb_top/u_core |
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_mode'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_enable'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_clk'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_in'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out'. |
# |
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out_en'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(214): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_rxfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'aempty'. |
# |
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(230): [TFMPC] - Too few port connections. Expected 14, found 12. |
# |
# Region: /tb_top/u_core/u_uart_core/u_txfifo |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'afull'. |
# |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'aempty'. |
# |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# NOTE: COMMUNICATION (RE)STARTED |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 00114501 |
# Config-Write: Id: 1 Addr = 0008, Cfg. Data = 00001616 |
# Clock period configured = 40 ns, data width = 4 |
# Config-Write: Id: 1 Addr = 0024, Cfg. Data = 70407000 |
# Status: End of Transmission Loop |
# 1260 ns: Starting packet transmission to MAC, size = 64 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81 |
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa |
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20 |
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d |
# **** |
# 7020 ns: Completed packet transmission to MAC |
# 8060 ns: Starting packet transmission to MAC, size = 65 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a |
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71 |
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c |
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9 |
# bb |
# **** |
# 13900 ns: Completed packet transmission to MAC |
# Status: End of Waiting Event Loop |
# 14940 ns: Starting packet transmission to MAC, size = 66 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d |
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73 |
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79 |
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99 |
# f0 ca |
# **** |
# 20860 ns: Completed packet transmission to MAC |
# 21900 ns: Starting packet transmission to MAC, size = 67 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79 |
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7 |
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66 |
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1 |
# d6 98 d3 |
# **** |
# 27900 ns: Completed packet transmission to MAC |
# 28940 ns: Starting packet transmission to MAC, size = 68 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78 |
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98 |
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38 |
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2 |
# d8 8a 95 46 |
# **** |
# 35020 ns: Completed packet transmission to MAC |
# 36060 ns: Starting packet transmission to MAC, size = 69 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd |
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae |
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53 |
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1 |
# 1f dd 21 ca 31 |
# **** |
# 42220 ns: Completed packet transmission to MAC |
# 43260 ns: Starting packet transmission to MAC, size = 70 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58 |
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49 |
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38 |
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9 |
# 86 25 ec 93 f7 b6 |
# **** |
# 49500 ns: Completed packet transmission to MAC |
# 50540 ns: Starting packet transmission to MAC, size = 71 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d |
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd |
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52 |
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6 |
# 25 32 a2 b2 82 de 56 |
# **** |
# 56860 ns: Completed packet transmission to MAC |
# 57900 ns: Starting packet transmission to MAC, size = 72 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14 |
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73 |
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93 |
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6 |
# bb 00 0f 69 16 8d 9c 08 |
# **** |
# 64300 ns: Completed packet transmission to MAC |
# 65340 ns: Starting packet transmission to MAC, size = 73 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59 |
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5 |
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8 |
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68 |
# f0 aa 0f f1 7d 1f 08 38 e7 |
# **** |
# 71820 ns: Completed packet transmission to MAC |
# Status: End of Waiting Delay Loop |
############################# |
# TB MII Statistic |
# TB TO DUT : |
# Frm cnt : 10 |
# Byte cnt : 685 |
# DUT TO TB : |
# Frm cnt : 0 |
# Byte cnt : 0 |
# Pause Frm cnt: 0 |
# Alig Err cnt: 0 |
# usized Err cnt: 0 |
# crc Err cnt: 0 |
# Length Err cnt: 0 |
############################# |
# A200 TB => 171820 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected 1 |
# A200 TB => 171820 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected 2 |
# |
# ------------------------------------------------- |
# Test Status |
# warnings: 0, errors: 2 |
# |
# ------------------------------------------------- |
# Test Status |
# warnings: 0, errors: 2 |
# |
# ========= |
# Test Status: TEST FAILED |
# ========= |
# |
Reading pref.tcl |
|
# 2020.3 |
|
# vsim -do "run.do" -c tb_top "+gmac_test_2" |
# Start time: 19:19:11 on Aug 18,2022 |
# // ModelSim Microsemi 2020.3 Jul 13 2020 Linux 5.15.0-41-generic |
# // |
# // Copyright 1991-2020 Mentor Graphics Corporation |
# // All Rights Reserved. |
# // |
# // ModelSim Microsemi and its associated documentation contain trade |
# // secrets and commercial or financial information that are the property of |
# // Mentor Graphics Corporation and are privileged, confidential, |
# // and exempt from disclosure under the Freedom of Information Act, |
# // 5 U.S.C. Section 552. Furthermore, this information |
# // is prohibited from disclosure under the Trade Secrets Act, |
# // 18 U.S.C. Section 1905. |
# // |
# Loading sv_std.std |
# Loading work.tb_top |
# Loading work.digital_core |
# Loading work.clkgen |
# Loading work.clk_ctl |
# Loading work.wb_crossbar |
# Loading work.g_mac_top |
# Loading work.g_dpath_ctrl |
# Loading work.g_eth_parser |
# Loading work.g_mac_core |
# Loading work.g_rx_top |
# Loading work.g_rx_fsm |
# Loading work.half_dup_dble_reg |
# Loading work.g_rx_crc32 |
# Loading work.g_deferral_rx |
# Loading work.g_md_intf |
# Loading work.g_tx_top |
# Loading work.g_deferral |
# Loading work.g_tx_fsm |
# Loading work.g_tx_crc32 |
# Loading work.toggle_sync |
# Loading work.g_cfg_mgmt |
# Loading work.s2f_sync |
# Loading work.generic_register |
# Loading work.req_register |
# Loading work.stat_counter |
# Loading work.generic_intr_stat_reg |
# Loading work.g_mii_intf |
# Loading work.async_fifo |
# Loading work.wb_rd_mem2mem |
# Loading work.wb_wr_mem2mem |
# Loading work.uart_core |
# Loading work.uart_cfg |
# Loading work.stat_register |
# Loading work.uart_txfsm |
# Loading work.uart_rxfsm |
# Loading work.double_sync_low |
# Loading work.spi_core |
# Loading work.spi_if |
# Loading work.spi_ctl |
# Loading work.spi_cfg |
# Loading work.oc8051_top |
# Loading work.oc8051_decoder |
# Loading work.oc8051_alu |
# Loading work.oc8051_multiply |
# Loading work.oc8051_divide |
# Loading work.oc8051_ram_top |
# Loading work.oc8051_ram_256x8_two_bist |
# Loading work.oc8051_alu_src_sel |
# Loading work.oc8051_comp |
# Loading work.oc8051_cy_select |
# Loading work.oc8051_indi_addr |
# Loading work.oc8051_memory_interface |
# Loading work.oc8051_sfr |
# Loading work.oc8051_acc |
# Loading work.oc8051_b_register |
# Loading work.oc8051_sp |
# Loading work.oc8051_dptr |
# Loading work.oc8051_psw |
# Loading work.oc8051_ports |
# Loading work.oc8051_int |
# Loading work.oc8051_tc |
# Loading work.oc8051_tc2 |
# Loading work.oc8051_xrom |
# Loading work.oc8051_xram |
# Loading work.tb_eth_top |
# Loading work.tb_mii |
# Loading work.tb_rmii |
# Loading work.uart_agent |
# Loading work.m25p20 |
# Loading work.memory_access |
# Loading work.acdc_check |
# Loading work.internal_logic |
# Loading work.AT45DB321 |
# Loading work.tb_glbl |
# Loading work.bit_register |
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u_core'. Expected 50, found 44. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../tb/tb_top.v Line: 162 |
# ** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (4) for port 'phy_txd'. The port definition is at: ../../rtl/core/digital_core.v(29). |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../tb/tb_top.v Line: 162 |
# ** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (4) for port 'phy_rxd'. The port definition is at: ../../rtl/core/digital_core.v(35). |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core File: ../tb/tb_top.v Line: 162 |
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'scan_mode'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'scan_enable'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_clk'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_in'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_out'. |
# ** Warning: (vsim-3722) ../tb/tb_top.v(162): [TFMPC] - Missing connection for port 'mdio_out_en'. |
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u_rxfifo'. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_rxfifo File: ../../rtl/uart/uart_core.v Line: 200 |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(200): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(200): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u_txfifo'. Expected 14, found 12. |
# Time: 0 ps Iteration: 0 Instance: /tb_top/u_core/u_uart_core/u_txfifo File: ../../rtl/uart/uart_core.v Line: 216 |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(216): [TFMPC] - Missing connection for port 'afull'. |
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(216): [TFMPC] - Missing connection for port 'aempty'. |
# ** Warning: (vsim-PLI-3003) [TOFD] - System task or function '$shm_open' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v Line: 397 |
# ** Warning: (vsim-PLI-3003) [TOFD] - System task or function '$shm_probe' is not defined. |
# Time: 0 ps Iteration: 0 Instance: /tb_top File: ../tb/tb_top.v Line: 398 |
# do run.do |
# i : 02 |
# i : 00 |
# i : 08 |
# i : 12 |
# i : 00 |
# i : 64 |
# i : 80 |
# i : fe |
# i : 75 |
# i : 81 |
# NOTE : Load memory with Initial delivery content |
# NOTE : Initial Load End |
# --> Dumpping the design |
# ** Error (suppressible): (vsim-12023) Cannot execute undefined system task/function '$shm_open' |
# Time: 0 ps Iteration: 0 Process: /tb_top/#INITIAL#395 File: ../tb/tb_top.v Line: 397 |
# ** Error (suppressible): (vsim-12023) Cannot execute undefined system task/function '$shm_probe' |
# Time: 0 ps Iteration: 0 Process: /tb_top/#INITIAL#395 File: ../tb/tb_top.v Line: 398 |
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file "../test_log_files/test1_events.log" for writing. |
# No such file or directory. (errno = ENOENT) : ../testcase/gmac_test2.v(20) |
# Time: 0 ps Iteration: 0 Instance: /tb_top |
# NOTE: COMMUNICATION (RE)STARTED |
# Config-Write: Id: 1 Addr = 0000, Cfg. Data = 00114501 |
# Config-Write: Id: 1 Addr = 0008, Cfg. Data = 00001616 |
# Clock period configured = 40 ns, data width = 4 |
# Config-Write: Id: 1 Addr = 0024, Cfg. Data = 70407000 |
# Status: End of Transmission Loop |
# 1260 ns: Starting packet transmission to MAC, size = 64 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 24 81 |
# 09 63 0d 8d 65 12 01 0d 76 3d ed 8c f9 c6 c5 aa |
# e5 77 12 8f f2 ce e8 c5 5c bd 2d 65 63 0a 80 20 |
# aa 9d 96 13 0d 53 6b d5 02 ae 1d cf 21 4c 4b 3d |
# **** |
# 7020 ns: Completed packet transmission to MAC |
# 8060 ns: Starting packet transmission to MAC, size = 65 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 23 0a |
# ca 3c f2 8a 41 d8 78 89 eb b6 c6 ae bc 2a 0b 71 |
# 85 4f 3b 3a 7e 15 f1 d9 62 4c 9f 8f f8 b7 9f 5c |
# 5b 89 49 d0 d7 51 96 0c c2 c8 77 3d 12 fb 72 d9 |
# bb |
# **** |
# 13900 ns: Completed packet transmission to MAC |
# Status: End of Waiting Event Loop |
# 14940 ns: Starting packet transmission to MAC, size = 66 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 7e 6d |
# 39 1f d3 85 78 5b 49 3f 2a 58 86 8e 9c fa 26 73 |
# a3 2f b3 5f 44 f7 cb e6 5a 29 ed da 65 b5 df 79 |
# 44 d0 2a ab 0e dc 9a fd c3 56 4e 67 0a b6 6f 99 |
# f0 ca |
# **** |
# 20860 ns: Completed packet transmission to MAC |
# 21900 ns: Starting packet transmission to MAC, size = 67 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 38 79 |
# b8 94 93 04 59 db 4d d9 6d 76 ca b6 95 46 04 f7 |
# 69 b4 88 28 2d c7 2e 08 1c fd 29 1c 86 da 3d 66 |
# 70 73 ba 5e fa d5 1a b9 37 96 c0 26 b6 7d dc e1 |
# d6 98 d3 |
# **** |
# 27900 ns: Completed packet transmission to MAC |
# 28940 ns: Starting packet transmission to MAC, size = 68 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 86 78 |
# 7e db cf 79 fa 61 17 a1 86 50 f5 35 29 c1 c5 98 |
# 4b 73 ec 8a 4e a8 a9 a1 0e e6 9f 2a 2a 8d 9e 38 |
# 79 c8 ca 13 6b c7 b6 ba c4 b9 92 b4 7f 86 fa f2 |
# d8 8a 95 46 |
# **** |
# 35020 ns: Completed packet transmission to MAC |
# 36060 ns: Starting packet transmission to MAC, size = 69 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 32 bd |
# 84 e4 ca a9 a1 8e fb 0b ef c9 36 75 8f 6b 88 ae |
# 9b 92 28 2d 4b c2 1e 0d ec 18 d1 86 41 3b d8 53 |
# 56 5b e2 04 73 d8 12 b8 39 e5 a1 2b 81 c8 27 a1 |
# 1f dd 21 ca 31 |
# **** |
# 42220 ns: Completed packet transmission to MAC |
# 43260 ns: Starting packet transmission to MAC, size = 70 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 04 58 |
# 96 14 12 96 b1 55 ed 2b f5 ad 27 84 a7 e7 b9 49 |
# db c9 51 a1 2a fa 45 83 7c 72 fe 68 6f 86 f0 38 |
# 40 28 f6 c5 c0 74 39 b0 3c 2a 62 15 e1 17 43 c9 |
# 86 25 ec 93 f7 b6 |
# **** |
# 49500 ns: Completed packet transmission to MAC |
# 50540 ns: Starting packet transmission to MAC, size = 71 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 c1 8d |
# 5a 07 2c 0c 71 3b b6 f7 9e 5c 55 20 a0 72 b4 dd |
# 0d 4b 79 9e fd 7b 8f 03 e3 1d b1 44 95 e0 ed 52 |
# f8 8d 52 84 46 8c 90 17 6a 84 aa 7c 60 ba 8b a6 |
# 25 32 a2 b2 82 de 56 |
# **** |
# 56860 ns: Completed packet transmission to MAC |
# 57900 ns: Starting packet transmission to MAC, size = 72 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 49 14 |
# 3d 4b 5c 47 86 39 b4 d0 2c 8c 07 6a 11 e8 4b 73 |
# ec 23 a4 c9 39 df d4 67 9d b0 82 49 d9 20 1c 93 |
# e3 2a c8 5d 3a 84 2b 39 12 52 59 d0 6e 97 db a6 |
# bb 00 0f 69 16 8d 9c 08 |
# **** |
# 64300 ns: Completed packet transmission to MAC |
# 65340 ns: Starting packet transmission to MAC, size = 73 |
# SA = 12:34:56:78:9a:bc, DA = 16:22:33:44:55:66, type/length = 0700 |
# Contents: |
# 16 22 33 44 55 66 12 34 56 78 9a bc 07 00 0c 59 |
# c5 cf 90 51 69 77 4a d8 9b c4 b8 b7 86 30 77 b5 |
# d4 07 76 e9 8b 01 db 80 c2 c5 30 af 66 af e9 f8 |
# 06 ef e1 95 ee 60 e5 28 64 29 e1 77 6e 81 d5 68 |
# f0 aa 0f f1 7d 1f 08 38 e7 |
# **** |
# 71820 ns: Completed packet transmission to MAC |
# Status: End of Waiting Delay Loop |
############################# |
# TB MII Statistic |
# TB TO DUT : |
# Frm cnt : 10 |
# Byte cnt : 685 |
# DUT TO TB : |
# Frm cnt : 0 |
# Byte cnt : 0 |
# Pause Frm cnt: 0 |
# Alig Err cnt: 0 |
# usized Err cnt: 0 |
# crc Err cnt: 0 |
# Length Err cnt: 0 |
############################# |
# A200 TB => 171820 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected 1 |
# A200 TB => 171820 ns ERROR :: tb_top.tb_glbl.test_err ERROR detected 2 |
# |
# ------------------------------------------------- |
# Test Status |
# warnings: 0, errors: 2 |
# |
# ------------------------------------------------- |
# Test Status |
# warnings: 0, errors: 2 |
# |
# ========= |
# Test Status: TEST FAILED |
# ========= |
# |
# ** Note: $finish : ../lib/tb_glbl.v(70) |
# Time: 172821 ps Iteration: 0 Instance: /tb_top |
# End time: 19:19:13 on Aug 18,2022, Elapsed time: 0:00:02 |
# Errors: 2, Warnings: 18 |
/verif/run/dat/oc8051_xrom.in
1,257 → 1,248
02 |
00 |
08 |
12 |
00 |
64 |
80 |
FE |
75 |
81 |
07 |
12 |
00 |
E3 |
E5 |
82 |
60 |
03 |
02 |
00 |
03 |
79 |
00 |
E9 |
44 |
00 |
60 |
1B |
7A |
00 |
90 |
00 |
E7 |
78 |
00 |
75 |
A0 |
08 |
E4 |
93 |
F2 |
A3 |
08 |
B8 |
00 |
02 |
05 |
A0 |
D9 |
F4 |
DA |
F2 |
75 |
A0 |
FF |
E4 |
78 |
FF |
F6 |
D8 |
FD |
78 |
00 |
E8 |
44 |
00 |
60 |
0A |
79 |
00 |
75 |
A0 |
00 |
E4 |
F3 |
09 |
D8 |
FC |
78 |
00 |
E8 |
44 |
08 |
60 |
0C |
79 |
08 |
90 |
00 |
00 |
E4 |
F0 |
A3 |
D8 |
FC |
D9 |
FA |
02 |
00 |
03 |
90 |
00 |
00 |
74 |
01 |
F0 |
7A |
01 |
7B |
00 |
74 |
F8 |
2B |
40 |
2A |
EA |
24 |
00 |
FC |
EB |
34 |
00 |
FD |
EA |
24 |
FF |
FE |
EB |
34 |
FF |
FF |
EE |
24 |
00 |
F5 |
82 |
EF |
34 |
00 |
F5 |
83 |
E0 |
FE |
0E |
8C |
82 |
8D |
83 |
EE |
F0 |
0A |
BA |
00 |
D4 |
0B |
80 |
D1 |
7A |
00 |
7B |
00 |
7C |
00 |
74 |
F8 |
2C |
40 |
29 |
EB |
24 |
00 |
F5 |
82 |
EC |
34 |
00 |
F5 |
83 |
E0 |
FD |
74 |
01 |
2B |
FE |
E4 |
3C |
E4 |
FF |
F8 |
ED |
B5 |
06 |
06 |
E8 |
B5 |
07 |
02 |
80 |
03 |
0A |
8A |
80 |
0B |
BB |
00 |
D5 |
0C |
80 |
D2 |
EA |
60 |
07 |
75 |
A0 |
55 |
8A |
B0 |
80 |
06 |
75 |
A0 |
AA |
75 |
B0 |
AA |
80 |
FE |
75 |
82 |
00 |
22 |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
FF |
/// |
/// created by oc8051 rom maker |
/// author: Simon Teran (simont@opencores.org) |
/// |
/// source file: D:\gmac_loopback.hex |
/// date: 5/6/2011 |
/// time: 4:47:40 PM |
/// |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
00 |
02 |
00 |
18 |
12 |
00 |
74 |
80 |
FE |
75 |
81 |
31 |
12 |
00 |
EC |
E5 |
82 |
60 |
03 |
02 |
00 |
13 |
79 |
00 |
E9 |
44 |
00 |
60 |
1B |
7A |
00 |
90 |
00 |
F0 |
78 |
07 |
75 |
A0 |
00 |
E4 |
93 |
F2 |
A3 |
08 |
B8 |
00 |
02 |
05 |
A0 |
D9 |
F4 |
DA |
F2 |
75 |
A0 |
FF |
E4 |
78 |
FF |
F6 |
D8 |
FD |
78 |
00 |
E8 |
44 |
00 |
60 |
0A |
79 |
00 |
75 |
A0 |
00 |
E4 |
F3 |
09 |
D8 |
FC |
78 |
07 |
E8 |
44 |
00 |
60 |
0C |
79 |
01 |
90 |
00 |
00 |
E4 |
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A3 |
D8 |
FC |
D9 |
FA |
02 |
00 |
13 |
90 |
00 |
05 |
E4 |
F0 |
A3 |
F0 |
E4 |
F5 |
30 |
F5 |
31 |
90 |
A0 |
30 |
E0 |
FC |
A3 |
E0 |
FD |
EC |
54 |
0F |
60 |
F3 |
90 |
00 |
05 |
E0 |
FC |
A3 |
E0 |
FD |
8C |
06 |
74 |
70 |
4D |
FF |
90 |
00 |
01 |
EE |
F0 |
A3 |
EF |
F0 |
74 |
40 |
4C |
F8 |
74 |
70 |
4D |
F9 |
90 |
00 |
03 |
E8 |
F0 |
A3 |
E9 |
F0 |
8E |
82 |
8F |
83 |
E0 |
FE |
A3 |
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FF |
A3 |
E0 |
FA |
A3 |
E0 |
FB |
88 |
82 |
89 |
83 |
EE |
F0 |
A3 |
EF |
F0 |
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EA |
F0 |
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EB |
F0 |
74 |
04 |
2C |
FC |
E4 |
3D |
FD |
90 |
00 |
05 |
74 |
3F |
5C |
F0 |
A3 |
E4 |
F0 |
05 |
30 |
E4 |
B5 |
30 |
98 |
05 |
31 |
80 |
94 |
75 |
82 |
00 |
22 |