Subversion Repositories turbo8051

/trunk/rtl/lib/clk_ctl.v

/trunk/rtl/lib/toggle_sync.v

trunk/rtl/lib/toggle_sync.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/lib/async_fifo.v =================================================================== --- trunk/rtl/lib/async_fifo.v (nonexistent) +++ trunk/rtl/lib/async_fifo.v (revision 11) @@ -0,0 +1,384 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +//------------------------------------------- +// async_fifo:: async FIFO +// Basic RTL is ported from p600 async_fifo.v +// Following two ports are newly added +// 1. At write clock domain: +// wr_total_free_space --> Indicate total free transfer available +// 2. At read clock domain: +// rd_total_aval --> Indicate total no of transfer available +//----------------------------------------------- + +module async_fifo (wr_clk, + wr_reset_n, + wr_en, + wr_data, + full, // sync'ed to wr_clk + afull, // sync'ed to wr_clk + wr_total_free_space, + rd_clk, + rd_reset_n, + rd_en, + empty, // sync'ed to rd_clk + aempty, // sync'ed to rd_clk + rd_total_aval, + rd_data); + + parameter W = 4'd8; + parameter DP = 3'd4; + parameter WR_FAST = 1'b1; + parameter RD_FAST = 1'b1; + parameter FULL_DP = DP; + parameter EMPTY_DP = 1'b0; + + parameter AW = (DP == 2) ? 1 : + (DP == 4) ? 2 : + (DP == 8) ? 3 : + (DP == 16) ? 4 : + (DP == 32) ? 5 : + (DP == 64) ? 6 : + (DP == 128) ? 7 : + (DP == 256) ? 8 : 0; + + output [W-1 : 0] rd_data; + input [W-1 : 0] wr_data; + input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n, + rd_en; + output full, empty; + output afull, aempty; // about full and about to empty + output [AW:0] wr_total_free_space; // Total Number of free space aval + // w.r.t write clk + // note: Without accounting byte enables + output [AW:0] rd_total_aval; // Total Number of words avaialble + // w.r.t rd clock, + // note: Without accounting byte enables + // synopsys translate_off + + initial begin + if (AW == 0) begin + $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP); + end // if (AW == 0) + end // initial begin + + // synopsys translate_on + reg [W-1 : 0] mem[DP-1 : 0]; + + /*********************** write side ************************/ + reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1; + wire [AW:0] sync_rd_ptr; + reg [AW:0] wr_ptr, grey_wr_ptr; + reg [AW:0] grey_rd_ptr; + reg full_q; + wire full_c; + wire afull_c; + wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1; + wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr); + + assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0; + assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0; + + //-------------------------- + // Shows total number of words + // of free space available w.r.t write clock + //--------------------------- + assign wr_total_free_space = FULL_DP - wr_cnt; + + always @(posedge wr_clk or negedge wr_reset_n) begin + if (!wr_reset_n) begin + wr_ptr <= 0; + grey_wr_ptr <= 0; + full_q <= 0; + end + else if (wr_en) begin + wr_ptr <= wr_ptr_inc; + grey_wr_ptr <= bin2grey(wr_ptr_inc); + if (wr_cnt == (FULL_DP-1)) begin + full_q <= 1'b1; + end + end + else begin + if (full_q && (wr_cnt= rd_ptr) begin + get_cnt = (wr_ptr - rd_ptr); + end + else begin + get_cnt = DP*2 - (rd_ptr - wr_ptr); + end +end +endfunction + +// synopsys translate_off +always @(posedge wr_clk) begin + if (wr_en && full) begin + $display($time, "%m Error! afifo overflow!"); + $stop; + end +end + +always @(posedge rd_clk) begin + if (rd_en && empty) begin + $display($time, "%m error! afifo underflow!"); + $stop; + end +end + +// gray code monitor +reg [AW:0] last_gwr_ptr; +always @(posedge wr_clk or negedge wr_reset_n) begin + if (!wr_reset_n) begin + last_gwr_ptr <= #1 0; + end + else if (last_gwr_ptr !== grey_wr_ptr) begin + check_ptr_chg(last_gwr_ptr, grey_wr_ptr); + last_gwr_ptr <= #1 grey_wr_ptr; + end +end + +reg [AW:0] last_grd_ptr; +always @(posedge rd_clk or negedge rd_reset_n) begin + if (!rd_reset_n) begin + last_grd_ptr <= #1 0; + end + else if (last_grd_ptr !== grey_rd_ptr) begin + check_ptr_chg(last_grd_ptr, grey_rd_ptr); + last_grd_ptr <= #1 grey_rd_ptr; + end +end + +task check_ptr_chg; +input [AW:0] last_ptr; +input [AW:0] cur_ptr; +integer i; +integer ptr_diff; +begin + ptr_diff = 0; + for (i=0; i<= AW; i=i+ 1'b1) begin + if (last_ptr[i] != cur_ptr[i]) begin + ptr_diff = ptr_diff + 1'b1; + end + end + if (ptr_diff !== 1) begin + $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h", + last_ptr, cur_ptr); + $stop; + end +end +endtask + // synopsys translate_on + +endmodule

trunk/rtl/lib/async_fifo.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/lib/dble_reg.v =================================================================== --- trunk/rtl/lib/dble_reg.v (nonexistent) +++ trunk/rtl/lib/dble_reg.v (revision 11) @@ -0,0 +1,91 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +/*************************************************************** + Description: + Synchronizes the pulse from one clock to another + * clock domain +***********************************************************************/ +//`timescale 1ns/100ps +module half_dup_dble_reg ( + //outputs + sync_out_pulse, + //inputs + in_pulse, + dest_clk, + reset_n); + + output sync_out_pulse; //output synchronised to slow clock + input in_pulse; //input based on fast clock, pulse + input dest_clk; //slow clock + input reset_n; + + reg s1_sync_out,d_sync_out,s2_sync_out; + + //double register the data in the slow clock domain + always @(posedge dest_clk or negedge reset_n) + begin + if (!reset_n) + begin + s1_sync_out <= 0; + s2_sync_out <= 0; + d_sync_out <= 0; + end // if (reset_n) + else + begin + s1_sync_out <= in_pulse; + s2_sync_out <= s1_sync_out; + d_sync_out <= s2_sync_out; + end // else: !if(reset_n) + end // always @ (posedge dest_clk or negedge reset_n) + + assign sync_out_pulse = d_sync_out; + +endmodule // dble_reg + + + + + +

trunk/rtl/lib/dble_reg.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/lib/double_sync_high.v =================================================================== --- trunk/rtl/lib/double_sync_high.v (nonexistent) +++ trunk/rtl/lib/double_sync_high.v (revision 11) @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +//---------------------------------------------------------------------------- +// Simple Double sync logic with Reset value = 0 +// This double signal should be used for signal transiting from low to high +//---------------------------------------------------------------------------- + +module double_sync_high ( + in_data , + out_clk , + out_rst_n , + out_data + ); + +parameter WIDTH = 1; + +input [WIDTH-1:0] in_data ; // Input from Different clock domain +input out_clk ; // Output clock +input out_rst_n ; // Active low Reset +output[WIDTH-1:0] out_data ; // Output Data + + +reg [WIDTH-1:0] in_data_s ; // One Cycle sync +reg [WIDTH-1:0] in_data_2s ; // two Cycle sync +reg [WIDTH-1:0] in_data_3s ; // three Cycle sync + +assign out_data = in_data_3s; + +always @(negedge out_rst_n or posedge out_clk) +begin + if(out_rst_n == 1'b0) + begin + in_data_s <= {WIDTH{1'b0}}; + in_data_2s <= {WIDTH{1'b0}}; + in_data_3s <= {WIDTH{1'b0}}; + end + else + begin + in_data_s <= in_data; + in_data_2s <= in_data_s; + in_data_3s <= in_data_2s; + end +end + + +endmodule Index: trunk/rtl/lib/sfifo.v =================================================================== --- trunk/rtl/lib/sfifo.v (nonexistent) +++ trunk/rtl/lib/sfifo.v (revision 11) @@ -0,0 +1,75 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module sfifo (QA,CLKA,CENA,AA,CLKB,CENB,AB,DB); + +parameter DW = 10; // Data Width +parameter AW = 5; // Address Width +parameter FW = 32; // FIFO DEPTH + +output [DW-1:0] QA; + +input CLKA; +input CENA; +input [AW-1:0] AA; +input CLKB; +input CENB; +input [AW-1:0] AB; +input [DW-1:0] DB; + +reg [DW-1:0] QA; +reg [DW-1:0] ram [FW-1:0]; + +always @ (posedge CLKB) +begin + if (!CENB) + ram[AB] <= DB; +end + +always @ (posedge CLKA) +begin + if (!CENA) + QA <= ram[AA]; +end + +endmodule Index: trunk/rtl/lib/wb_crossbar.v =================================================================== --- trunk/rtl/lib/wb_crossbar.v (nonexistent) +++ trunk/rtl/lib/wb_crossbar.v (revision 11) @@ -0,0 +1,380 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +/********************************************** + Web-bone cross bar M-Master By S-Slave +**********************************************/ + +module wb_crossbar ( + + rst_n , + clk , + + + // Master Interface Signal + wbd_taddr_master , + wbd_din_master , + wbd_dout_master , + wbd_adr_master , + wbd_be_master , + wbd_we_master , + wbd_ack_master , + wbd_stb_master , + wbd_cyc_master , + wbd_err_master , + wbd_rty_master , + + // Slave Interface Signal + wbd_din_slave , + wbd_dout_slave , + wbd_adr_slave , + wbd_be_slave , + wbd_we_slave , + wbd_ack_slave , + wbd_stb_slave , + wbd_cyc_slave , + wbd_err_slave , + wbd_rty_slave + ); + +parameter WB_SLAVE = 4 ; +parameter WB_MASTER = 4 ; + +parameter D_WD = 16; // Data Width +parameter BE_WD = 2; // Byte Enable +parameter ADR_WD = 28; // Address Width +parameter TAR_WD = 4; // Target Width + +input clk; // CLK_I The clock input [CLK_I] coordinates all activities + // for the internal logic within the WISHBONE interconnect. + // All WISHBONE output signals are registered at the + // rising edge of [CLK_I]. + // All WISHBONE input signals must be stable before the + // rising edge of [CLK_I]. +input rst_n; // RST_I The reset input [RST_I] forces the WISHBONE interface + // to restart. Furthermore, all internal self-starting state + // machines will be forced into an initial state. + +input [(WB_MASTER *TAR_WD)-1:0] wbd_taddr_master; // target address from master +input [WB_MASTER-1:0] wbd_stb_master; + // STB_O The strobe output [STB_O] indicates a valid data + // transfer cycle. It is used to qualify various other signals + // on the interface such as [SEL_O(7..0)]. The SLAVE must + // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in + // response to every assertion of the [STB_O] signal. +output [WB_SLAVE-1:0] wbd_stb_slave; + // STB_O The strobe output [STB_O] indicates a valid data + // transfer cycle. It is used to qualify various other signals + // on the interface such as [SEL_O(7..0)]. The SLAVE must + // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in + // response to every assertion of the [STB_O] signal. + +input [WB_MASTER-1:0] wbd_we_master; + // WE_O The write enable output [WE_O] indicates whether the + // current local bus cycle is a READ or WRITE cycle. The + // signal is negated during READ cycles, and is asserted + // during WRITE cycles. +output [WB_SLAVE-1:0] wbd_we_slave; + // WE_O The write enable output [WE_O] indicates whether the + // current local bus cycle is a READ or WRITE cycle. The + // signal is negated during READ cycles, and is asserted + // during WRITE cycles. + +output [WB_MASTER-1:0] wbd_ack_master; + // The acknowledge input [ACK_I], when asserted, + // indicates the termination of a normal bus cycle. + // Also see the [ERR_I] and [RTY_I] signal descriptions. +input [WB_SLAVE-1:0] wbd_ack_slave; + // The acknowledge input [ACK_I], when asserted, + // indicates the termination of a normal bus cycle. + // Also see the [ERR_I] and [RTY_I] signal descriptions. + +input [(WB_MASTER *ADR_WD)-1:0] wbd_adr_master; + // The address output array [ADR_O(63..0)] is used + // to pass a binary address, with the most significant + // address bit at the higher numbered end of the signal array. + // The lower array boundary is specific to the data port size. + // The higher array boundary is core-specific. + // In some cases (such as FIFO interfaces) + // the array may not be present on the interface. + +output [(WB_SLAVE *ADR_WD)-1:0] wbd_adr_slave; + // The address output array [ADR_O(63..0)] is used + // to pass a binary address, with the most significant + // address bit at the higher numbered end of the signal array. + // The lower array boundary is specific to the data port size. + // The higher array boundary is core-specific. + // In some cases (such as FIFO interfaces) + // the array may not be present on the interface. + +input [(WB_MASTER * BE_WD)-1:0] wbd_be_master; // Byte Enable + // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates + // where valid data is expected on the [DAT_I(63..0)] signal + // array during READ cycles, and where it is placed on the + // [DAT_O(63..0)] signal array during WRITE cycles. + // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O] + // signal descriptions. +input [(WB_SLAVE * BE_WD)-1:0] wbd_be_slave; // Byte Enable + // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates + // where valid data is expected on the [DAT_I(63..0)] signal + // array during READ cycles, and where it is placed on the + // [DAT_O(63..0)] signal array during WRITE cycles. + // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O] + // signal descriptions. + +input [WB_SLAVE -1:0] wbd_cyc_master; + // CYC_O The cycle output [CYC_O], when asserted, + // indicates that a valid bus cycle is in progress. + // The signal is asserted for the duration of all bus cycles. + // For example, during a BLOCK transfer cycle there can be + // multiple data transfers. The [CYC_O] signal is asserted + // during the first data transfer, and remains asserted + // until the last data transfer. The [CYC_O] signal is useful + // for interfaces with multi-port interfaces + // (such as dual port memories). In these cases, + // the [CYC_O] signal requests use of a common bus from an + // arbiter. Once the arbiter grants the bus to the MASTER, + // it is held until [CYC_O] is negated. +output [WB_SLAVE -1:0] wbd_cyc_slave; + // CYC_O The cycle output [CYC_O], when asserted, + // indicates that a valid bus cycle is in progress. + // The signal is asserted for the duration of all bus cycles. + // For example, during a BLOCK transfer cycle there can be + // multiple data transfers. The [CYC_O] signal is asserted + // during the first data transfer, and remains asserted + // until the last data transfer. The [CYC_O] signal is useful + // for interfaces with multi-port interfaces + // (such as dual port memories). In these cases, + // the [CYC_O] signal requests use of a common bus from an + // arbiter. Once the arbiter grants the bus to the MASTER, + // it is held until [CYC_O] is negated. + +input [(WB_MASTER * D_WD)-1:0] wbd_din_master; + // DAT_I(63..0) The data input array [DAT_I(63..0)] is + // used to pass binary data. The array boundaries are + // determined by the port size. Also see the [DAT_O(63..0)] + // and [SEL_O(7..0)] signal descriptions. + +output [(WB_SLAVE * D_WD)-1:0] wbd_din_slave; + // DAT_I(63..0) The data input array [DAT_I(63..0)] is + // used to pass binary data. The array boundaries are + // determined by the port size. Also see the [DAT_O(63..0)] + // and [SEL_O(7..0)] signal descriptions. + +output [(WB_MASTER * D_WD)-1:0] wbd_dout_master; + // DAT_O(63..0) The data output array [DAT_O(63..0)] is + // used to pass binary data. The array boundaries are + // determined by the port size. Also see the [DAT_I(63..0)] + // and [SEL_O(7..0)] signal descriptions. +input [(WB_SLAVE * D_WD)-1:0] wbd_dout_slave; + // DAT_O(63..0) The data output array [DAT_O(63..0)] is + // used to pass binary data. The array boundaries are + // determined by the port size. Also see the [DAT_I(63..0)] + // and [SEL_O(7..0)] signal descriptions. + +output [WB_MASTER -1:0] wbd_err_master; + // ERR_I The error input [ERR_I] indicates an abnormal + // cycle termination. The source of the error, and the + // response generated by the MASTER is defined by the IP core + // supplier in the WISHBONE DATASHEET. Also see the [ACK_I] + // and [RTY_I] signal descriptions. +input [WB_SLAVE -1:0] wbd_err_slave; + // ERR_I The error input [ERR_I] indicates an abnormal + // cycle termination. The source of the error, and the + // response generated by the MASTER is defined by the IP core + // supplier in the WISHBONE DATASHEET. Also see the [ACK_I] + // and [RTY_I] signal descriptions. + +output [WB_MASTER -1:0] wbd_rty_master; + // RTY_I The retry input [RTY_I] indicates that the indicates + // that the interface is not ready to accept or send data, and + // that the cycle should be retried. When and how the cycle is + // retried is defined by the IP core supplier in the WISHBONE + // DATASHEET. Also see the [ERR_I] and [RTY_I] signal + // descriptions. +input [WB_SLAVE -1:0] wbd_rty_slave; + // RTY_I The retry input [RTY_I] indicates that the indicates + // that the interface is not ready to accept or send data, and + // that the cycle should be retried. When and how the cycle is + // retried is defined by the IP core supplier in the WISHBONE + // DATASHEET. Also see the [ERR_I] and [RTY_I] signal + // descriptions. + + +reg [WB_MASTER-1:0] wbd_ack_master; +reg [WB_MASTER-1:0] wbd_err_master; +reg [WB_MASTER-1:0] wbd_rty_master; + + +reg [WB_MASTER-1:0] master_busy; // master busy flag +reg [WB_SLAVE-1:0] slave_busy; // slave busy flag +reg [TAR_WD -1:0] master_mx_id[WB_MASTER-1:0]; +reg [TAR_WD -1:0] slave_mx_id [WB_SLAVE-1:0]; + +reg [TAR_WD-1 :0] cur_target_id; +wire [TAR_WD-1:0] wbd_taddr_master_t[WB_MASTER]; // target address from master +wire [D_WD-1:0] wbd_din_master_t[WB_MASTER-1:0]; // target address from master +reg [D_WD-1:0] wbd_dout_master_t[WB_MASTER-1:0]; // target address from master +wire [ADR_WD-1:0] wbd_adr_master_t[WB_MASTER-1:0]; // target address from master +wire [BE_WD-1:0] wbd_be_master_t[WB_MASTER-1:0]; // target address from master + + +reg [WB_SLAVE-1:0] wbd_stb_slave; +reg [WB_SLAVE-1:0] wbd_we_slave; +reg [WB_SLAVE-1:0] wbd_cyc_slave; +wire [D_WD-1:0] wbd_dout_slave_t[WB_SLAVE-1:0]; // target data towards master + + +reg [D_WD-1:0] wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master +reg [ADR_WD-1:0] wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master +reg [BE_WD-1:0] wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master + +integer i,k,l; + + +/********************************************************** + Re-Arraging the array in seperate two dimensional information +***********************************************************/ + +genvar j,m; +generate + + // Connect the Master Mux + for(j=0; j < WB_MASTER ; j = j + 1) begin : master_expand + assign wbd_taddr_master_t[j] = wbd_taddr_master[((j+1)*TAR_WD)-1:j * TAR_WD]; + assign wbd_din_master_t[j] = wbd_din_master[((j+1)*D_WD)-1:j * D_WD]; + assign wbd_adr_master_t[j] = wbd_adr_master[((j+1)*ADR_WD)-1:j * ADR_WD]; + assign wbd_be_master_t[j] = wbd_be_master[((j+1)*BE_WD)-1:j * BE_WD]; + + assign wbd_dout_master[((j+1)*D_WD)-1:j * D_WD] = wbd_dout_master_t[j]; + end + + // Connect the Slave Mux + for(m=0; m < WB_SLAVE ; m = m + 1) begin : slave_expand + assign wbd_din_slave[((m+1)*D_WD)-1:m * D_WD] = wbd_din_slave_t[m]; + assign wbd_adr_slave[((m+1)*ADR_WD)-1:m * ADR_WD] = wbd_adr_slave_t[m]; + assign wbd_be_slave[((m+1)*BE_WD)-1:m * BE_WD] = wbd_be_slave_t[m]; + + assign wbd_dout_slave_t[m] = wbd_dout_slave[((m+1)*D_WD)-1:m * D_WD]; + + end +endgenerate + +always @* begin + for(k = 0; k < WB_MASTER; k = k + 1) begin + if(master_busy[k] == 1) begin + wbd_dout_master_t[k] = wbd_dout_slave_t[master_mx_id[k]]; + wbd_ack_master[k] = wbd_ack_slave[master_mx_id[k]]; + wbd_err_master[k] = wbd_err_slave[master_mx_id[k]]; + wbd_rty_master[k] = wbd_rty_slave[master_mx_id[k]]; + end else begin + wbd_dout_master_t[k] = 0; + wbd_ack_master[k] = 0; + wbd_err_master[k] = 0; + wbd_rty_master[k] = 0; + end + end + for(l = 0; l < WB_SLAVE; l = l + 1) begin + if(slave_busy[l] == 1) begin + wbd_din_slave_t[l] = wbd_din_master_t[slave_mx_id[l]]; + wbd_adr_slave_t[l] = wbd_adr_master_t[slave_mx_id[l]]; + wbd_be_slave_t[l] = wbd_be_master_t[slave_mx_id[l]]; + wbd_stb_slave[l] = wbd_stb_master[slave_mx_id[l]]; + wbd_we_slave[l] = wbd_we_master[slave_mx_id[l]]; + wbd_cyc_slave[l] = wbd_cyc_master[slave_mx_id[l]]; + end else begin + wbd_din_slave_t[l] = 0; + wbd_adr_slave_t[l] = 0; + wbd_be_slave_t[l] = 0; + wbd_stb_slave[l] = 0; + wbd_we_slave[l] = 0; + wbd_cyc_slave[l] = 0; + end + end +end + +/******************************************************* + Parsing through the master and deciding on mux connectio + Step-1: analysis the master from 0 to total master + Step-2: If the previously master is not busy, + Then check for any new request from the master and + check corresponding slave is free or not. If there is + master request and requesting slave is free. + Then set the master max id to slave id & + requesting slave to master number & set the master + and slave busy flag + Step-3: If the previous state of master is busy and bus-cycle + is de-asserted, then reset the master and corresponding + slave busy flag + +*********************************************************/ + +always @(negedge rst_n or posedge clk) begin + if(rst_n == 0) begin + master_busy <= 0; + slave_busy <= 0; + end + else begin + for(i = 0; i < WB_MASTER; i = i + 1) begin + cur_target_id = wbd_taddr_master_t[i]; + if(master_busy[i] == 0) begin + if(wbd_stb_master[i] & slave_busy[cur_target_id] == 0) begin + master_mx_id[i] = cur_target_id; + slave_mx_id [cur_target_id] = i; + slave_busy[cur_target_id] = 1; + master_busy[i] = 1; + // synopsys translate_off + $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,cur_target_id); + // synopsys translate_on + end + end else if(wbd_cyc_master[i] == 0) begin + master_busy[i] = 0; + slave_busy[cur_target_id] = 0; + end + end + end +end + + + +endmodule Index: trunk/rtl/lib/double_sync_low.v =================================================================== --- trunk/rtl/lib/double_sync_low.v (nonexistent) +++ trunk/rtl/lib/double_sync_low.v (revision 11) @@ -0,0 +1,86 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +//---------------------------------------------------------------------------- +// Simple Double sync logic with Reset value = 1 +// This double signal should be used for signal transiting from low to high +//---------------------------------------------------------------------------- + +module double_sync_low ( + in_data , + out_clk , + out_rst_n , + out_data + ); + +parameter WIDTH = 1; + +input [WIDTH-1:0] in_data ; // Input from Different clock domain +input out_clk ; // Output clock +input out_rst_n ; // Active low Reset +output[WIDTH-1:0] out_data ; // Output Data + + +reg [WIDTH-1:0] in_data_s ; // One Cycle sync +reg [WIDTH-1:0] in_data_2s ; // two Cycle sync +reg [WIDTH-1:0] in_data_3s ; // three Cycle sync + +assign out_data = in_data_3s; + +always @(negedge out_rst_n or posedge out_clk) +begin + if(out_rst_n == 1'b0) + begin + in_data_s <= {WIDTH{1'b1}}; + in_data_2s <= {WIDTH{1'b1}}; + in_data_3s <= {WIDTH{1'b1}}; + end + else + begin + in_data_s <= in_data; + in_data_2s <= in_data_s; + in_data_3s <= in_data_2s; + end +end + + +endmodule Index: trunk/rtl/lib/registers.v =================================================================== --- trunk/rtl/lib/registers.v (nonexistent) +++ trunk/rtl/lib/registers.v (revision 11) @@ -0,0 +1,276 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +//`timescale 1ns/100ps + +/********************************************************************* +** module: bit register + +** description: infers a register, make it modular + ***********************************************************************/ +module bit_register ( + //inputs + we, + clk, + reset_n, + data_in, + + //outputs + data_out + ); + +//--------------------------------- +// Reset Default value +//--------------------------------- +parameter RESET_DEFAULT = 1'h0; + + input we; + input clk; + input reset_n; + input data_in; + output data_out; + + reg data_out; + + //infer the register + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + data_out <= RESET_DEFAULT; + else if (we) + data_out <= data_in; + end // always @ (posedge clk or negedge reset_n) +endmodule // register + + +/********************************************************************* +** module: req register. + +** description: This register is set by cpu writting 1 and reset by + harward req = 1 + + Note: When there is a clash between cpu and hardware, cpu is given higher + priority + + ***********************************************************************/ +module req_register ( + //inputs + clk, + reset_n, + cpu_we, + cpu_req, + hware_ack, + + //outputs + data_out + ); + +//--------------------------------- +// Reset Default value +//--------------------------------- +parameter RESET_DEFAULT = 1'h0; + + input clk ; + input reset_n ; + input cpu_we ; // cpu write enable + input cpu_req ; // CPU Request + input hware_ack; // Hardware Ack + output data_out ; + + reg data_out; + + //infer the register + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + data_out <= RESET_DEFAULT; + else if (cpu_we & cpu_req) // Set on CPU Request + data_out <= 1'b1; + else if (hware_ack) // Reset the flag on Hardware ack + data_out <= 1'b0; + end // always @ (posedge clk or negedge reset_n) +endmodule // register + + +/********************************************************************* +** module: req register. + +** description: This register is cleared by cpu writting 1 and set by + harward req = 1 + + Note: When there is a clash between cpu and hardware, + hardware is given higher priority + + ***********************************************************************/ +module stat_register ( + //inputs + clk, + reset_n, + cpu_we, + cpu_ack, + hware_req, + + //outputs + data_out + ); + +//--------------------------------- +// Reset Default value +//--------------------------------- +parameter RESET_DEFAULT = 1'h0; + + input clk ; + input reset_n ; + input cpu_we ; // cpu write enable + input cpu_ack ; // CPU Ack + input hware_req; // Hardware Req + output data_out ; + + reg data_out; + + //infer the register + always @(posedge clk or negedge reset_n) + begin + if (!reset_n) + data_out <= RESET_DEFAULT; + else if (hware_req) // Set the flag on Hardware Req + data_out <= 1'b1; + else if (cpu_we & cpu_ack) // Clear on CPU Ack + data_out <= 1'b0; + end // always @ (posedge clk or negedge reset_n) +endmodule // register + + + + + +/********************************************************************* +** copyright message here. + +** module: generic register + +***********************************************************************/ +module generic_register ( + //List of Inputs + we, + data_in, + reset_n, + clk, + + //List of Outs + data_out + ); + + parameter WD = 1; + parameter RESET_DEFAULT = 0; + input [WD-1:0] we; + input [WD-1:0] data_in; + input reset_n; + input clk; + output [WD-1:0] data_out; + + +generate + genvar i; + for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg + bit_register #(RESET_DEFAULT[i]) u_bit_reg ( + .we (we[i]), + .clk (clk), + .reset_n (reset_n), + .data_in (data_in[i]), + .data_out (data_out[i]) + ); + end +endgenerate + + +endmodule + + +/********************************************************************* +** copyright message here. + +** module: generic register + +***********************************************************************/ +module generic_intr_stat_reg ( + //inputs + clk, + reset_n, + reg_we, + reg_din, + hware_req, + + //outputs + data_out + ); + + parameter WD = 1; + parameter RESET_DEFAULT = 0; + input [WD-1:0] reg_we; + input [WD-1:0] reg_din; + input [WD-1:0] hware_req; + input reset_n; + input clk; + output [WD-1:0] data_out; + + +generate + genvar i; + for (i = 0; i < WD; i = i + 1) begin : gen_bit_reg + stat_register #(RESET_DEFAULT[i]) u_bit_reg ( + //inputs + . clk (clk ), + . reset_n (reset_n ), + . cpu_we (reg_we[i] ), + . cpu_ack (reg_din[i] ), + . hware_req (hware_req[i] ), + + //outputs + . data_out (data_out[i] ) + ); + + end +endgenerate + + +endmodule

trunk/rtl/lib/registers.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/lib/wb_interface.v =================================================================== --- trunk/rtl/lib/wb_interface.v (nonexistent) +++ trunk/rtl/lib/wb_interface.v (revision 11) @@ -0,0 +1,382 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module wb_interface ( + rst , + clk , + + dma_req_i , + dma_write_i , + dma_addr_i , + dma_length_i , + dma_ack_o , + dma_done_o , + + dma_start_o , + dma_wr_o , + dma_rd_o , + dma_last_o , + dma_wdata_i , + dma_rdata_o , + + // external memory + wbd_dat_i , + wbd_dat_o , + wbd_adr_o , + wbd_be_o , + wbd_we_o , + wbd_ack_i , + wbd_stb_o , + wbd_cyc_o , + wbd_err_i + + + ); + + + +input rst ; +input clk ; + +input dma_req_i ; +input dma_write_i ; +input [25:0] dma_addr_i ; +input [7:0] dma_length_i ; +output dma_ack_o ; +output dma_done_o ; // indicates end of DMA transaction + +output dma_start_o ; +output dma_wr_o ; +output dma_rd_o ; +output dma_last_o ; +input [31:0] dma_wdata_i ; +output [31:0] dma_rdata_o ; + +//-------------------------------- +// WB interface +//-------------------------------- +input [31:0] wbd_dat_i ; // data input +output [31:0] wbd_dat_o ; // data output +output [23:0] wbd_adr_o ; // address +output [3:0] wbd_be_o ; // byte enable +output wbd_we_o ; // write +input wbd_ack_i ; // acknowlegement +output wbd_stb_o ; // strobe/request +output wbd_cyc_o ; // wb cycle +input wbd_err_i ; // we error + +//------------------------------------ +// Reg Declaration +//-------------------------------- +reg [2:0] state ; +reg [2:0] state_d ; +reg [7:0] preq_len ; // pending request length in bytes +reg wbd_we_o ; // westbone write req +reg [23:0] wbd_adr_o ; // westnone address +reg dma_ack_o ; // dma ack +reg dma_done_o ; // dma ack +reg [7:0] twbtrans ; // total westbone transaction +reg dma_wr_o ; // dma write request +reg dma_rd_o ; // dma read request +reg [31:0] temp_data ; // temp holding data +reg [1:0] be_sof ; // Byte enable starting alignment +reg [31:0] wbd_dat_o ; // westbone data out +reg [3:0] wbd_be_o ; // west bone byte enable +reg [31:0] dma_rdata_o ; // dma read data +reg wbd_stb_o ; +reg dma_start_o ; // dma first transfer +reg dma_last_o ; // dma last transfer + +parameter WB_IDLE = 3'b000; +parameter WB_REQ = 3'b001; +parameter WB_WR_PHASE = 3'b010; +parameter WB_RD_PHASE_SOF = 3'b011; +parameter WB_RD_PHASE_CONT = 3'b100; + +assign dma_done_o = (state == WB_IDLE) && (state_d != WB_IDLE); + +always @(posedge rst or posedge clk) +begin + if(rst) begin + state <= WB_IDLE; + state_d <= WB_IDLE; + wbd_we_o <= 0; + wbd_adr_o <= 0; + preq_len <= 0; + dma_ack_o <= 0; + twbtrans <= 0; + dma_wr_o <= 0; + dma_rd_o <= 0; + temp_data <= 0; + be_sof <= 0; + wbd_dat_o <= 0; + wbd_be_o <= 0; + dma_rdata_o <= 0; + wbd_stb_o <= 0; + dma_start_o <= 0; + dma_last_o <= 0; + end + else begin + state_d <= state; + case(state) + WB_IDLE : + begin + if(dma_req_i) + begin + dma_ack_o <= 1; + wbd_we_o <= dma_write_i; + wbd_adr_o <= dma_addr_i[25:2]; + be_sof <= dma_addr_i[1] << 1 + dma_addr_i[0]; + preq_len <= dma_length_i; + // total wb transfer + twbtrans <= dma_length_i[7:2] + + |(dma_length_i[1:0]) + + |(dma_addr_i[1:0]); + state <= WB_REQ; + end + dma_wr_o <= 0; + dma_rd_o <= 0; + wbd_stb_o <= 0; + dma_start_o <= 0; + end + WB_REQ : + begin + dma_ack_o <= 0; + wbd_stb_o <= 1; + if(wbd_we_o) begin + dma_wr_o <= 1; + dma_start_o <= 1; + temp_data <= dma_wdata_i; + if(be_sof == 0) begin + wbd_dat_o <= dma_wdata_i; + wbd_be_o <= 4'b1111; + preq_len <= preq_len - 4; + end + else if(be_sof == 1) begin + wbd_dat_o <= {dma_wdata_i[23:0],8'h0}; + wbd_be_o <= 4'b1110; + preq_len <= preq_len - 3; + end + else if(be_sof == 2) begin + wbd_dat_o <= {dma_wdata_i[15:0],16'h0}; + wbd_be_o <= 4'b1100; + preq_len <= preq_len - 2; + end + else begin + wbd_dat_o <= {dma_wdata_i[7:0],23'h0}; + wbd_be_o <= 4'b1000; + preq_len <= preq_len - 1; + end + twbtrans <= twbtrans -1; + state <= WB_WR_PHASE; + if(twbtrans == 1) + dma_last_o <= 1; + end + else begin + state <= WB_RD_PHASE_SOF; + end + end + WB_WR_PHASE : + begin + dma_start_o <= 0; + if(wbd_ack_i) begin + if(twbtrans == 1) + dma_last_o <= 1; + else + dma_last_o <= 0; + if(twbtrans > 0) begin + temp_data <= dma_wdata_i; + twbtrans <= twbtrans -1; + if(be_sof == 0) begin + wbd_dat_o <= dma_wdata_i; + end + else if(be_sof == 1) begin + wbd_dat_o <= {dma_wdata_i[23:0],temp_data[31:24]}; + end + else if(be_sof == 2) begin + wbd_dat_o <= {dma_wdata_i[15:0],temp_data[31:16]}; + end + else begin + wbd_dat_o <= {dma_wdata_i[7:0],temp_data[31:8]}; + end + + if(twbtrans > 1) begin // If the Pending Transfer is more than 1 + dma_wr_o <= 1; + wbd_be_o <= 4'b1111; + preq_len <= preq_len - 4; + end + else begin // for last write access + wbd_be_o <= preq_len[1:0] == 2'b00 ? 4'b1111: + preq_len[1:0] == 2'b01 ? 4'b0001: + preq_len[1:0] == 2'b10 ? 4'b0011: 4'b0111; + + case({be_sof[1:0],preq_len[1:0]}) + // Start alignment = 0 + 4'b0001 : dma_wr_o <= 1; + 4'b0010 : dma_wr_o <= 1; + 4'b0011 : dma_wr_o <= 1; + 4'b0000 : dma_wr_o <= 1; + // Start alignment = 1 + 4'b0101 : dma_wr_o <= 0; + 4'b0110 : dma_wr_o <= 1; + 4'b0111 : dma_wr_o <= 1; + 4'b0100 : dma_wr_o <= 1; + // Start alignment = 2 + 4'b1001 : dma_wr_o <= 0; + 4'b1010 : dma_wr_o <= 0; + 4'b1011 : dma_wr_o <= 1; + 4'b1000 : dma_wr_o <= 1; + // Start alignment = 3 + 4'b1101 : dma_wr_o <= 0; + 4'b1110 : dma_wr_o <= 0; + 4'b1111 : dma_wr_o <= 0; + 4'b1100 : dma_wr_o <= 1; + endcase + end + end + else begin + dma_wr_o <= 0; + wbd_stb_o <= 0; + state <= WB_IDLE; + end + end + else begin + dma_last_o <= 0; + dma_wr_o <= 0; + end + end + WB_RD_PHASE_SOF : + begin + if(wbd_ack_i) begin + twbtrans <= twbtrans -1; + if(twbtrans == 1) begin // If the Pending Transfer is 1 + dma_rd_o <= 1; + dma_start_o<= 1; + if(be_sof == 0) begin + dma_rdata_o <= wbd_dat_i; + preq_len <= preq_len - 4; + end + else if(be_sof == 1) begin + dma_rdata_o <= {8'h0,wbd_dat_i[31:24]}; + preq_len <= preq_len - 3; + end + else if(be_sof == 2) begin + dma_rdata_o <= {16'h0,wbd_dat_i[31:16]}; + preq_len <= preq_len - 2; + end + else begin + dma_rdata_o <= {23'h0,wbd_dat_i[31:8]}; + preq_len <= preq_len - 0; + end + dma_last_o <= 1; + state <= WB_IDLE; + end + else begin // pending transction is more than 1 + if(be_sof == 0) begin + dma_rdata_o <= wbd_dat_i; + dma_rd_o <= 1; + dma_start_o <= 1; + preq_len <= preq_len - 4; + end + else if(be_sof == 1) begin + temp_data <= {8'h0,wbd_dat_i[31:24]}; + dma_rd_o <= 0; + preq_len <= preq_len - 3; + end + else if(be_sof == 2) begin + temp_data <= {16'h0,wbd_dat_i[31:16]}; + preq_len <= preq_len - 2; + end + else begin + temp_data <= {23'h0,wbd_dat_i[31:8]}; + preq_len <= preq_len - 0; + end + state <= WB_RD_PHASE_CONT; + end + end + else begin + dma_rd_o <= 0; + end + end + WB_RD_PHASE_CONT: + begin + dma_start_o <= 0; + if(wbd_ack_i) begin + dma_rd_o <= 1; + twbtrans <= twbtrans -1; + if(be_sof == 0) begin + dma_rdata_o <= wbd_dat_i; + preq_len <= preq_len - 4; + end + else if(be_sof == 1) begin + dma_rdata_o <= {wbd_dat_i[7:0],temp_data[23:0]}; + temp_data <= {8'h0,wbd_dat_i[31:8]}; + preq_len <= preq_len - 3; + end + else if(be_sof == 2) begin + dma_rdata_o <= {wbd_dat_i[15:0],temp_data[15:0]}; + temp_data <= {16'h0,wbd_dat_i[31:16]}; + preq_len <= preq_len - 2; + end + else begin + dma_rdata_o <= {wbd_dat_i[23:0],temp_data[7:0]}; + temp_data <= {24'h0,wbd_dat_i[31:23]}; + preq_len <= preq_len - 1; + end + if(twbtrans == 1) begin // If the it's last transfer + dma_last_o <= 1; + state <= WB_IDLE; + end + end + else begin + dma_last_o <= 0; + dma_rd_o <= 0; + end + end + endcase + end +end + + + +endmodule Index: trunk/rtl/lib/stat_counter.v =================================================================== --- trunk/rtl/lib/stat_counter.v (nonexistent) +++ trunk/rtl/lib/stat_counter.v (revision 11) @@ -0,0 +1,117 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Tubo 8051 cores common library Module //// +//// //// +//// This file is part of the Turbo 8051 cores project //// +//// http://www.opencores.org/cores/turbo8051/ //// +//// //// +//// Description //// +//// Turbo 8051 definitions. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// ----------------------------------------------------------------------- +// Module Name : stat_counter.v +// Company : +// Creation date : +// ----------------------------------------------------------------------- +// Description : This is the general purpose statistics counter. +// +// +// References : +// ------------------------------------------------------------------------ + +//----------------- compiler directives ----------------------------------- + +// ------------------------------------------------------------------------ +module stat_counter + ( + // Clock and Reset Signals + sys_clk, + s_reset_n, + + count_trigger, + + reg_sel, + reg_wr_data, + reg_wr, + + cntr_intr, + cntrout + + + ); + +parameter CWD = 1; // Counter Width + //-------------------- Parameters ------------------------------------- + + // ------------------- Clock and Reset Signals ------------------------ + input sys_clk; + input s_reset_n; + input count_trigger; + input reg_sel; + input reg_wr; + input [CWD-1:0] reg_wr_data; + output cntr_intr; + output [CWD-1:0] cntrout; + // ------------------- Register Declarations -------------------------- + reg [CWD-1:0] reg_trig_cntr; + + +// ------------------- Logic Starts Here ---------------------------------- + + + +always @ (posedge sys_clk or negedge s_reset_n) +begin + if (s_reset_n == 1'b0) begin + reg_trig_cntr <= 'b0; + end + else begin + if (reg_sel && reg_wr) begin + reg_trig_cntr <= reg_wr_data; + end + else begin + if (count_trigger) + reg_trig_cntr <= reg_trig_cntr + 1'b1; + else + reg_trig_cntr <= reg_trig_cntr; + end + end +end +assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_trigger) ; + +assign cntrout = reg_trig_cntr; + +endmodule // must_stat_counter

trunk/rtl/lib/stat_counter.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property