URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
Subversion Repositories turbo8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/turbo8051
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/rtl/gmac/mac/filelist_mac.f
0,0 → 1,20
dble_reg.v |
g_tx_fsm.v |
g_deferral.v |
g_tx_top.v |
g_rx_fsm.v |
g_cfg_mgmt.v |
s2f_sync.v |
g_md_intf.v |
g_ad_fltr.v |
g_deferral_rx.v |
g_rx_top.v |
g_mii_intf.v |
g_mac_core.v |
../crc32/g_rx_crc32.v |
../crc32/g_tx_crc32.v |
-v ../../lib/registers.v |
-v ../../lib/toggle_sync.v |
-v ../../lib/stat_counter.v |
+lint=all |
+v2k |
/trunk/rtl/gmac/mac/g_mac_core.v
0,0 → 1,590
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Tubo 8051 cores MAC Interface Module //// |
//// //// |
//// This file is part of the Turbo 8051 cores project //// |
//// http://www.opencores.org/cores/turbo8051/ //// |
//// //// |
//// Description //// |
//// Turbo 8051 definitions. //// |
//// //// |
//// To Do: //// |
//// nothing //// |
//// //// |
//// Author(s): //// |
//// - Dinesh Annayya, dinesha@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//`timescale 1ns/100ps |
module g_mac_core ( |
scan_mode, |
s_reset_n, |
tx_reset_n, |
rx_reset_n, |
reset_mdio_clk_n, |
app_reset_n, |
|
app_clk, |
app_send_pause_i, |
app_send_pause_active_o, |
app_send_jam_i, |
|
// Reg Bus Interface Signal |
reg_cs, |
reg_wr, |
reg_addr, |
reg_wdata, |
reg_be, |
|
// Outputs |
reg_rdata, |
reg_ack, |
|
|
// RX FIFO Interface Signal |
rx_fifo_full_i, |
rx_fifo_wr_o, |
rx_fifo_data_o, |
rx_commit_wr_o, |
rx_rewind_wr_o, |
rx_commit_write_done_o, |
clr_rx_error_from_rx_fsm_o, |
rx_fifo_error_i, |
|
// TX FIFO Interface Signal |
tx_fifo_data_i, |
tx_fifo_empty_i, |
tx_fifo_rdy_i, |
tx_fifo_rd_o, |
tx_commit_read_o, |
|
// Phy Signals |
|
// Line Side Interface TX Path |
phy_tx_en, |
phy_tx_er, |
phy_txd, |
phy_tx_clk, |
|
// Line Side Interface RX Path |
phy_rx_clk, |
phy_rx_er, |
phy_rx_dv, |
phy_rxd, |
phy_crs, |
|
//MDIO interface |
mdio_clk, |
mdio_in, |
mdio_out_en, |
mdio_out |
); |
|
parameter mac_mdio_en = 1'b1; |
|
//----------------------------------------------------------------------- |
// INPUT/OUTPUT DECLARATIONS |
//----------------------------------------------------------------------- |
input scan_mode; |
input s_reset_n; |
input tx_reset_n; |
input rx_reset_n; |
input reset_mdio_clk_n; |
input app_reset_n; |
|
//----------------------------------------------------------------------- |
// Application Clock Related Declaration |
//----------------------------------------------------------------------- |
input app_clk; |
input app_send_pause_i; |
output app_send_pause_active_o; |
input app_send_jam_i; |
|
// Conntrol Bus Sync with Application Clock |
//--------------------------------- |
// Reg Bus Interface Signal |
//--------------------------------- |
input reg_cs ; |
input reg_wr ; |
input [3:0] reg_addr ; |
input [31:0] reg_wdata ; |
input [3:0] reg_be ; |
|
// Outputs |
output [31:0] reg_rdata ; |
output reg_ack ; |
|
|
|
// RX FIFO Interface Signal |
output clr_rx_error_from_rx_fsm_o; |
input rx_fifo_full_i; |
output rx_fifo_wr_o; |
output [8:0] rx_fifo_data_o; |
output rx_commit_wr_o; |
output rx_commit_write_done_o; |
output rx_rewind_wr_o; |
input rx_fifo_error_i; |
|
//----------------------------------------------------------------------- |
// TX-Clock Domain Status Signal |
//----------------------------------------------------------------------- |
output tx_commit_read_o; |
output tx_fifo_rd_o; |
|
input [8:0] tx_fifo_data_i; |
input tx_fifo_empty_i; |
input tx_fifo_rdy_i; |
|
|
//----------------------------------------------------------------------- |
// Line-Tx Signal |
//----------------------------------------------------------------------- |
output phy_tx_en; |
output phy_tx_er; |
output [7:0] phy_txd; |
input phy_tx_clk; |
|
//----------------------------------------------------------------------- |
// Line-Rx Signal |
//----------------------------------------------------------------------- |
input phy_rx_clk; |
input phy_rx_er; |
input phy_rx_dv; |
input [7:0] phy_rxd; |
input phy_crs; |
|
|
//----------------------------------------------------------------------- |
// MDIO Signal |
//----------------------------------------------------------------------- |
input mdio_clk; |
input mdio_in; |
output mdio_out_en; |
output mdio_out; |
|
//----------------------------------------------------------------------- |
// RX-Clock Domain Status Signal |
//----------------------------------------------------------------------- |
wire rx_sts_vld_o; |
wire [15:0] rx_sts_bytes_rcvd_o; |
wire rx_sts_large_pkt_o; |
wire rx_sts_lengthfield_err_o; |
wire rx_sts_len_mismatch_o; |
wire rx_sts_crc_err_o; |
wire rx_sts_runt_pkt_rcvd_o; |
wire rx_sts_rx_overrun_o; |
wire rx_sts_frm_length_err_o; |
wire rx_sts_rx_er_o; |
|
|
//----------------------------------------------------------------------- |
// TX-Clock Domain Status Signal |
//----------------------------------------------------------------------- |
wire tx_sts_vld_o ; |
wire [15:0]tx_sts_byte_cntr_o ; |
wire tx_sts_fifo_underrun_o; |
// TX Interface Status Signal |
wire tx_set_fifo_undrn_o ;// Description: At GMII Interface , |
// abug after a transmit fifo underun was found. |
// The packet after a packet that |
// underran has 1 too few bytes . |
|
wire[7:0] mi2rx_rx_byte,tx2mi_tx_byte; |
wire [7:0] cf2df_dfl_single_rx; |
wire [15:0] cf2rx_max_pkt_sz; |
|
g_rx_top u_rx_top( |
//application |
.app_clk (app_clk), |
.app_reset_n (s_reset_n), // Condor Change |
.rx_reset_n (rx_reset_n), |
.scan_mode (scan_mode), |
|
.rx_sts_vld (rx_sts_vld_o), |
.rx_sts_bytes_rcvd (rx_sts_bytes_rcvd_o), |
.rx_sts_large_pkt (rx_sts_large_pkt_o), |
.rx_sts_lengthfield_err (rx_sts_lengthfield_err_o), |
.rx_sts_len_mismatch (rx_sts_len_mismatch_o), |
.rx_sts_crc_err (rx_sts_crc_err_o), |
.rx_sts_runt_pkt_rcvd (rx_sts_runt_pkt_rcvd_o), |
.rx_sts_rx_overrun (rx_sts_rx_overrun_o), |
.rx_sts_frm_length_err (rx_sts_frm_length_err_o), |
.clr_rx_error_from_rx_fsm (clr_rx_error_from_rx_fsm_o), |
.rx_fifo_full (rx_fifo_full_i), |
.rx_dt_wrt (rx_fifo_wr_o), |
.rx_dt_out (rx_fifo_data_o), |
.rx_commit_wr (rx_commit_wr_o), |
.commit_write_done (rx_commit_write_done_o), |
.rx_rewind_wr (rx_rewind_wr_o), |
//transistor interface |
.rx2tx_pause_tx (rx2tx_pause_o), |
//mii interface |
.phy_rx_clk (phy_rx_clk), |
.mi2rx_strt_rcv (mi2rx_strt_rcv), |
.mi2rx_rcv_vld (mi2rx_rcv_vld), |
.mi2rx_rx_byte (mi2rx_rx_byte), |
.mi2rx_end_rcv (mi2rx_end_rcv), |
.mi2rx_extend (mi2rx_extend), |
.mi2rx_frame_err (mi2rx_frame_err), |
.mi2rx_end_frame (mi2rx_end_frame), |
.mi2rx_crs (mi2rx_crs), |
.df2rx_dfl_dn (df2rx_dfl_dn), |
//PHY Signals |
.phy_rx_dv (phy_rx_dv), |
//Config interface |
.cf2rx_max_pkt_sz (cf2rx_max_pkt_sz), |
.cf2rx_rx_ch_en (cf2rx_ch_en), |
.cf2rx_strp_pad_en (cf2rx_strp_pad_en), |
.cf2rx_snd_crc (cf2rx_snd_crc), |
.cf2rx_pause_en (cf2rx_pause_en), |
.cf2rx_rcv_runt_pkt_en (cf2rx_runt_pkt_en), |
.cf_macmode (cf_mac_mode_o), |
.cf2df_dfl_single_rx (cf2df_dfl_single_rx), |
.ap2rx_rx_fifo_err (rx_fifo_error_i), |
//A200 change Port added for crs based flow control |
.phy_crs (phy_crs), |
//A200 change crs flow control enable signal |
.crs_flow_control_enable (cfg_crs_flow_ctrl_enb_i), |
//A200 change pause detected pulse for counter |
.pause_frame_detected () |
); |
|
wire [4:0] cf2md_regad,cf2md_phyad; |
wire [15:0] cf2md_datain,md2cf_data; |
|
|
|
wire md2cf_status; |
wire md2cf_cmd_done; |
wire cf2md_op; |
wire cf2md_go; |
wire mdc; |
|
wire int_s_reset_n; |
wire [4:0] int_cf2md_regad; |
wire [4:0] int_cf2md_phyad; |
wire int_cf2md_op; |
wire int_cf2md_go; |
wire [15:0] int_cf2md_datain; |
|
wire int_md2cf_status; |
wire [15:0] int_md2cf_data; |
wire int_md2cf_cmd_done; |
|
wire int_mdio_clk; |
wire int_mdio_out_en; |
wire int_mdio_out; |
wire int_mdc; |
wire int_mdio_in; |
|
// ------------------------------------------------------------------------ |
// CONDOR CHANGE |
// MDIO Enable/disable Mux |
// MDIO is used only in the WAN MAC block. The MDIO block has to be disabled |
// in all other places. When MDIO is enabled the MDIO block signals will be |
// connected to core module appriprotately. If MDIO is disabled, all inputs |
// to the MDIO module is made zero and all outputs from this module to other |
// modules is made zero. The enable/disable is controlled by the parameter |
// mac_mdio_en. |
// ------------------------------------------------------------------------ |
|
// ------------------------------------------------------------------------ |
// Inputs to the MDIO module |
// ------------------------------------------------------------------------ |
|
assign int_s_reset_n = (mac_mdio_en == 1'b1) ? reset_mdio_clk_n : 1'b1; |
assign int_cf2md_regad = (mac_mdio_en == 1'b1) ? cf2md_regad : 5'b0; |
assign int_cf2md_phyad = (mac_mdio_en == 1'b1) ? cf2md_phyad : 5'b0; |
assign int_cf2md_op = (mac_mdio_en == 1'b1) ? cf2md_op : 1'b0; |
assign int_cf2md_go = (mac_mdio_en == 1'b1) ? cf2md_go : 1'b0; |
assign int_cf2md_datain = (mac_mdio_en == 1'b1) ? cf2md_datain : 16'b0; |
|
// ------------------------------------------------------------------------ |
// Outputs from the MDIO module used locally |
// ------------------------------------------------------------------------ |
|
assign md2cf_status = (mac_mdio_en == 1'b1) ? int_md2cf_status : 1'b0; |
assign md2cf_data = (mac_mdio_en == 1'b1) ? int_md2cf_data : 16'b0; |
//assign md2cf_cmd_done = (mac_mdio_en == 1'b1) ? int_md2cf_cmd_done : 1'b0; |
|
// ------------------------------------------------------------------------ |
// Outputs from the MDIO module driven out of this module |
// ------------------------------------------------------------------------ |
|
assign mdio_out_en = (mac_mdio_en == 1'b1) ? int_mdio_out_en : 1'b0; |
assign mdio_out = (mac_mdio_en == 1'b1) ? int_mdio_out : 1'b0; |
assign mdc = (mac_mdio_en == 1'b1) ? int_mdc : 1'b0; |
|
assign int_mdio_clk = (mac_mdio_en == 1'b1) ? mdio_clk : 1'b0; |
assign int_mdio_in = (mac_mdio_en == 1'b1) ? mdio_in : 1'b0; |
|
// ------------------------------------------------------------------------ |
// MDIO module connected with 'int_' signals |
// ------------------------------------------------------------------------ |
|
|
g_md_intf u_md_intf( |
//apllication interface |
.scan_mode (scan_mode), // A200 change |
.reset_n (int_s_reset_n), // Condor Change |
|
.mdio_clk (int_mdio_clk), |
.mdio_in (int_mdio_in), |
.mdio_outen_reg (int_mdio_out_en), |
.mdio_out_reg (int_mdio_out), |
//Config interface |
.mdio_regad (int_cf2md_regad), |
.mdio_phyad (int_cf2md_phyad), |
.mdio_op (int_cf2md_op), |
.go_mdio (int_cf2md_go), |
.mdio_datain (int_cf2md_datain), |
.mdio_dataout (int_md2cf_data), |
.mdio_cmd_done (md2cf_cmd_done), |
.mdio_stat (int_md2cf_status), |
.mdc (int_mdc) |
); |
|
|
wire [7:0] cf2df_dfl_single; |
wire [47:0] cf_mac_sa; |
wire [15:0] cf2tx_pause_quanta; |
wire cf2tx_force_bad_fcs; |
wire cf2tx_tstate_mode; |
wire set_fifo_undrn; |
|
g_tx_top U_tx_top ( |
.app_clk (app_clk) , |
.send_pause_active (app_send_pause_active_o), |
.set_fifo_undrn (tx_set_fifo_undrn_o), |
|
//Outputs |
//TX FIFO management |
.tx_commit_read (tx_commit_read_o), |
.tx_dt_rd (tx_fifo_rd_o), |
|
//MII interface |
.tx2mi_strt_preamble (tx2mi_strt_preamble), |
.tx2mi_byte_valid (tx2mi_byte_valid), |
.tx2mi_byte (tx2mi_tx_byte), |
.tx2mi_end_transmit (tx2mi_end_transmit), |
.tx_ch_en (tx_ch_en), |
|
//Status to application |
.tx_sts_vld (tx_sts_vld_o), |
.tx_sts_byte_cntr (tx_sts_byte_cntr_o), |
.tx_sts_fifo_underrun (tx_sts_fifo_underrun_o), |
|
//Inputs |
//MII interface |
.phy_tx_en (phy_tx_en), |
.phy_tx_er (phy_tx_er), |
|
//application |
.app_send_pause (app_send_pause_i), |
|
//rx_top |
.rx2tx_pause (rx2tx_pause_o), |
|
//configuration |
.cf2tx_tstate_mode (cf2tx_tstate_mode), |
.cf2tx_ch_en (cf2tx_ch_en), |
.cf2df_dfl_single (cf2df_dfl_single), |
.cf2tx_pad_enable (cf2tx_pad_enable), |
.cf2tx_append_fcs (cf2tx_append_fcs), |
.cf_mac_mode (cf_mac_mode_o), |
.cf_mac_sa (cf_mac_sa), |
.cf2tx_pause_quanta (cf2tx_pause_quanta), |
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs), |
|
//FIFO data |
.app_tx_dt_in (tx_fifo_data_i), |
.app_tx_fifo_empty (tx_fifo_empty_i), |
.app_tx_rdy (tx_fifo_rdy_i), |
|
//MII |
.mi2tx_byte_ack (mi2tx_byte_ack), |
|
.app_reset_n (s_reset_n), // Condor Change |
.tx_reset_n (tx_reset_n), |
.tx_clk (phy_tx_clk) |
); |
|
toggle_sync u_rx_sts_sync ( |
. in_clk (phy_rx_clk ), |
. in_rst_n (rx_reset_n ), |
. in (rx_sts_vld_o ), |
. out_clk (app_clk ), |
. out_rst_n (app_reset_n ), |
. out_req (rx_sts_vld_ss ), |
. out_ack (rx_sts_vld_ss ) |
); |
|
|
toggle_sync u_tx_sts_sync ( |
. in_clk (phy_tx_clk ), |
. in_rst_n (tx_reset_n ), |
. in (tx_sts_vld_o ), |
. out_clk (app_clk ), |
. out_rst_n (app_reset_n ), |
. out_req (tx_sts_vld_ss ), |
. out_ack (tx_sts_vld_ss ) |
); |
|
|
|
g_cfg_mgmt #(mac_mdio_en) u_cfg_mgmt ( |
|
// Reg Bus Interface Signal |
. reg_cs (reg_cs), |
. reg_wr (reg_wr), |
. reg_addr (reg_addr), |
. reg_wdata (reg_wdata), |
. reg_be (reg_be), |
|
// Outputs |
. reg_rdata (reg_rdata), |
. reg_ack (reg_ack), |
|
// Rx Status |
. rx_sts_vld(rx_sts_vld_ss), |
. rx_sts ({rx_sts_large_pkt_o, |
rx_sts_lengthfield_err_o, |
rx_sts_len_mismatch_o, |
rx_sts_crc_err_o, |
rx_sts_runt_pkt_rcvd_o, |
rx_sts_rx_overrun_o, |
rx_sts_frm_length_err_o, |
rx_sts_rx_er_o |
}), |
|
// Tx Status |
. tx_sts_vld(tx_sts_vld_ss), |
. tx_sts (tx_sts_fifo_underrun_o), |
|
// MDIO READ DATA FROM PHY |
// CONDOR CHANGE |
// Since MDIO is not required for the half duplex |
// MACs the done is always tied to 1'b1 |
.md2cf_cmd_done (md2cf_cmd_done), |
.md2cf_status (md2cf_status), |
.md2cf_data (md2cf_data), |
|
.app_clk (app_clk), |
.app_reset_n (app_reset_n), |
|
//List of Outputs |
// MII Control |
.cf2mi_loopback_en (cf2mi_loopback_en), |
.cf_mac_mode (cf_mac_mode_o), |
.cf_chk_rx_dfl (cf_chk_rx_dfl), |
.cf_silent_mode (cf_silent_mode), |
.cf2mi_rmii_en (cf2mi_rmii_en_o), |
|
// Config In |
.cfg_uni_mac_mode_change_i (cfg_uni_mac_mode_change_i), |
.cfg_crs_flow_ctrl_enb_i (cfg_crs_flow_ctrl_enb_i), |
|
//CHANNEL enable |
.cf2tx_tstate_mode (cf2tx_tstate_mode), |
.cf2tx_ch_en (cf2tx_ch_en), |
//CHANNEL CONTROL TX |
.cf2df_dfl_single (cf2df_dfl_single), |
.cf2df_dfl_single_rx (cf2df_dfl_single_rx), |
.cf2tx_pad_enable (cf2tx_pad_enable), |
.cf2tx_append_fcs (cf2tx_append_fcs), |
//CHANNEL CONTROL RX |
.cf2rx_max_pkt_sz (cf2rx_max_pkt_sz), |
.cf2rx_ch_en (cf2rx_ch_en), |
.cf2rx_strp_pad_en (cf2rx_strp_pad_en), |
.cf2rx_snd_crc (cf2rx_snd_crc), |
.cf2rx_pause_en (cf2rx_pause_en), |
.cf2rx_addrchk_en (), |
.cf2rx_runt_pkt_en (cf2rx_runt_pkt_en), |
.cf2af_broadcast_disable (cf2af_broadcast_disable), |
.cf_mac_sa (cf_mac_sa), |
.cf2tx_pause_quanta (cf2tx_pause_quanta), |
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs), |
//MDIO CONTROL & DATA |
.cf2md_datain (cf2md_datain), |
.cf2md_regad (cf2md_regad), |
.cf2md_phyad (cf2md_phyad), |
.cf2md_op (cf2md_op), |
.cf2md_go (cf2md_go) |
); |
|
g_mii_intf u_mii_intf( |
// Data and Control Signals to tx_fsm and rx_fsm |
.mi2rx_strt_rcv (mi2rx_strt_rcv), |
.mi2rx_rcv_vld (mi2rx_rcv_vld), |
.mi2rx_rx_byte (mi2rx_rx_byte), |
.mi2rx_end_rcv (mi2rx_end_rcv), |
.mi2rx_extend (mi2rx_extend), |
.mi2rx_frame_err (mi2rx_frame_err), |
.mi2rx_end_frame (mi2rx_end_frame), |
.mi2rx_crs (mi2rx_crs), |
.mi2tx_byte_ack (mi2tx_byte_ack), |
.cfg_uni_mac_mode_change (cfg_uni_mac_mode_change_i), |
|
// Phy Signals |
.phy_tx_en (phy_tx_en), |
.phy_tx_er (phy_tx_er), |
.phy_txd (phy_txd), |
.phy_tx_clk (phy_tx_clk), |
.phy_rx_clk (phy_rx_clk), |
.tx_reset_n (tx_reset_n), |
.rx_reset_n (rx_reset_n), |
.phy_rx_er (phy_rx_er), |
.phy_rx_dv (phy_rx_dv), |
.phy_rxd (phy_rxd), |
.phy_crs (phy_crs), |
|
// Reset signal |
// .app_reset (app_reset), |
.rx_sts_rx_er_reg (rx_sts_rx_er), |
.app_reset_n (s_reset_n), |
|
// Signals from Config Management |
.cf2mi_loopback_en (cf2mi_loopback_en), |
.cf2mi_rmii_en (cf2mi_rmii_en_o), |
.cf_mac_mode (cf_mac_mode_o), |
.cf_chk_rx_dfl (cf_chk_rx_dfl), |
.cf_silent_mode (cf_silent_mode), |
|
// Signal from Application to transmit JAM |
.df2rx_dfl_dn (df2rx_dfl_dn), |
.app_send_jam (app_send_jam_i), |
|
// Inputs from Transmit FSM |
.tx2mi_strt_preamble (tx2mi_strt_preamble), |
.tx2mi_end_transmit (tx2mi_end_transmit), |
.tx2mi_tx_byte (tx2mi_tx_byte), |
.tx_ch_en (tx_ch_en), |
.mi2tx_slot_vld () |
); |
endmodule |
trunk/rtl/gmac/mac/g_mac_core.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/byte_reg.v
===================================================================
--- trunk/rtl/gmac/mac/byte_reg.v (nonexistent)
+++ trunk/rtl/gmac/mac/byte_reg.v (revision 12)
@@ -0,0 +1,79 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ byte_reg.v: instantiates 32 registers to make a quad
+ This enables maintaining timing on blocks
+ in check
+***********************************************************************/
+module half_dup_byte_reg(
+ //List of Inputs
+ we,
+ data_in,
+ reset_n,
+ clk,
+
+ //List of Outputs
+ data_out
+);
+
+ input [7:0] we;
+ input [7:0] data_in;
+ input reset_n;
+ input clk;
+ output [7:0] data_out;
+
+
+ generic_register #(8,0) u_reg (
+
+ .we (we),
+ .clk (clk),
+ .reset_n (reset_n),
+ .data_in (data_in),
+ .data_out (data_out)
+ );
+
+
+endmodule
+
trunk/rtl/gmac/mac/byte_reg.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_rx_top.v
===================================================================
--- trunk/rtl/gmac/mac/g_rx_top.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_rx_top.v (revision 12)
@@ -0,0 +1,242 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+ module g_rx_top(
+ app_reset_n,
+ phy_rx_clk,
+ rx_reset_n,
+ app_clk,
+ scan_mode,
+ rx_sts_vld,
+ rx_sts_bytes_rcvd,
+ rx_sts_large_pkt,
+ rx_sts_lengthfield_err,
+ rx_sts_len_mismatch,
+ rx_sts_crc_err,
+ rx_sts_runt_pkt_rcvd,
+ rx_sts_rx_overrun,
+ rx_sts_frm_length_err,
+ clr_rx_error_from_rx_fsm,
+ rx_fifo_full,
+ rx_dt_wrt,
+ rx_dt_out,
+ rx_commit_wr,
+ commit_write_done,
+ rx_rewind_wr,
+ rx2tx_pause_tx,
+ mi2rx_strt_rcv,
+ mi2rx_rcv_vld,
+ mi2rx_rx_byte,
+ mi2rx_end_rcv,
+ mi2rx_extend,
+ mi2rx_frame_err,
+ mi2rx_end_frame,
+ phy_rx_dv,
+ cf2rx_max_pkt_sz,
+ cf2rx_rx_ch_en,
+ cf2rx_strp_pad_en,
+ cf2rx_snd_crc,
+ cf2rx_pause_en,
+ cf2df_dfl_single_rx,
+ cf2rx_rcv_runt_pkt_en,
+ cf_macmode,
+ mi2rx_crs,
+ df2rx_dfl_dn,
+ ap2rx_rx_fifo_err,
+ //A200 change Port added for crs based flow control
+ phy_crs,
+ //A200 change crs flow control enable signal
+ crs_flow_control_enable,
+ //A200 change pause detected pulse for counter
+ pause_frame_detected
+ );
+
+ input app_reset_n;
+ input phy_rx_clk;
+ input rx_reset_n;
+ input app_clk;
+ input scan_mode;
+
+ output rx_sts_vld;
+ output [15:0] rx_sts_bytes_rcvd;
+ output rx_sts_large_pkt;
+ output rx_sts_lengthfield_err;
+ output rx_sts_len_mismatch;
+ output rx_sts_crc_err;
+ output rx_sts_runt_pkt_rcvd;
+ output rx_sts_rx_overrun;
+ output rx_sts_frm_length_err;
+
+ output clr_rx_error_from_rx_fsm;
+ input rx_fifo_full;
+ output rx_dt_wrt;
+ output [8:0] rx_dt_out;
+ output rx_commit_wr;
+ output commit_write_done;
+ output rx_rewind_wr;
+ output rx2tx_pause_tx;
+ input mi2rx_strt_rcv;
+ input mi2rx_rcv_vld;
+ input [7:0] mi2rx_rx_byte;
+ input mi2rx_end_rcv;
+ input mi2rx_extend;
+ input mi2rx_frame_err;
+ input mi2rx_end_frame;
+ input phy_rx_dv;
+ input [15:0] cf2rx_max_pkt_sz;
+ input cf2rx_rx_ch_en;
+ input cf2rx_strp_pad_en;
+ input cf2rx_snd_crc;
+ input cf2rx_pause_en;
+ input cf2rx_rcv_runt_pkt_en;
+ input cf_macmode;
+ input [7:0] cf2df_dfl_single_rx;
+ input ap2rx_rx_fifo_err;
+ input mi2rx_crs;
+ output df2rx_dfl_dn;
+
+ //A200 change Port added for crs based flow control
+ input phy_crs;
+ //A200 change crs flow control enable signal
+ input crs_flow_control_enable;
+
+ //A200 change pause detected pulse for counter
+ output pause_frame_detected;
+
+
+ g_rx_fsm u_rx_fsm(
+ // Status information to Applications
+ .rx_sts_vld(rx_sts_vld),
+ .rx_sts_bytes_rcvd(rx_sts_bytes_rcvd),
+ .rx_sts_large_pkt(rx_sts_large_pkt),
+ .rx_sts_lengthfield_err(rx_sts_lengthfield_err),
+ .rx_sts_len_mismatch(rx_sts_len_mismatch),
+ .rx_sts_crc_err(rx_sts_crc_err),
+ .rx_sts_runt_pkt_rcvd(rx_sts_runt_pkt_rcvd),
+ .rx_sts_rx_overrun(rx_sts_rx_overrun),
+ .rx_sts_frm_length_err(rx_sts_frm_length_err),
+ // Data Signals to Fifo Management Block
+ .clr_rx_error_from_rx_fsm(clr_rx_error_from_rx_fsm),
+ .rx2ap_rx_fsm_wrt(rx_dt_wrt),
+ .rx2ap_rx_fsm_dt(rx_dt_out),
+ // Fifo Control Signal to Fifo Management Block
+ .rx2ap_commit_write(rx_commit_wr),
+ .rx2ap_rewind_write(rx_rewind_wr),
+ // To address filtering block
+ // Pause control to Tx block
+ .rx2tx_pause_tx(rx2tx_pause_tx),
+ .commit_write_done(commit_write_done),
+
+ // Global Signals
+ .reset_n(rx_reset_n),
+ .phy_rx_clk(phy_rx_clk),
+ // Signals from Mii/Rmii block for Receive data
+ .mi2rx_strt_rcv(mi2rx_strt_rcv),
+ .mi2rx_rcv_vld(mi2rx_rcv_vld),
+ .mi2rx_rx_byte(mi2rx_rx_byte),
+ .mi2rx_end_rcv(mi2rx_end_rcv),
+ .mi2rx_extend(mi2rx_extend),
+ .mi2rx_end_frame(mi2rx_end_frame),
+ .mi2rx_frame_err(mi2rx_frame_err),
+ // Rx fifo management signal to indicate overrun
+ .rx_fifo_full(rx_fifo_full),
+ .ap2rx_rx_fifo_err(ap2rx_rx_fifo_err),
+ // Signal from CRC check block
+ .rc2rx_crc_ok(rc2rx_crc_ok),
+ // Signals from Address filtering block
+ .af2rx_pause_frame(af2rx_pause_frame),
+ // Signals from Config Management Block
+ .cf2rx_max_pkt_sz(cf2rx_max_pkt_sz),
+ .cf2rx_rx_ch_en(cf2rx_rx_ch_en),
+ .cf2rx_strp_pad_en(cf2rx_strp_pad_en),
+ .cf2rx_snd_crc(cf2rx_snd_crc),
+ .cf2rx_pause_en(cf2rx_pause_en),
+ .cf2rx_rcv_runt_pkt_en(cf2rx_rcv_runt_pkt_en),
+ .cf2rx_gigabit_xfr(cf_macmode),
+ //A200 change Port added for crs based flow control
+ .phy_crs(phy_crs),
+ //A200 change crs flow control enable signal
+ .crs_flow_control_enable(crs_flow_control_enable),
+ //A200 change pause detected pulse for counter
+ .pause_frame_detected(pause_frame_detected)
+ );
+
+ g_ad_fltr u_ad_fltr(
+ .phy_rx_clk(phy_rx_clk),
+ .rx_reset_n(rx_reset_n),
+ .app_clk(app_clk),
+ .scan_mode(scan_mode),
+ //MII Interface
+ .mi2af_rcv_vld(mi2rx_rcv_vld),
+ .mi2af_strt_rcv(mi2rx_strt_rcv),
+ .mi2af_end_rcv(mi2rx_end_rcv),
+ .mi2af_rx_data(mi2rx_rx_byte),
+ //RX_FSM Interface
+ .af2rf_pause_frame(af2rx_pause_frame)
+ );
+
+ g_rx_crc32 u_rx_crc32 (
+ // CRC Valid signal to rx_fsm
+ .rc2rf_crc_ok(rc2rx_crc_ok),
+
+ // Global Signals
+ .phy_rx_clk(phy_rx_clk),
+ .reset_n(rx_reset_n),
+ // CRC Data signals
+ .mi2rc_strt_rcv(mi2rx_strt_rcv),
+ .mi2rc_rcv_valid(mi2rx_rcv_vld),
+ .mi2rc_rx_byte(mi2rx_rx_byte)
+ );
+
+
+ g_deferral_rx U_deferral_rx (
+//0503 Changed .port names to match g_deferral_rx
+ .rx_dfl_dn(df2rx_dfl_dn),
+ .dfl_single(cf2df_dfl_single_rx),
+ .rx_dv(phy_rx_dv),
+//0504 .phy_rx_er(phy_rx_er),
+ .rx_clk(phy_rx_clk),
+ .reset_n(rx_reset_n));
+
+ endmodule
trunk/rtl/gmac/mac/g_rx_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_ad_fltr.v
===================================================================
--- trunk/rtl/gmac/mac/g_ad_fltr.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_ad_fltr.v (revision 12)
@@ -0,0 +1,199 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+
+ module g_ad_fltr(
+ phy_rx_clk,
+ rx_reset_n,
+ app_clk,
+ scan_mode,
+ //MII Interface
+ mi2af_rcv_vld,
+ mi2af_strt_rcv,
+ mi2af_end_rcv,
+ mi2af_rx_data,
+ //Configuration Interface
+ //RX_FSM Interface
+ af2rf_pause_frame
+ );
+
+parameter PAUSE_CONTROL_FRAME = 48'h01_00_00_c2_80_01;
+
+
+ input phy_rx_clk;
+ input rx_reset_n;
+ input app_clk;
+ input scan_mode;
+ //MII Interface
+ input mi2af_rcv_vld;
+ input mi2af_strt_rcv;
+ input mi2af_end_rcv;
+ input [7:0] mi2af_rx_data;
+ //Configuration Interface
+ //RX_FSM Interface
+ output af2rf_pause_frame;
+
+ //****** appliction initializing the address filter registers*******
+
+ reg pause1_valid;
+
+
+ //***********************************************************************************
+
+ reg [2:0] addr_length_ptr;
+
+ wire rf2af_addr_chk = (mi2af_rcv_vld && addr_length_ptr < 5);
+
+ always @(posedge phy_rx_clk
+ or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ addr_length_ptr <= 3'b0;
+ else if(mi2af_strt_rcv)
+ addr_length_ptr <= 3'b0;
+ else if(mi2af_rcv_vld & rf2af_addr_chk)
+ addr_length_ptr <= addr_length_ptr + 1;
+ end
+
+ reg [7:0] pause_filt_reg;
+ wire [47:0] pause_reg;
+
+
+ assign pause_reg = PAUSE_CONTROL_FRAME;
+
+ always @(addr_length_ptr or pause_reg )
+ begin
+ case(addr_length_ptr)
+ 4'h0:
+ begin
+ pause_filt_reg[7:0] = pause_reg[7:0];
+ end
+ 4'h1:
+ begin
+ pause_filt_reg[7:0] = pause_reg[15:8];
+ end
+ 4'h2:
+ begin
+ pause_filt_reg[7:0] = pause_reg[23:16];
+ end
+ 4'h3:
+ begin
+ pause_filt_reg[7:0] = pause_reg[31:24];
+ end
+ 4'h4:
+ begin
+ pause_filt_reg[7:0] = pause_reg[39:32];
+ end
+ 4'h5:
+ begin
+ pause_filt_reg[7:0] = pause_reg[47:40];
+ end
+ default:
+ begin
+ pause_filt_reg[7:0] = pause_reg[7:0];
+ end
+ endcase
+ end
+
+ reg first_byte;
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ first_byte <= 0;
+ else if(mi2af_strt_rcv)
+ first_byte <= 1;
+ else if(rf2af_addr_chk && mi2af_rcv_vld)
+ first_byte <= 0;
+ end
+
+ reg pause0bit_valid,pause1bit_valid,pause2bit_valid,pause3bit_valid,
+ pause4bit_valid,pause5bit_valid,pause6bit_valid,pause7bit_valid;
+
+
+
+ always @(mi2af_rx_data or pause_filt_reg)
+ begin
+ pause0bit_valid = !(pause_filt_reg[0] ^ mi2af_rx_data[0]);
+ pause1bit_valid = !(pause_filt_reg[1] ^ mi2af_rx_data[1]);
+ pause2bit_valid = !(pause_filt_reg[2] ^ mi2af_rx_data[2]);
+ pause3bit_valid = !(pause_filt_reg[3] ^ mi2af_rx_data[3]);
+ pause4bit_valid = !(pause_filt_reg[4] ^ mi2af_rx_data[4]);
+ pause5bit_valid = !(pause_filt_reg[5] ^ mi2af_rx_data[5]);
+ pause6bit_valid = !(pause_filt_reg[6] ^ mi2af_rx_data[6]);
+ pause7bit_valid = !(pause_filt_reg[7] ^ mi2af_rx_data[7]);
+ end
+
+ wire pausetmp_valid;
+
+ assign pausetmp_valid = pause0bit_valid && pause1bit_valid
+ && pause2bit_valid && pause3bit_valid
+ && pause4bit_valid && pause5bit_valid
+ && pause6bit_valid && pause7bit_valid
+ && rf2af_addr_chk;
+
+ always @(posedge phy_rx_clk
+ or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ pause1_valid <= 0;
+ else if(mi2af_end_rcv)
+ pause1_valid <= 0;
+ else if(first_byte && pausetmp_valid)
+ pause1_valid <= 1;
+ else if(pause1_valid && pausetmp_valid)
+ pause1_valid <= 1;
+ else if(!rf2af_addr_chk)
+ pause1_valid <= pause1_valid;
+ else if(!pausetmp_valid && mi2af_rcv_vld)
+ pause1_valid <= 1'b0;
+ end
+ //*****************************OUTPUTS**********************************************************
+
+ wire af2rf_pause_frame;
+
+
+ assign af2rf_pause_frame = pause1_valid;
+
+ endmodule
+
trunk/rtl/gmac/mac/g_ad_fltr.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_tx_top.v
===================================================================
--- trunk/rtl/gmac/mac/g_tx_top.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_tx_top.v (revision 12)
@@ -0,0 +1,252 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+/***************************************************************
+ Description:
+
+ tx_top.v: This module has the top level of the transmit block
+ It instantiates the following blocks
+ 1. tx_fsm
+ 2. tx_crc
+ 3. tx_fifo_mgmt
+ 4. deferral
+ 5. backoff
+ ***********************************************************************/
+module g_tx_top(
+ app_clk,
+ send_pause_active,
+ set_fifo_undrn,
+
+
+ //Outputs
+ //TX FIFO management
+ tx_commit_read,
+ tx_dt_rd,
+
+ //MII interface
+ tx2mi_strt_preamble,
+ tx2mi_byte_valid,
+ tx2mi_byte,
+ tx2mi_end_transmit,
+ tx_ch_en, // MANDAR
+
+ //Status to application
+ tx_sts_vld,
+ tx_sts_byte_cntr,
+ tx_sts_fifo_underrun,
+
+
+ //Inputs
+ //MII interface
+ phy_tx_en,
+ phy_tx_er,
+ //application
+ app_send_pause,
+
+ //rx_top
+ rx2tx_pause,
+
+ //configuration
+ cf2tx_tstate_mode,
+ cf2tx_ch_en,
+ cf2df_dfl_single,
+ cf2tx_pad_enable,
+ cf2tx_append_fcs,
+ cf_mac_mode,
+ cf_mac_sa,
+ cf2tx_pause_quanta,
+ cf2tx_force_bad_fcs,
+ //FIFO data
+ app_tx_dt_in,
+ app_tx_fifo_empty,
+ app_tx_rdy,
+
+ //MII
+ mi2tx_byte_ack,
+ app_reset_n,
+ tx_reset_n,
+ tx_clk);
+ input app_reset_n; // Global app_reset for the MAC
+ input tx_reset_n;
+ input tx_clk; // Transmit clock
+
+ input app_send_pause;
+ input [8:0] app_tx_dt_in;
+ input app_tx_fifo_empty;
+ input app_tx_rdy;
+
+ input phy_tx_en; // Transmit data Enable
+ input phy_tx_er; // Transmit Error
+ input cf2tx_tstate_mode; // OFN auth intf fix
+ input cf2tx_ch_en; // Transmit channel Enable
+ input [7:0] cf2df_dfl_single;
+ input cf2tx_pad_enable; // Padding Enabled
+ input cf2tx_append_fcs; // Append CRC to packets
+ input cf2tx_force_bad_fcs; // force bad fcs
+ input [47:0] cf_mac_sa; // MAC Source Address
+ input [15:0] cf2tx_pause_quanta; // Pause Quanta used when sending a pause frame
+ input cf_mac_mode; // Gigabit or 10/100
+
+
+ input rx2tx_pause;
+
+ input mi2tx_byte_ack; // Transmit byte ack from RMII
+ output tx_commit_read;
+ output tx_dt_rd; //get the next fsm data
+
+
+ output tx2mi_strt_preamble; // Start preamble indicated to RMII
+ output tx2mi_byte_valid; // Byte valid from the Tx State Macine
+ output [7:0] tx2mi_byte; // Transmit byte to RMII
+ output tx2mi_end_transmit; // Transmit complete
+
+ output tx_sts_vld; //tx_sts is valid on valid tx_sts_vld
+ output [15:0] tx_sts_byte_cntr;
+ output tx_sts_fifo_underrun;
+
+ output tx_ch_en; // MANDAR
+
+ output send_pause_active; // condor fix
+ output set_fifo_undrn;// Description: At GMII Interface ,
+ // abug after a transmit fifo underun was found.
+ // The packet after a packet that
+ // underran has 1 too few bytes .
+
+ input app_clk; // condor fix
+
+ wire [31:0] tc2tx_fcs;
+ wire set_fifo_undrn;// E3C fix
+
+
+
+
+
+ // Instantiate Defferal block
+ g_deferral U_deferral (
+ //Outputs
+ .df2tx_dfl_dn(df2tx_dfl_dn),
+ .cf2df_dfl_single(cf2df_dfl_single),
+ .phy_tx_en(phy_tx_en),
+ .phy_tx_er(phy_tx_er),
+ .tx_clk(tx_clk),
+ .app_reset_n(tx_reset_n));
+
+
+
+ // Instantiate Transmit State machine block
+ g_tx_fsm U_tx_fsm(
+ .send_pause_active_out(send_pause_active), // condor fix
+ .app_clk(app_clk), // condor fix
+ .set_fifo_undrn(set_fifo_undrn), // E3C fix
+
+ //Outputs
+ .tx_commit_read(tx_commit_read),
+ .tx_dt_rd(tx_dt_rd),
+ //FCS block interface
+ .tx2tc_fcs_active(tx2tc_fcs_active),
+ .tx2tc_gen_crc(tx2tc_gen_crc),
+ //MII or RMII interface signals
+ .tx2mi_strt_preamble(tx2mi_strt_preamble),
+ .tx2mi_byte_valid(tx2mi_byte_valid),
+ .tx2mi_byte(tx2mi_byte),
+ .tx2mi_end_transmit(tx2mi_end_transmit),
+ .tx_ch_en(tx_ch_en),
+ .phy_tx_en(phy_tx_en), // mfilardo. for ofn auth fix.
+ //tx fifo management outputs
+ .tx_sts_vld(tx_sts_vld),
+ .tx_sts_byte_cntr(tx_sts_byte_cntr),
+ .tx_sts_fifo_underrun(tx_sts_fifo_underrun),
+ .app_tx_rdy(app_tx_rdy),
+ .tx_end_frame(app_tx_dt_in[8]),
+ .app_tx_dt_in(app_tx_dt_in[7:0]),
+ .app_tx_fifo_empty(app_tx_fifo_empty),
+ //dfl and back off
+ .df2tx_dfl_dn(df2tx_dfl_dn),
+ .app_send_pause(app_send_pause),
+ //inputs from FCS
+ .tc2tx_fcs(tc2tx_fcs),
+ .cf2tx_tstate_mode(cf2tx_tstate_mode),
+ .cf2tx_ch_en(cf2tx_ch_en),
+ .cf2tx_pad_enable(cf2tx_pad_enable),
+ .cf2tx_append_fcs(cf2tx_append_fcs),
+ .cf_mac_mode(cf_mac_mode),
+ .cf_mac_sa(cf_mac_sa),
+ .cf2tx_pause_quanta(cf2tx_pause_quanta),
+ .cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
+ //RX pause frame received
+ .rx2tx_pause(rx2tx_pause),
+ //MII
+ .mi2tx_byte_ack(mi2tx_byte_ack),
+ .tx_clk(tx_clk),
+ .tx_reset_n(tx_reset_n),
+ .app_reset_n(app_reset_n));
+
+
+
+
+ // Instantiate CRC 32 block for Transmit
+ g_tx_crc32 U_tx_crc32 (
+ // List of outputs.
+ .tx_fcs (tc2tx_fcs),
+ // List of inputs
+ .gen_tx_crc(tx2tc_gen_crc),
+ .tx_reset_crc(tx2mi_strt_preamble),
+ .tx_data(tx2mi_byte),
+ .sclk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
trunk/rtl/gmac/mac/g_tx_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_deferral_rx.v
===================================================================
--- trunk/rtl/gmac/mac/g_deferral_rx.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_deferral_rx.v (revision 12)
@@ -0,0 +1,189 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ deferral.v : This block performs the deferral algorithm for
+ half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
+ This block also implements the optional two part deferral
+ mechanism.
+***********************************************************************/
+
+module g_deferral_rx (
+ rx_dfl_dn,
+ dfl_single,
+ rx_dv,
+ rx_clk,
+ reset_n);
+
+
+ input [7:0] dfl_single; //program with 9.6 ms
+ input rx_dv; //TX frame is done, wait for IPG
+ //used in FULL duplex
+ input rx_clk; //MII provided rx_clk
+ input reset_n;
+
+ output rx_dfl_dn; //when active hold the TX, else
+ //TX can send preamble
+
+ parameter dfl_idle_st = 6'b000000;
+ parameter dfl_dfl_st = 6'b000010;
+ parameter dfl_full_tx_dn_st = 6'b010000;
+ parameter dfl_wipg_st = 6'b100000;
+
+ reg [5:0] curr_dfl_st, nxt_dfl_st;
+ reg rx_dfl_dn;
+ reg strt_dfl;
+ reg [8:0] fst_dfl_cntr;
+ reg [8:0] dfl_cntr;
+ reg [8:0] scnd_dfl_cntr;
+
+ /*****************************************************************
+ * Synchronous process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(posedge rx_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ curr_dfl_st <= dfl_idle_st;
+ else
+ curr_dfl_st <= nxt_dfl_st;
+ end // always @ (posedge rx_clk or negedge reset_n)
+
+ /*****************************************************************
+ * comb process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(curr_dfl_st or dfl_cntr or rx_dv)
+ begin
+ strt_dfl = 0;
+ rx_dfl_dn = 0;
+ nxt_dfl_st = curr_dfl_st;
+
+ case (curr_dfl_st)
+ dfl_idle_st :
+ begin
+ rx_dfl_dn = 1;
+ if (rx_dv)
+ begin
+ rx_dfl_dn = 0;
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // if (rx_dv)
+ else
+ nxt_dfl_st = dfl_idle_st;
+ end // case: dfl_idle_st
+
+ dfl_full_tx_dn_st :
+ begin
+ // full duplex mode, wait till the current tx
+ // frame is transmitted and wait for IPG time,
+ // no need to wait for two part defferal
+ if (!rx_dv)
+ begin
+ strt_dfl = 1;
+ nxt_dfl_st = dfl_wipg_st;
+ end // if (!rx_dv)
+ else
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // case: dfl_full_tx_dn_st
+
+ dfl_wipg_st :
+ begin
+ // This state is reached when there is no transmit
+ // in progress. In this state IPG counter should checked
+ // and upon its expiry indicate deferral done
+ // to tx_fsm block
+ if (dfl_cntr == 9'd0)
+ begin
+ rx_dfl_dn = 1;
+ nxt_dfl_st = dfl_idle_st;
+ end
+ else
+ nxt_dfl_st = dfl_wipg_st;
+ end // case: dfl_wipg_st
+
+ dfl_dfl_st :
+ //wait in this state till deferral time is done
+ //if CRS is active before the deferral time
+ //restart the deferral process again
+ begin
+ begin
+ if (dfl_cntr == 9'd0)
+ begin
+ rx_dfl_dn = 1;
+ nxt_dfl_st = dfl_idle_st;
+ end
+ else
+ nxt_dfl_st = dfl_dfl_st;
+ end //
+ end // case: dfl_dfl_st
+
+ default :
+ begin
+ nxt_dfl_st = dfl_idle_st;
+ end
+ endcase // case (curr_dfl_st)
+ end // always @ (curr_dfl_st )
+
+ //counter for the single phase deferral scheme
+ always @(posedge rx_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ dfl_cntr <= 9'd0;
+ else
+ begin
+ if (strt_dfl)
+ begin
+ dfl_cntr[7:0] <= dfl_single;
+ dfl_cntr[8] <= 0;
+ end
+ else
+ dfl_cntr <= dfl_cntr - 1;
+ end // else: !if(reset_n)
+ end // always @ (posedge rx_clk or negedge reset_n)
+
+endmodule // deferral
+
+
+
+
trunk/rtl/gmac/mac/g_deferral_rx.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/dble_reg.v
===================================================================
--- trunk/rtl/gmac/mac/dble_reg.v (nonexistent)
+++ trunk/rtl/gmac/mac/dble_reg.v (revision 12)
@@ -0,0 +1,90 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ Synchronizes the pulse from one clock to another
+ * clock domain
+***********************************************************************/
+//`timescale 1ns/100ps
+module half_dup_dble_reg (
+ //outputs
+ sync_out_pulse,
+ //inputs
+ in_pulse,
+ dest_clk,
+ reset_n);
+
+ output sync_out_pulse; //output synchronised to slow clock
+ input in_pulse; //input based on fast clock, pulse
+ input dest_clk; //slow clock
+ input reset_n;
+
+ reg s1_sync_out,d_sync_out,s2_sync_out;
+
+ //double register the data in the slow clock domain
+ always @(posedge dest_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ s1_sync_out <= 0;
+ s2_sync_out <= 0;
+ d_sync_out <= 0;
+ end // if (reset_n)
+ else
+ begin
+ s1_sync_out <= in_pulse;
+ s2_sync_out <= s1_sync_out;
+ d_sync_out <= s2_sync_out;
+ end // else: !if(reset_n)
+ end // always @ (posedge dest_clk or negedge reset_n)
+
+ assign sync_out_pulse = d_sync_out;
+
+endmodule // dble_reg
+
+
+
+
+
+
trunk/rtl/gmac/mac/dble_reg.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_rx_fsm.v
===================================================================
--- trunk/rtl/gmac/mac/g_rx_fsm.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_rx_fsm.v (revision 12)
@@ -0,0 +1,1387 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+
+ rx_fsm.v: This verilog file is the receive state machine for the MAC
+ block. It receives nibbles from rmii block. It assembles
+ double words from bytes. Generates writes to Receive FIFO
+ Removes padding and generates appropriate signals to the
+ CRC and Address Filtering block. It also generates the necessary
+ signals to generate status for every frame.
+
+ ***************************************************************/
+/************** MODULE DECLARATION ****************************/
+//`timescale 1ns/100ps
+module g_rx_fsm(
+ // Status information to Applications
+ rx_sts_vld,
+ rx_sts_bytes_rcvd,
+ rx_sts_large_pkt,
+ rx_sts_lengthfield_err,
+ rx_sts_crc_err,
+ rx_sts_runt_pkt_rcvd,
+ rx_sts_rx_overrun,
+ rx_sts_frm_length_err,
+ rx_sts_len_mismatch,
+ // Data Signals to Fifo Management Block
+ clr_rx_error_from_rx_fsm,
+ rx2ap_rx_fsm_wrt,
+ rx2ap_rx_fsm_dt,
+ // Fifo Control Signal to Fifo Management Block
+ rx2ap_commit_write,
+ rx2ap_rewind_write,
+ // To address filtering block
+ // Pause control to Tx block
+ rx2tx_pause_tx,
+ //commit
+ commit_write_done,
+
+ // Global Signals
+ reset_n,
+ phy_rx_clk,
+ // Signals from Mii/Rmii block for Receive data
+ mi2rx_strt_rcv,
+ mi2rx_rcv_vld,
+ mi2rx_rx_byte,
+ mi2rx_end_rcv,
+ mi2rx_extend,
+ mi2rx_frame_err,
+ mi2rx_end_frame,
+ // Rx fifo management signal to indicate overrun
+ rx_fifo_full,
+ ap2rx_rx_fifo_err,
+ // Signal from CRC check block
+ rc2rx_crc_ok,
+ // Signals from Address filtering block
+ af2rx_pause_frame,
+ // Signals from Config Management Block
+ cf2rx_max_pkt_sz,
+ cf2rx_rx_ch_en,
+ cf2rx_strp_pad_en,
+ cf2rx_snd_crc,
+ cf2rx_pause_en,
+ cf2rx_rcv_runt_pkt_en,
+ cf2rx_gigabit_xfr,
+ //A200 change Port added for crs based flow control
+ phy_crs,
+ //A200 change crs flow control enable signal
+ crs_flow_control_enable,
+ //A200 change pause detected pulse for counter
+ pause_frame_detected
+
+ );
+
+
+parameter MIN_FRM_SIZE = 6'h2e ;
+ /******* INPUT & OUTPUT DECLARATIONS *************************/
+ output rx_sts_vld; // Receive status is available for the application
+ output [15:0] rx_sts_bytes_rcvd;
+ output rx_sts_large_pkt;
+ output rx_sts_lengthfield_err;
+ output rx_sts_crc_err;
+ output rx_sts_runt_pkt_rcvd;
+ output rx_sts_rx_overrun;
+ output rx_sts_frm_length_err;
+ output rx_sts_len_mismatch;
+
+ output rx2ap_rx_fsm_wrt; // Receive Fifo Write
+ output [8:0] rx2ap_rx_fsm_dt; // This is 32 bit assembled receive data
+ // with EOP and valid bytes information in it.
+ output rx2ap_commit_write; // This is to RX fifo MGMT to indicate
+ // that the current packet
+ // has to be sent to application
+ output rx2ap_rewind_write; // This indicates the previous packet
+ // in the FIFO has a error
+ // Ignore the packet and restart from the
+ // end of previous packet
+ output rx2tx_pause_tx; // pause frame detected pause transmit
+ output clr_rx_error_from_rx_fsm;
+ output commit_write_done;
+
+ output pause_frame_detected; //A200 change bringing out a pulse to count number
+ //pause frames received.
+
+ input reset_n; // reset from mac application interface
+ input phy_rx_clk; // Reference clock used for RX
+
+ input mi2rx_strt_rcv; // Receive data from the PHY
+ input mi2rx_rcv_vld; // Received nibble is valid
+ input [7:0] mi2rx_rx_byte; // Rx nibble from the RMII/MII block
+ input mi2rx_end_rcv; // This is provided by the RMII/MII
+ // block to indicate
+ // end of receieve
+ input mi2rx_frame_err;
+ input mi2rx_end_frame;
+ input rx_fifo_full;
+ input ap2rx_rx_fifo_err; // Receive error generated by the
+ // RX FIFO MGMT block
+
+ input rc2rx_crc_ok; // CRC of the receiving packet is OK.
+ // Generated by CRC block
+
+ input af2rx_pause_frame; // Detected a pause frame
+
+ input [15:0] cf2rx_max_pkt_sz; // max packet size
+
+ input cf2rx_rx_ch_en; // Receive Enabled
+ input cf2rx_strp_pad_en; // Do not Append padding after the data
+ input cf2rx_snd_crc; // Append CRC to the data
+ // ( This automatically means padding
+ // will be enabled)
+ input cf2rx_pause_en; // This is set when flow control is enabled
+ input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
+ input cf2rx_gigabit_xfr;
+ input mi2rx_extend;
+
+ //A200 change Port added for crs based flow control
+ input phy_crs;
+ //A200 change crs flow control enable signal
+ input crs_flow_control_enable;
+
+
+ /******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
+ reg rx2ap_commit_write;
+ reg rx2ap_rewind_write;
+ reg [8:0] rx2ap_rx_fsm_dt;
+ reg rx2ap_rx_fsm_wrt;
+ wire [31:0] rx_sts_dt;
+ reg [31:0] rx_sts;
+ wire rx2tx_pause_tx;
+ //Renamed to rx2tx_pause_tx_int as rx2tx_pause_tx is genrated in CRS
+ //condition also
+ reg rx2tx_pause_tx_int;
+
+ /*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
+ reg commit_write;
+ reg rewind_write;
+ wire pause_dn;
+ wire look_at_length_field;
+ reg send_crc;
+ reg rcv_pad_data;
+ reg first_dword;
+ wire [15:0] inc_rcv_byte_count;
+ reg [15:0] rcv_byte_count;
+ reg reset_tmp_count;
+ reg ld_length_byte_1,ld_length_byte_2;
+ reg set_crc_error;
+ reg set_byte_allgn_error;
+ reg rx_sts_vld,e_rx_sts_vld;
+ reg padding_needed;
+ reg dec_data_len;
+ reg dec_pad_len;
+ reg gen_eop;
+ reg set_frm_lngth_error;
+ reg set_incomplete_frm;
+ reg byte_boundary;
+ reg error;
+ reg error_seen;
+ reg commit_write_done;
+ reg check_padding;
+ reg check_padding_in;
+ reg gen_pause_det;
+ reg pause_opcode_detected;
+ reg ld_pause_quanta_1,ld_pause_quanta_2;
+ reg [2:0] padding_len_reg;
+ reg [15:0] rcv_length_reg;
+ reg [15:0] length_counter;
+
+ reg [18:0] rx_fsm_cur_st;
+ reg [18:0] rx_fsm_nxt_st;
+ reg [15:0] pause_quanta;
+ reg [1:0] c_pause_ptr;
+ reg [15:0] pause_count;
+ reg [8:0] pause_quanta_count;
+ reg crc_stat_reg;
+ reg rx_runt_pkt_reg;
+ reg large_pkt_reg;
+ reg rx_fifo_overrun_reg;
+ reg frm_length_err_reg;
+ reg [2:0] crc_count;
+ reg inc_shift_counter;
+ reg send_data_to_fifo;
+ wire send_runt_packet;
+ reg [2:0] shift_counter;
+ reg [2:0] bytes_to_fifo;
+ reg [7:0] buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
+ wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
+ reg lengthfield_error;
+ reg lengthfield_err_reg;
+ reg pause_frame_detected;
+ reg pause_seen;
+ reg addr_stat_chk;
+ reg clr_rx_error_from_rx_fsm;
+
+ wire [15:0] adj_rcv_length_reg;
+ wire [15:0] adj_rcv_byte_count;
+ wire [15:0] adj_cf2rx_max_pkt_sz;
+ reg set_tag1_flag, set_tag2_flag;
+
+ parameter rx_fsm_idle_st= 19'b0000000000000000000,
+ rx_fsm_chkdestad_nib1_st = 19'b0000000000000000001,
+ rx_fsm_lk4srcad_nib1_st = 19'b0000000000000000010,
+ rx_fsm_lk4len_byte1_st = 19'b0000000000000000100,
+ rx_fsm_lk4len_byte2_st = 19'b0000000000000001000,
+ rx_fsm_getdt_nib1_st = 19'b0000000000000010000,
+ rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
+ rx_fsm_updstat_st = 19'b0000000000001000000,
+ rx_fsm_chkval_st = 19'b0000000000010000000,
+ rx_fsm_pausectrl_st = 19'b0000000000100000000,
+ rx_fsm_extend_st = 19'b0000000100000000000,
+ rx_fsm_pausequanta_byte1_st = 19'b0000001000000000000,
+ rx_fsm_pausequanta_byte2_st = 19'b0000010000000000000,
+ rx_fsm_wt4_pause_end_st = 19'b0000100000000000000;
+
+ /***************** WIRE ASSIGNMENTS *************************/
+ wire [6:0] dec_pad_length;
+ wire [15:0] inc_length_counter;
+ wire rx_overrun_error;
+ wire commit_condition;
+
+//COMMIT_WRITE CONDITION
+assign commit_condition = ((inc_rcv_byte_count[14:0] == 15'd65)&& !commit_write_done );
+
+
+
+ /******** SEQUENTIAL LOGIC **********************************/
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(rx_ch_en),
+ //inputs
+ .in_pulse(cf2rx_rx_ch_en),
+ .dest_clk(phy_rx_clk),
+ .reset_n(reset_n)
+ );
+
+ // ap2rx_rx_fifo_err signal is generated in rx_clk domain
+ assign rx_overrun_error = ap2rx_rx_fifo_err;
+
+ reg rx_sts_vld_delayed;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rx_sts <= 32'b0;
+ rx_sts_vld <= 1'b0;
+ rx_sts_vld_delayed <= 1'b0;
+ end
+ else
+ begin
+ rx_sts_vld <= rx_sts_vld_delayed;
+ rx_sts_vld_delayed <= e_rx_sts_vld;
+ if (e_rx_sts_vld)
+ rx_sts <= rx_sts_dt;
+ end
+ end
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rx_fsm_cur_st <= rx_fsm_idle_st;
+ check_padding <= 1'b0;
+ end
+ else
+ begin
+ rx_fsm_cur_st <= rx_fsm_nxt_st;
+ check_padding <= check_padding_in;
+ end
+ end
+ reg first_byte_seen;
+
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ if(!reset_n)
+ first_byte_seen <= 1'b0;
+ else if(mi2rx_strt_rcv)
+ first_byte_seen <= 1'b1;
+ else if(mi2rx_rcv_vld)
+ first_byte_seen <= 1'b0;
+
+
+
+// adjust rcv_length reg for packet sizes < 64 bytes
+assign adj_rcv_length_reg = (rcv_length_reg < 8'h2E) ? 8'h2E : rcv_length_reg;
+
+// subtr 18 bytes (sa + da + fcs + t/l)
+assign adj_rcv_byte_count = rcv_byte_count - 8'd18;
+
+// configured max packet size should be 16'd1518.
+assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
+
+
+ always @(posedge phy_rx_clk or negedge reset_n) begin
+ if(!reset_n)
+ pause_opcode_detected <= 1'b0;
+ else
+ begin
+ if(rx_fsm_cur_st == rx_fsm_pausequanta_byte1_st)
+ pause_opcode_detected <= 1'b1;
+ else if(rx_fsm_cur_st == rx_fsm_idle_st)
+ pause_opcode_detected <= 1'b0;
+ end
+ end
+
+ // Following state machine is to receive nibbles from the RMII/MII
+ // block and packetize them to 32 bits with information of EOP and
+ // valid bytes. It also discards packets which are less than minimum
+ // frame size. It performs Address validity and Data validity.
+ always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
+ or cf2rx_snd_crc or cf2rx_pause_en or look_at_length_field
+ or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
+ or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
+ or inc_length_counter or rcv_length_reg or commit_write_done
+ or crc_count or shift_counter or bytes_to_fifo
+ or af2rx_pause_frame or cf2rx_rcv_runt_pkt_en
+ or inc_rcv_byte_count or send_runt_packet
+ or pause_frame_detected or rcv_byte_count or first_dword
+ or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
+ //or pause_opcode_detected)
+ begin
+ rx_fsm_nxt_st = rx_fsm_cur_st;
+ set_tag1_flag = 1'b0;
+ set_tag2_flag = 1'b0;
+ reset_tmp_count = 1'b0;
+ ld_length_byte_1 = 1'b0;
+ ld_length_byte_2 = 1'b0;
+ dec_data_len = 1'b0;
+ dec_pad_len = 1'b0;
+ commit_write = 1'b0;
+ rewind_write = 1'b0;
+ e_rx_sts_vld = 1'b0;
+ set_crc_error = 1'b0;
+ check_padding_in = 1'b0;
+ set_byte_allgn_error = 1'b0;
+ set_incomplete_frm = 1'b0;
+ set_frm_lngth_error = 1'b0;
+ gen_eop = 1'b0;
+ error = 1'b0;
+ byte_boundary= 1'b0;
+ gen_pause_det = 1'b0;
+ ld_pause_quanta_1 = 1'b0;
+ ld_pause_quanta_2 = 1'b0;
+ send_crc = 1'b0;
+ rcv_pad_data = 1'b0;
+ inc_shift_counter = 1'b0;
+ send_data_to_fifo = 1'b0;
+ lengthfield_error = 1'b0;
+ pause_seen = 1'b0;
+ addr_stat_chk = 1'b0;
+ clr_rx_error_from_rx_fsm = 1'b0;
+ //pause_opcode_detected = 1'b0;
+
+
+ casex(rx_fsm_cur_st) // synopsys parallel_case full_case
+ rx_fsm_idle_st:
+ // Waiting for packet from mii block
+ // Continues accepting data only if
+ // receive has been enabled
+ begin
+ //pause_opcode_detected = 1'b0;
+ if(ap2rx_rx_fifo_err)
+ begin
+ clr_rx_error_from_rx_fsm = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if (rx_fifo_full)
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ else if(mi2rx_strt_rcv && rx_ch_en )
+ rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
+ else
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+
+ rx_fsm_chkdestad_nib1_st:
+ begin
+ // collecting the nibbles of destination
+ // address
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ if (rcv_byte_count[2:0] > 5)
+ rewind_write = 1'b1;
+ end
+ end // if (mi2rx_end_rcv)
+
+ else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
+ begin
+ if(cf2rx_pause_en && af2rx_pause_frame)
+ begin
+ pause_seen = 1;
+ rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
+ rewind_write = 1'b1;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
+ end
+ end
+
+ rx_fsm_lk4srcad_nib1_st:
+ // collecting nibbles of source address
+ // in case of termination of packet
+ // or carrier sense error then generate eop
+ // and generate status
+ begin
+ if(ap2rx_rx_fifo_err )
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ rewind_write = 1'b1;
+ end
+ end
+ else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
+ begin
+ if(pause_frame_detected)
+ rx_fsm_nxt_st = rx_fsm_pausectrl_st;
+ else
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
+ end
+ end
+
+ rx_fsm_lk4len_byte1_st:
+ // this state collects the odd nibbles of the length
+ // field.
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ rewind_write = 1'b1;
+ end
+ end
+ else if(mi2rx_rcv_vld)
+ begin
+ ld_length_byte_1 = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
+ end
+
+ rx_fsm_lk4len_byte2_st:
+ // This state generates the even nibbles of the length
+ // field
+ begin
+ if(ap2rx_rx_fifo_err )
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ commit_write = 1'b1;
+ end
+ else
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ rewind_write = 1'b1;
+ end
+ end
+ else if(mi2rx_rcv_vld )
+ begin
+ ld_length_byte_2 = 1'b1;
+ check_padding_in = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
+ end // rx_fsm_lk4len_byte2_st
+
+ rx_fsm_getdt_nib1_st: //state number 7
+ // This state collects the nibbles of the receive data
+ // This state makes a determination to remove padding
+ // only if strip padding is enabled and the length field
+ // detected is less than 64
+ begin
+ if (commit_condition)
+ commit_write = 1'b1;
+
+ if((ap2rx_rx_fifo_err) && !commit_write_done)
+ begin
+ rewind_write = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end // else: !if(mi2rx_end_rcv)
+ else if (ap2rx_rx_fifo_err)
+ begin
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ if(cf2rx_rcv_runt_pkt_en && !(commit_write_done | commit_condition))
+ begin
+ commit_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(!(commit_write_done | commit_condition) && !cf2rx_rcv_runt_pkt_en)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(mi2rx_rcv_vld && (inc_length_counter == rcv_length_reg) &&
+ look_at_length_field)
+ begin
+ dec_data_len = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
+ end
+ else if(mi2rx_rcv_vld && look_at_length_field)
+ begin
+ dec_data_len = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
+ end
+
+ rx_fsm_getpaddt_nib1_st:
+ // This state handles the padded data in case of less than 64
+ // byte packets This handles the odd nibbles
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ if(rcv_byte_count[14:0] <= 15'd64) // mfilardo
+ //if(inc_rcv_byte_count[14:0] <= 15'd64)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ //if(inc_rcv_byte_count[14:0] == 15'd64)
+ if(rcv_byte_count[14:0] == 15'd64) // mfilardo
+ lengthfield_error = 0;
+ else
+ lengthfield_error = 1;
+
+ rx_fsm_nxt_st = rx_fsm_extend_st;
+ end
+ else if(mi2rx_rcv_vld)
+ begin
+ if(cf2rx_strp_pad_en)
+ rcv_pad_data = 1'b1;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
+ end // case: rx_fsm_getpaddt_nib1_st
+
+
+ rx_fsm_extend_st:
+ //This state handles the first extend conditon in the
+ //cf2rx_gigabit_xfr
+ //transfer
+ begin
+ if (mi2rx_extend)
+ begin
+ rx_fsm_nxt_st = rx_fsm_extend_st;
+ end
+ else
+ begin
+ commit_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ end
+ rx_fsm_chkval_st:
+ // This packet generates the validity of the packet
+ // This is reached either on clean or error type
+ // completion of packet.
+ begin
+ if(ap2rx_rx_fifo_err)
+ begin
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(cf2rx_rcv_runt_pkt_en && first_dword)
+ begin
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ case(rcv_byte_count[2:0]) //synopsys full_case parallel_case
+ 3'd1:
+ begin
+ if(shift_counter == 3'd4)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end // if (bytes_to_fifo == rcv_nibble_count[3:1])
+ else
+ send_data_to_fifo = 1'b1;
+ end // if (shift_counter == 3'd4)
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd1
+
+ 3'd2:
+ begin
+ if(shift_counter == 3'd3)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end // if (bytes_to_fifo == rcv_nibble_count[3:1])
+ else
+ send_data_to_fifo = 1'b1;
+ end // if (shift_counter == 3'd3)
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd2
+
+ 3'd3:
+ begin
+ if(shift_counter == 3'd2)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else
+ send_data_to_fifo = 1'b1;
+ end // if (shift_counter == 3'd2)
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd3
+
+ 3'd4:
+ begin
+ if(shift_counter == 3'd1)
+ begin
+ if(bytes_to_fifo == rcv_byte_count[2:0])
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end // if (bytes_to_fifo == rcv_nibble_count[3:1])
+ else
+ send_data_to_fifo = 1'b1;
+ end
+ else
+ inc_shift_counter = 1;
+ end // case: 3'd4
+ default:
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ gen_eop = 1'b0;
+ end
+ endcase // case(rcv_nibble_count[3
+ end // if (cf2rx_rcv_runt_pkt_en && first_dword)
+ else if(((cf2rx_snd_crc || send_runt_packet || look_at_length_field)
+ && crc_count == 3'd4))
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else if(send_runt_packet || look_at_length_field)
+ begin
+ send_crc = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(!cf2rx_snd_crc)
+ begin
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_updstat_st;
+ end
+ else
+ begin
+ send_crc = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ end // case: rx_fsm_chkval_st
+
+ rx_fsm_updstat_st:
+ // This state updates the status to the application
+ // This allows the application to determine the validity
+ // of the packet so that it can take the necessary action
+ begin
+ e_rx_sts_vld = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+
+ rx_fsm_pausectrl_st:
+ // collecting odd nibbles of pause control
+ // in case of termination of packet
+ // or carrier sense error then generate eop
+ // and generate status
+ begin
+ if(mi2rx_end_rcv)
+ begin
+ set_incomplete_frm = 1'b1;
+ error = 1'b1;
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ if(cf2rx_rcv_runt_pkt_en)
+ commit_write = 1'b1;
+ else
+ rewind_write = 1'b1;
+ end
+ else if(mi2rx_rcv_vld)
+ case(inc_rcv_byte_count[1:0])
+ 2'b01 : if(mi2rx_rx_byte != 8'h88)
+ rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
+ 2'b10 : if(mi2rx_rx_byte != 8'h08)
+ rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
+ 2'b11 : if(mi2rx_rx_byte != 8'h00)
+ rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
+ 2'b00 : begin
+ if(mi2rx_rx_byte != 8'h01)
+ rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
+ else
+ rx_fsm_nxt_st = rx_fsm_pausequanta_byte1_st;
+ end
+ endcase
+ else
+ rx_fsm_nxt_st = rx_fsm_pausectrl_st;
+ end // case: rx_fsm_pausectrl_nib1_st
+
+ rx_fsm_pausequanta_byte1_st:
+ // This state collects the odd nibbles of the receive data
+ begin
+ //pause_opcode_detected = 1'b1;
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ set_incomplete_frm = 1'b1;
+ error = 1'b1;
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ if(cf2rx_rcv_runt_pkt_en)
+ commit_write = 1'b1;
+ else
+ rewind_write = 1'b1;
+ end
+ else if(mi2rx_rcv_vld)
+ begin
+ ld_pause_quanta_1 = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_pausequanta_byte2_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_pausequanta_byte1_st;
+ end // case: rx_fsm_pausequanta_nib1_st
+
+ rx_fsm_pausequanta_byte2_st:
+ // This state collects the even nibbles of the receive data.
+ begin
+ //pause_opcode_detected = 1'b1;
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ set_incomplete_frm = 1'b1;
+ error = 1'b1;
+ gen_eop = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_chkval_st;
+ end
+ else if(mi2rx_rcv_vld )
+ begin
+ ld_pause_quanta_2 = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_pausequanta_byte2_st;
+ end // case: rx_fsm_pausequanta_nib2_st
+
+ rx_fsm_wt4_pause_end_st:
+ begin
+ //pause_opcode_detected = 1'b1;
+ if(ap2rx_rx_fifo_err)
+ begin
+ rewind_write = 1'b1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if(mi2rx_end_rcv)
+ begin
+ if(rcv_byte_count[14:0] < 15'd64) // mfilardo
+ begin
+ lengthfield_error = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else if(rc2rx_crc_ok)
+ begin
+ gen_pause_det = 1;
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ else
+ rx_fsm_nxt_st = rx_fsm_wt4_pause_end_st;
+ end // case: rx_fsm_wt4_pause_end_st
+ default:
+ begin
+ rx_fsm_nxt_st = rx_fsm_idle_st;
+ end
+ endcase // casex(rx_fsm_cur_st)
+ end // always @ (rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en...
+
+ always @(inc_rcv_byte_count)
+ begin
+ if(inc_rcv_byte_count[14:0] < 15'd6)
+ first_dword = 1'b1;
+ else
+ first_dword = 1'b0;
+ end // always @ (inc_rcv_nibble_count or...
+
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ crc_count <= 3'b000;
+ else if(mi2rx_strt_rcv)
+ crc_count <= 3'b000;
+ else if(send_crc)
+ crc_count <= crc_count + 1;
+ end // always @ (posedge phy_rx_clk...
+
+ // These signals are used as intermediate flags to determine
+ // whether to commit pointer or not to commit pointers
+ // to the application
+ // error_seen helps in tracking errors which could occurs in between
+ // packet transfer
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ commit_write_done <= 1'b1;
+ error_seen <= 1'b0;
+ end
+ else if(mi2rx_strt_rcv)
+ begin
+ commit_write_done <= 1'b0;
+ error_seen <= 1'b0;
+ end
+ else
+ begin
+ if(commit_write)
+ commit_write_done <= 1'b1;
+ if(error)
+ error_seen <= 1'b1;
+ end
+ end // always @ (posedge phy_rx_clk...
+
+ assign look_at_length_field = cf2rx_strp_pad_en &&
+ (rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
+ assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
+ (rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
+
+ //
+ // Detect pause control frame
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ pause_frame_detected <= 1'b0;
+ else if(mi2rx_end_rcv)
+ pause_frame_detected <= 1'b0;
+ else if(af2rx_pause_frame && cf2rx_pause_en && pause_seen)
+ pause_frame_detected <= 1'b1;
+ end // always @ (posedge phy_rx_clk...
+
+ // counter used for decrementing pause to transmit
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ pause_count <= 16'b0;
+ else
+ begin
+ if(~cf2rx_pause_en)
+ pause_count <= 'h0;
+ else if(gen_pause_det & pause_opcode_detected)
+ pause_count <= pause_quanta;
+ //else if(pause_quanta_count == 9'd511)
+ else if( ( cf2rx_gigabit_xfr && (pause_quanta_count[5:0] == 6'd63 )) ||
+ (~cf2rx_gigabit_xfr && (pause_quanta_count[6:0] == 7'd127)) ) // mfilardo pause bit time fix. A pause quanta should be 512 bit times.
+ pause_count <= pause_count - 1;
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk...
+
+ // counter used for decrementing pause quanta count
+ // which is 512 bit times
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ pause_quanta_count <= 9'b0;
+ else
+ begin
+ if(pause_dn)
+ pause_quanta_count <= 9'b0;
+ else if(rx2tx_pause_tx_int)
+ pause_quanta_count <= pause_quanta_count + 1;
+ end // else: !if(!reset_n)
+ end
+
+ assign pause_dn = ~|pause_count & rx2tx_pause_tx_int;
+ //A200 change :
+ //When phy_crs input is asserted rx2tx_pause_tx which stops the
+ //frame transmission. Same function has been done on receiving pause
+ //frame so phy_crs is ored with pause receive signal when config is
+ //zero.
+ assign rx2tx_pause_tx = rx2tx_pause_tx_int |
+ (phy_crs & ~crs_flow_control_enable);
+
+ // Generation pause to tx_fsm
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ rx2tx_pause_tx_int <= 1'b0;
+ else
+ begin
+ if(pause_dn)
+ rx2tx_pause_tx_int <= 1'b0;
+ else if(gen_pause_det)
+ rx2tx_pause_tx_int <= 1'b1;
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk...
+
+ assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ rcv_byte_count <= 16'h0000;
+ else if(mi2rx_strt_rcv)
+ rcv_byte_count <= 16'h0000;
+ else if(mi2rx_rcv_vld)
+ rcv_byte_count <= inc_rcv_byte_count;
+ end // always @ (posedge phy_rx_clk...
+
+ // This signal is asserted wheneven there is no valid transfer on the
+ // line. Valid transfer is only between mi2rx_strt_rcv and
+ // mi2rx_end_rcv. In case
+ // of rewind write transfer becomes invalid. Such data should not be
+ // written in to the fifo
+ reg dt_xfr_invalid;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ dt_xfr_invalid <= 1;
+ else if(rewind_write || ap2rx_rx_fifo_err)
+ dt_xfr_invalid <= 1;
+ else if(mi2rx_strt_rcv)
+ dt_xfr_invalid <= 0;
+ end
+ // This is the mux to gather nibbles to two octets for the length field
+ // of the register
+ assign inc_length_counter = length_counter + 16'h1;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rcv_length_reg <= 16'b0;
+ length_counter <= 16'b0;
+ end // if (reset_n)
+ else if (rx_ch_en)
+ begin
+ if(mi2rx_strt_rcv)
+ begin
+ length_counter <= 16'b0;
+ rcv_length_reg <= 16'b0;
+ end
+ else if(dec_data_len )
+ length_counter <= inc_length_counter;
+ else
+ begin
+ if(ld_length_byte_1)
+ begin
+ rcv_length_reg[15:8] <= mi2rx_rx_byte;
+ end
+ else if(ld_length_byte_2)
+ begin
+ rcv_length_reg[7:0] <= mi2rx_rx_byte;
+ end
+ end // else: !if(dec_data_len)
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk...
+
+ // This signal helps in making sure that when packets are received the
+ // channel is enabled else ignore the complete packet until next start
+ // of packet
+ reg enable_channel;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ enable_channel <= 0;
+ else if(gen_eop)
+ enable_channel <= 0;
+ else if(mi2rx_strt_rcv && rx_ch_en)
+ enable_channel <= 1;
+ end
+
+ // This is the decremented padding length register
+ // Once it reaches zero CRC should follow
+ assign dec_pad_length = padding_len_reg - 7'h1;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ padding_needed <= 1'b0;
+ padding_len_reg <= 6'b0;
+ end
+ else if(mi2rx_strt_rcv)
+ begin
+ padding_needed <= 1'b0;
+ padding_len_reg <= 6'b0;
+ end
+ else if(look_at_length_field &&
+ check_padding)
+ begin
+ padding_len_reg <= MIN_FRM_SIZE - rcv_length_reg[5:0];
+ padding_needed <= 1'b1;
+ end
+ else if(dec_pad_len)
+ begin
+ padding_len_reg <= dec_pad_len;
+ padding_needed <= padding_needed;
+ end
+ end // always @ (posedge phy_rx_clk...
+
+ /*********************************************************
+ Status Generation for Receive packets
+ Statuses in this case are checked at end of receive packets
+ and are registered and provided inthe next state along with
+ rx_sts_valid bit asserted
+ *********************************************************/
+
+ reg[14:0] fifo_byte_count;
+ wire [14:0] inc_fifo_byte_count;
+ wire [14:0] dec_fifo_byte_count;
+ assign inc_fifo_byte_count = fifo_byte_count + 15'h1;
+ assign dec_fifo_byte_count = fifo_byte_count - 15'h1;
+
+ always @(posedge phy_rx_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ fifo_byte_count <= 15'd0;
+ else if(rewind_write || mi2rx_strt_rcv)
+ fifo_byte_count <= 15'd0;
+ else if(rx2ap_rx_fsm_wrt)
+ fifo_byte_count <= inc_fifo_byte_count;
+ end
+
+ reg length_sz_mismatch;
+
+ assign rx_sts_dt[31:16] = (e_rx_sts_vld && ap2rx_rx_fifo_err) ?
+ {dec_fifo_byte_count + 16'h1} : {fifo_byte_count + 16'h1};
+ assign rx_sts_dt[15:13] = 3'd0;
+ assign rx_sts_dt[12] = length_sz_mismatch;
+ assign rx_sts_dt[11] = 1'b0;
+ assign rx_sts_dt[10] = large_pkt_reg;
+ assign rx_sts_dt[7] = lengthfield_err_reg;
+ assign rx_sts_dt[6] = crc_stat_reg;
+ assign rx_sts_dt[5] = rx_runt_pkt_reg;
+ assign rx_sts_dt[4] = rx_fifo_overrun_reg;
+ assign rx_sts_dt[2] = frm_length_err_reg;
+ assign rx_sts_dt[1:0] = 2'd0;
+
+ wire rx_sts_large_pkt;
+ wire [15:0] rx_sts_bytes_rcvd;
+ wire rx_sts_lengthfield_err;
+ wire rx_sts_crc_err;
+ wire rx_sts_runt_pkt_rcvd;
+ wire rx_sts_rx_overrun;
+ wire rx_sts_frm_length_err;
+ wire rx_sts_len_mismatch;
+
+ assign rx_sts_bytes_rcvd = rx_sts[31:16];
+ assign rx_sts_len_mismatch = rx_sts[12];
+ assign rx_sts_large_pkt = rx_sts[10];
+ assign rx_sts_lengthfield_err = rx_sts[7];
+ assign rx_sts_crc_err = rx_sts[6];
+ assign rx_sts_runt_pkt_rcvd = rx_sts[5];
+ assign rx_sts_rx_overrun = rx_sts[4];
+ assign rx_sts_frm_length_err = rx_sts[2];
+
+
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ crc_stat_reg <= 1'b0;
+ frm_length_err_reg <= 1'b0;
+ lengthfield_err_reg <= 1'b0;
+ rx_fifo_overrun_reg <= 1'b0;
+ rx_runt_pkt_reg <= 1'b0;
+ large_pkt_reg <= 1'b0;
+ length_sz_mismatch <= 1'b0;
+ end
+ else if(mi2rx_strt_rcv)
+ begin
+ crc_stat_reg <= 1'b0;
+ frm_length_err_reg <= 1'b0;
+ lengthfield_err_reg <= 1'b0;
+ rx_fifo_overrun_reg <= 1'b0;
+ rx_runt_pkt_reg <= 1'b0;
+ large_pkt_reg <= 1'b0;
+ length_sz_mismatch <= 1'b0;
+ end
+ else
+ begin
+ if(rx_overrun_error)
+ rx_fifo_overrun_reg <= 1'b1;
+
+ if(lengthfield_error)
+ lengthfield_err_reg <= 1'b1;
+
+ if(mi2rx_end_rcv && mi2rx_frame_err)
+ frm_length_err_reg <= 1'b1;
+
+ if(mi2rx_end_rcv)
+ begin
+ if(!rc2rx_crc_ok)
+ crc_stat_reg <= 1'b1;
+ if(rcv_byte_count[14:0] < 15'd64)
+ rx_runt_pkt_reg <= 1'b1;
+ if(rcv_byte_count[14:0] > adj_cf2rx_max_pkt_sz)
+ large_pkt_reg <= 1'b1;
+ if( (adj_rcv_byte_count[15:0] != adj_rcv_length_reg) && (adj_rcv_length_reg <= 16'd1500) )
+ length_sz_mismatch <= 1'b1;
+ end // if (mi2rx_end_rcv)
+ end // else: !if(mi2rx_strt_rcv)
+ end // always @ (posedge phy_rx_clk...
+
+ /***************************************************/
+ //
+ // Additions for Byte operation
+ //
+ /***************************************************/
+ always @(posedge phy_rx_clk or
+ negedge reset_n)
+ begin
+ if(!reset_n)
+ shift_counter <= 3'd0;
+ else if(mi2rx_strt_rcv)
+ shift_counter <= 3'd0;
+ else if(inc_shift_counter)
+ shift_counter <= shift_counter + 1;
+ end // always @ (posedge phy_rx_clk or...
+
+ always @(posedge phy_rx_clk or
+ negedge reset_n)
+ begin
+ if(!reset_n)
+ bytes_to_fifo <= 3'd0;
+ else if(mi2rx_strt_rcv)
+ bytes_to_fifo <= 3'd1;
+ else if(send_data_to_fifo)
+ bytes_to_fifo <= bytes_to_fifo + 1;
+ end // always @ (posedge phy_rx_clk or...
+
+ wire[8:0] e_rx_fsm_dt;
+ wire e_rx_fsm_wrt;
+ assign e_rx_fsm_dt[7:0] = buf_latch4;
+// assign e_rx_fsm_dt[8] = (rx_fifo_full) ? 1'b1 :gen_eop;
+ assign e_rx_fsm_dt[8] = gen_eop;
+
+ always @(posedge phy_rx_clk or
+ negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ rx2ap_rx_fsm_dt <= 9'd0;
+ rx2ap_rx_fsm_wrt <= 1'b0;
+ rx2ap_commit_write <= 1'b0;
+ rx2ap_rewind_write <= 1'b0;
+ end
+ else
+ begin
+ rx2ap_rx_fsm_wrt <= e_rx_fsm_wrt && (!ap2rx_rx_fifo_err);
+ rx2ap_rx_fsm_dt <= e_rx_fsm_dt;
+ rx2ap_commit_write <= commit_write;
+ rx2ap_rewind_write <= rewind_write;
+ end
+ end // always @ (posedge phy_rx_clk or...
+
+ assign e_rx_fsm_wrt = ((enable_channel &&
+ mi2rx_rcv_vld && !first_dword) ||
+ (enable_channel &&
+ (gen_eop || send_crc)) ||
+ (enable_channel && send_data_to_fifo)) && !rcv_pad_data
+ && !dt_xfr_invalid && !rewind_write;
+ assign ld_buf = enable_channel && !rcv_pad_data && (|rcv_byte_count == 1) &&
+ (mi2rx_rcv_vld) || send_crc || inc_shift_counter || send_data_to_fifo;
+
+ assign ld_buf4 = ld_buf ;
+ assign ld_buf3 = ld_buf ;
+ assign ld_buf2 = ld_buf ;
+ assign ld_buf1 = ld_buf ;
+ always @(posedge phy_rx_clk
+ or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ buf_latch4 <= 8'b0;
+ buf_latch3 <= 8'b0;
+ buf_latch2 <= 8'b0;
+ buf_latch1 <= 8'b0;
+ buf_latch0 <= 8'b0;
+ end
+ else
+ begin
+ if(ld_buf4)
+ buf_latch4 <= buf_latch3;
+
+ if(ld_buf3)
+ buf_latch3 <= buf_latch2;
+
+ if(ld_buf2)
+ buf_latch2 <= buf_latch1;
+
+ if(ld_buf1)
+ buf_latch1 <= buf_latch0;
+
+ if (rx_ch_en)
+ begin
+ if(mi2rx_strt_rcv)
+ begin
+ buf_latch0 <= 8'b0;
+ end
+ else
+ begin
+ if(mi2rx_rcv_vld && !rcv_pad_data)
+ begin
+ buf_latch0 <= mi2rx_rx_byte;
+ end
+ end // else: !if(mi2rx_strt_rcv)
+ end // if (rx_ch_en)
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk...
+
+ // This is used load the pause quanta value on received
+ // pause control frame
+ always @(posedge phy_rx_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ pause_quanta <= 16'b0;
+ c_pause_ptr <= 2'b0;
+ end // if (reset_n)
+ else if (rx_ch_en)
+ begin
+ if(mi2rx_strt_rcv)
+ begin
+ pause_quanta <= 16'b0;
+ c_pause_ptr <= 2'b0;
+ end
+ else
+ begin
+ if(ld_pause_quanta_1)
+ begin
+ pause_quanta[15:8] <= mi2rx_rx_byte;
+ end
+ else if(ld_pause_quanta_2)
+ begin
+ pause_quanta[7:0] <= mi2rx_rx_byte;
+ end
+ end // else: !if(mi2rx_strt_rcv)
+ end // else: !if(!reset_n)
+ end
+
+endmodule
trunk/rtl/gmac/mac/g_rx_fsm.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_mii_intf.v
===================================================================
--- trunk/rtl/gmac/mac/g_mii_intf.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_mii_intf.v (revision 12)
@@ -0,0 +1,1136 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+/***************************************************************
+ Description:
+
+ mii_intf.v: This verilog file is reduced mii interface for ethenet
+ The transmit state machine generates a condition to indicate
+ start transmit. This is done using strt_preamble. The transmit
+ state machine upon detecting strt_preamble generates pre-amble
+ and start of frame de-limiter and then starts accepting the data
+ from the transmit block by asserting the transmit nibble ack.
+
+ ***************************************************************/
+/************** MODULE DECLARATION ****************************/
+module g_mii_intf(
+ // Data and Control Signals to tx_fsm and rx_fsm
+ mi2rx_strt_rcv,
+ mi2rx_rcv_vld,
+ mi2rx_rx_byte,
+ mi2rx_end_rcv,
+ mi2rx_extend,
+ mi2rx_frame_err,
+ mi2rx_end_frame,
+ mi2rx_crs,
+ mi2tx_byte_ack,
+ mi2tx_slot_vld,
+ cfg_uni_mac_mode_change,
+
+ // Phy Signals
+ phy_tx_en,
+ phy_tx_er,
+ phy_txd,
+ phy_tx_clk,
+ phy_rx_clk,
+ tx_reset_n,
+ rx_reset_n,
+ phy_rx_er,
+ phy_rx_dv,
+ phy_rxd,
+ phy_crs,
+ // rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
+ rx_sts_rx_er_reg,
+
+ // Reset signal
+ app_reset_n,
+
+ // Signals from Config Management
+ cf2mi_loopback_en,
+ cf2mi_rmii_en,
+ cf_mac_mode,
+ cf_chk_rx_dfl,
+ cf_silent_mode,
+
+ // Signal from Application to transmit JAM
+ app_send_jam,
+ df2rx_dfl_dn,
+
+ // Inputs from Transmit FSM
+ tx2mi_strt_preamble,
+ tx2mi_end_transmit,
+ tx2mi_tx_byte,
+ tx_ch_en
+ );
+
+
+parameter NO_GMII_PREAMBLE = 5'b00111;
+parameter NO_MII_PREAMBLE = 5'b01111;
+parameter NO_RMII_PREAMBLE = 5'b11111;
+parameter GMII_JAM_COUNT = 5'b0011;
+parameter MII_JAM_COUNT = 5'b0111;
+parameter RMII_JAM_COUNT = 5'b1111;
+
+ /******* INPUT & OUTPUT DECLARATIONS *************************/
+
+ output mi2rx_strt_rcv; // This is generated by the MII block to indicate start
+ // of receive data.
+ output mi2rx_rcv_vld; // This signal is asserted by MII on reception of valid
+ // bytes to indicate to the RX block to accept data from PHY
+ output[7:0] mi2rx_rx_byte; // This the receive data from the PHY gathered as bytes
+ output mi2rx_end_rcv; // This signal is asserted with the last data assembled
+ output mi2rx_extend; // This signal is asserted during carrier extension (Receive)
+ output mi2rx_frame_err; // This signal is asserted during Dibit Error (In RMII Mode)
+ // or Nibble Error in (MII Mode)
+ output mi2rx_end_frame; // End of Frame
+ output mi2rx_crs; // CRS signal in rx_clk domain
+ output mi2tx_byte_ack; // MII block acknowledges a byte during transmit
+ output mi2tx_slot_vld; // MII block acknowledges valid slot during transmit // mfilardo
+
+ output phy_tx_en; // Enable data on TX
+ output phy_tx_er; // Transmit Error (Used in Carrier Extension in 1000 Mode)
+ output[7:0] phy_txd; // Transmit data on the line
+
+ input phy_tx_clk; // Transmit Clock in 10/100 Mb/s
+
+ output rx_sts_rx_er_reg; // rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
+ input app_reset_n; // reset from the application interface
+
+ input phy_rx_clk; // Receive Clock in 10/100/1000 Mb/s
+ input phy_rx_er; // Receive Error. Used in Carrier Extension in 1000 Mode
+ input phy_rx_dv; // Receive Data Valid from the PHY
+ input[7:0] phy_rxd; // Receive Data
+ input phy_crs; // Carrier Sense from the line
+
+ input tx_reset_n;
+ input rx_reset_n;
+
+
+ input cf2mi_loopback_en; // loop back enable
+ input cf2mi_rmii_en; // RMII Mode
+ input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
+ input cf_chk_rx_dfl; // Check for Deferal
+ input cf_silent_mode; // PHY Inactive
+ input app_send_jam; // Send a Jam Sequence (From the Application)
+ input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
+ input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
+ // preamble on the line
+ input tx2mi_end_transmit; // This is provided by the TX block to
+ // indicate end of transmit
+ input[7:0] tx2mi_tx_byte; // 8 bits of data from Tx block
+ input tx_ch_en; // Transmitt Enable
+ input cfg_uni_mac_mode_change;
+
+ /******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
+ reg phy_tx_en;
+ reg mi2tx_byte_ack;
+ reg mi2tx_slot_vld;
+ reg [7:0] phy_txd;
+ wire [7:0] mi2rx_rx_byte;
+ reg [7:0] mi2rx_rx_byte_in;
+ reg mi2rx_extend;
+ reg mi2rx_extend_err;
+ reg mi2rx_strt_rcv;
+ reg mi2rx_end_rcv;
+ reg mi2rx_rcv_vld;
+ reg mi2rx_frame_err;
+
+ /*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
+
+ reg [4:0] tx_preamble_cnt_val;
+ reg [4:0] jam_count;
+ reg [4:0] jam_count_reg;
+
+
+ reg strt_rcv_in;
+ reg end_rcv_in;
+ reg rx_dv_in;
+ reg rx_er_in;
+ reg rcv_valid_in;
+
+
+
+ reg [7:0] rxd_in;
+
+ parameter mii_rx_idle_st = 3'd0, mii_rx_pre_st = 3'd1,
+ mii_rx_byte_st = 3'd2, mii_rx_end_st = 3'd3,
+ mii_rx_dibit_st = 3'd4, mii_rx_nibble_st = 3'd5;
+
+ reg [2:0] mii_rx_nxt_st;
+ reg [2:0] mii_rx_cur_st;
+
+ parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
+ mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
+ mii_tx_jam_st = 4'd4, mii_tx_nibble_st = 4'd5,
+ mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
+ mii_tx_dibit_end_st = 4'd8;
+
+ reg [3:0] mii_tx_cur_st;
+ reg [3:0] mii_tx_nxt_st;
+
+ wire send_jam;
+ wire receive_detect;
+ wire pre_condition;
+ wire sfd_condition;
+ wire tx_en;
+ wire tx_er;
+ wire [7:0] txd;
+ wire byte_boundary_rx, byte_boundary_tx;
+
+ reg tx_en_in;
+ reg tx_err_in;
+ reg tx_ext_in;
+ reg tx_pre_in;
+ reg tx_sfd_in;
+ reg tx_jam_in;
+ reg tx_xfr_ack_in;
+ reg inc_preamble_cntr;
+ reg rst_preamble_cntr;
+ reg inc_jam_cntr;
+ reg rst_jam_cntr;
+ reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
+ reg rx_dv;
+ reg rx_er;
+ reg rcv_err_in;
+ reg mi2rx_end_frame_in;
+
+ reg [1:0] tx_dibit_in;
+ reg mi2rx_extend_in, mi2rx_extend_err_in, mi2rx_end_frame;
+ reg crs_in;
+ reg phy_tx_er;
+
+ wire dibit_check_rx, dibit_check_tx;
+ wire nibble_check_rx, nibble_check_tx;
+ wire pre_condition_gmii, pre_condition_mii, pre_condition_rmii;
+ wire sfd_condition_gmii, sfd_condition_mii, sfd_condition_rmii;
+ wire [3:0] tx_nibble_in;
+ reg [7:0] rxd;
+ wire receive_detect_pulse;
+ reg d_receive_detect;
+
+
+ reg lb_tx_en, lb_tx_er;
+ reg rx_dv_del;
+ reg [1:0] rxd_del;
+ reg rx_dfl_dn;
+ reg rx_dfl_dn_reg;
+
+
+ /******** SEQUENTIAL LOGIC **********************************/
+
+ // This logic generates appropriate receive data valid
+ // in case of loop back
+ always @(tx_en or phy_rxd or txd or phy_rx_dv or tx_er or phy_crs
+ or cf2mi_loopback_en or phy_tx_en or phy_rx_er or
+ cf2mi_rmii_en or cf_mac_mode)
+ begin
+ if(cf2mi_loopback_en)
+ begin
+ rx_dv_in = tx_en;
+ rx_er_in = tx_er;
+ rxd_in = txd;
+ crs_in = (tx_en | tx_er) && cf_mac_mode;
+ end // if (mii_loopback_en)
+ else
+ begin
+ rx_dv_in = phy_rx_dv ;
+ rx_er_in = phy_rx_er;
+ rxd_in = phy_rxd;
+ // *** NOTE ****
+ // phy_crs should be a combination of crs and tx_en
+ // In Full Duplex tx_en determines deferral in half duplex
+ // crs determines deferral
+ crs_in = (tx_en | tx_er);
+ end // else: !if(mii_loopback_en)
+ end
+
+
+ // Following state machine is to detect start preamble and
+ // transmit preamble and sfd and then the data.
+ // This state machine also generates acknowledge to TX block
+ // to allow the TX block to update its byte pointers
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ begin
+ mii_tx_cur_st <= mii_tx_idle_st;
+ end
+ else if (tx_ch_en)
+ begin
+ mii_tx_cur_st <= mii_tx_nxt_st;
+ end
+ else
+ begin
+ mii_tx_cur_st <= mii_tx_idle_st;
+ end
+ end
+
+ always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
+ or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
+ or jam_count or tx_xfr_cnt or send_jam or receive_detect
+ or receive_detect_pulse or jam_count_reg or jam_count or cfg_uni_mac_mode_change)
+ begin
+
+ mii_tx_nxt_st = mii_tx_cur_st;
+ tx_en_in = 1'b0;
+ tx_pre_in = 1'b0;
+ tx_sfd_in = 1'b0;
+ tx_err_in = 1'b0;
+ tx_ext_in = 1'b0;
+ tx_jam_in = 1'b0;
+ inc_preamble_cntr = 1'b0;
+ rst_preamble_cntr = 1'b0;
+ inc_jam_cntr = 1'b0;
+ rst_jam_cntr = 1'b0;
+ tx_xfr_ack_in = 1'b0;
+
+ casex(mii_tx_cur_st) // synopsys parallel_case full_case
+
+ mii_tx_idle_st:
+ // wait from start from transmit state machine
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ inc_preamble_cntr = 1'b1;
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+
+ mii_tx_pre_st:
+ // This state generates the preamble to be transmitted and
+ // generates SFD before transitioning the data state
+ begin
+ if((tx_preamble_cnt_val == NO_GMII_PREAMBLE) && cf_mac_mode)
+ begin
+ tx_en_in = 1'b1;
+ tx_sfd_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ rst_preamble_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ else if((tx_preamble_cnt_val == NO_MII_PREAMBLE) && !cf_mac_mode &&
+ !cf2mi_rmii_en)
+ begin
+ tx_en_in = 1'b1;
+ tx_sfd_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ rst_preamble_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ else if((tx_preamble_cnt_val == NO_RMII_PREAMBLE) && !cf_mac_mode &&
+ cf2mi_rmii_en)
+ begin
+ tx_en_in = 1'b1;
+ tx_sfd_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ rst_preamble_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_dibit_st;
+ end
+ else
+ begin
+ inc_preamble_cntr = 1'b1;
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ end
+
+ mii_tx_byte_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_end_st;
+ end
+ else if (!cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ end
+
+ /*mii_tx_byte_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_end_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ end*/
+
+ mii_tx_jam_st:
+ begin
+ if(jam_count == jam_count_reg)
+ begin
+ tx_en_in = 1'b1;
+ tx_jam_in = 1'b1;
+ rst_jam_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_jam_in = 1'b1;
+ inc_jam_cntr = 1'b1;
+ mii_tx_nxt_st = mii_tx_jam_st;
+ end
+ end
+
+ mii_tx_end_st:
+ // This state checks for the end of transfer
+ // and extend for carrier extension
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ end
+
+ /*mii_tx_nibble_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && !byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_end_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ end*/
+
+ mii_tx_nibble_st: // Mandar
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && !byte_boundary_tx )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_end_st;
+ end
+ else if (cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_byte_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_nibble_st;
+ end
+ end
+
+ mii_tx_nibble_end_st:
+ // This state checks for the end of transfer
+ // and extend for carrier extension
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b0;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ end
+
+ mii_tx_dibit_st:
+ // This state picks up a byte from the transmit block
+ // before transmitting on the line
+ begin
+ if(tx2mi_end_transmit && (tx_xfr_cnt[0]) && (tx_xfr_cnt[1]) )
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_dibit_end_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ tx_xfr_ack_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_dibit_st;
+ end
+ end
+
+ mii_tx_dibit_end_st:
+ // This state checks for the end of transfer
+ // and extend for carrier extension
+ begin
+ if(tx2mi_strt_preamble)
+ begin
+ tx_en_in = 1'b1;
+ tx_pre_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_pre_st;
+ end
+ else
+ begin
+ tx_en_in = 1'b1;
+ mii_tx_nxt_st = mii_tx_idle_st;
+ end
+ end
+ endcase
+ end // end always
+
+ // All the data, enable and ack signals leaving this blocks are
+ // registered tx_data and tx_en are outputs going to PHY tx_nibble_ack
+ // is indicating to the TX block of acceptance of data nibble
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ begin
+ lb_tx_en <= 1'b0;
+ lb_tx_er <= 1'b0;
+ phy_tx_en <= 1'b0;
+ phy_tx_er <= 1'b0;
+ mi2tx_byte_ack <= 1'b0;
+ mi2tx_slot_vld <= 1'b0;
+ end
+ else
+ begin
+ lb_tx_en <= tx_en_in;
+ lb_tx_er <= tx_err_in;
+ phy_tx_en <= (cf_silent_mode) ? 1'b0 : tx_en_in;
+ phy_tx_er <= (cf_silent_mode) ? 1'b0 : tx_err_in;
+ mi2tx_byte_ack <= (cf_mac_mode || (cf2mi_rmii_en && tx_xfr_cnt[1] && !tx_xfr_cnt[0]) ||
+ (!cf2mi_rmii_en && nibble_check_tx)) ? tx_xfr_ack_in : 1'b0;
+ mi2tx_slot_vld <= (cf_mac_mode || (cf2mi_rmii_en && tx_slot_xfr_cnt[1] && !tx_slot_xfr_cnt[0]) ||
+ (!cf2mi_rmii_en && tx_slot_xfr_cnt[0] )) ? (tx_xfr_ack_in || inc_preamble_cntr) : 1'b0;
+ end
+ end
+
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ begin
+ phy_txd[7:0] <= 8'b00000000;
+ end
+ else
+ begin
+ if (cf_mac_mode)
+ phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
+ 8'b11010101 : ((tx_jam_in) ? 8'b11111111 :
+ ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte)));
+ else if (!cf_mac_mode && !cf2mi_rmii_en)
+ phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
+ 4'b1101 : ((tx_jam_in) ? 4'b1111 : tx_nibble_in)) ;
+ else if (!cf_mac_mode && cf2mi_rmii_en)
+ phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
+ 2'b11 : ((tx_jam_in) ? 2'b11 : tx_dibit_in)) ;
+ end
+ end
+ assign receive_detect_pulse = receive_detect && !d_receive_detect;
+
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ jam_count_reg <= 5'd0;
+ else if(cf_mac_mode)
+ jam_count_reg <= GMII_JAM_COUNT;
+ else if(cf2mi_rmii_en)
+ jam_count_reg <= RMII_JAM_COUNT;
+ else if(!cf2mi_rmii_en)
+ jam_count_reg <= MII_JAM_COUNT;
+ end
+
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ d_receive_detect <= 0;
+ else
+ d_receive_detect <= receive_detect;
+ end
+ // counter for the number transfers
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_xfr_cnt <= 2'd0;
+ else if(tx2mi_strt_preamble)
+ tx_xfr_cnt <= 2'd0;
+ else if(tx_xfr_ack_in)
+ tx_xfr_cnt <= tx_xfr_cnt + 1;
+ end
+
+ // phy_tx_en_dly
+ reg phy_tx_en_dly;
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ phy_tx_en_dly <= 1'd0;
+ else
+ phy_tx_en_dly <= phy_tx_en;
+ end
+
+ wire phy_tx_en_fall;
+ assign phy_tx_en_fall = phy_tx_en_dly && !phy_tx_en;
+
+ // counter for the number transfers ...
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_slot_xfr_cnt <= 2'd0;
+ else if(phy_tx_en_fall)
+ tx_slot_xfr_cnt <= 2'd0;
+ else if(inc_preamble_cntr || tx_xfr_ack_in)
+ tx_slot_xfr_cnt <= tx_slot_xfr_cnt + 1;
+ end
+
+ assign nibble_check_tx = tx_xfr_cnt[0];
+ assign dibit_check_tx= tx_xfr_cnt[0] && tx_xfr_cnt[1];
+ assign byte_boundary_tx = (cf_mac_mode) ? 1'b1:
+ ((!cf_mac_mode && !cf2mi_rmii_en) ? nibble_check_tx : dibit_check_tx);
+
+ assign tx_nibble_in = (tx_xfr_cnt[0]) ? tx2mi_tx_byte[3:0] : tx2mi_tx_byte[7:4];
+
+/* always @(tx_xfr_cnt or tx2mi_tx_byte or phy_tx_clk)
+ begin
+ if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[1:0];
+ else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[3:2];
+ else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[5:4];
+ else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[7:6];
+ else
+ tx_dibit_in <= tx2mi_tx_byte[1:0];
+ end
+*/
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_dibit_in <= 2'b0;
+ else if(tx2mi_strt_preamble)
+ tx_dibit_in <= 2'b0;
+ else
+ begin
+ if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[1:0];
+ else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[3:2];
+ else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[5:4];
+ else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
+ tx_dibit_in <= tx2mi_tx_byte[7:6];
+ end
+ end
+
+ // counter for the number of preamble to be sent
+ // before transmitting the sfd
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ tx_preamble_cnt_val <= 5'd0;
+ else if(rst_preamble_cntr)
+ tx_preamble_cnt_val <= 5'd0;
+ else if(inc_preamble_cntr)
+ tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
+ end
+
+ // Jam Counter
+ always @(posedge phy_tx_clk or negedge tx_reset_n)
+ begin
+ if(!tx_reset_n)
+ jam_count <= 5'd0;
+ else if(rst_jam_cntr)
+ jam_count <= 5'd0;
+ else if(inc_jam_cntr)
+ jam_count <= jam_count + 1;
+ end
+
+
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ rx_dfl_dn_reg <= 1'b0;
+ else if (df2rx_dfl_dn)
+ rx_dfl_dn_reg <= 1'b1;
+ else
+ begin
+ if (!phy_rx_dv && !phy_rx_er)
+ rx_dfl_dn_reg <= 1'b0;
+ end
+ end
+
+ assign mi2rx_rx_byte = mi2rx_rx_byte_in;
+ //assign rxd = (!cf_mac_mode && cf2mi_rmii_en)? mi2rx_rx_byte : mi2rx_rx_byte_in;
+
+ assign pre_condition_gmii = (!rxd[7] && rxd[6] && !rxd[5] && rxd[4]
+ && !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign pre_condition_mii = (!rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign pre_condition_rmii = (!rxd[1] && rxd[0] && rx_dv
+ && !rxd_del[1] && rxd_del[0] && rx_dv_del
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign sfd_condition_gmii = (rxd[7] && rxd[6] && !rxd[5] && rxd[4]
+ && !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign sfd_condition_mii = (rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+ assign sfd_condition_rmii = (rxd[1] && rxd[0] && rx_dv
+ && !rxd_del[1] && rxd_del[0] && rx_dv_del
+ && !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
+
+
+
+ assign pre_condition = (cf_mac_mode) ? pre_condition_gmii :
+ ((cf2mi_rmii_en) ? pre_condition_rmii : pre_condition_mii);
+
+ assign sfd_condition = (cf_mac_mode) ? sfd_condition_gmii :
+ ((cf2mi_rmii_en) ? sfd_condition_rmii : sfd_condition_mii);
+
+ // Following state machine is to detect strt preamble and
+ // receive preamble and sfd and then the data.
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mii_rx_cur_st <= mii_rx_idle_st;
+ end
+ else
+ begin
+ mii_rx_cur_st <= mii_rx_nxt_st;
+ end
+ end
+
+ always @(mii_rx_cur_st or rx_dv or rx_er or pre_condition or sfd_condition
+ or byte_boundary_rx or rxd or rx_xfr_cnt or cf2mi_rmii_en or cf_mac_mode)
+ begin
+ mii_rx_nxt_st = mii_rx_cur_st;
+ strt_rcv_in = 1'b0;
+ end_rcv_in = 1'b0;
+ rcv_valid_in = 1'b0;
+ rcv_err_in = 1'b0;
+ mi2rx_extend_in = 1'b0;
+ mi2rx_extend_err_in = 1'b0;
+ mi2rx_end_frame_in = 1'b0;
+
+ casex(mii_rx_cur_st) // synopsys parallel_case full_case
+
+ mii_rx_idle_st:
+ // This state is waiting for pre-amble to
+ // appear on the line in Receive mode
+ begin
+ if(pre_condition)
+ mii_rx_nxt_st = mii_rx_pre_st;
+ else
+ mii_rx_nxt_st = mii_rx_idle_st;
+ end
+
+ mii_rx_pre_st:
+ // This state checks the pre-amble and Waits for SFD on the line
+ begin
+ if(sfd_condition)
+ begin
+ strt_rcv_in = 1'b1;
+ if(cf_mac_mode)
+ mii_rx_nxt_st = mii_rx_byte_st;
+ else if(!cf_mac_mode && !cf2mi_rmii_en)
+ mii_rx_nxt_st = mii_rx_nibble_st;
+ else if(!cf_mac_mode && cf2mi_rmii_en)
+ mii_rx_nxt_st = mii_rx_dibit_st;
+ end
+ else if(pre_condition)
+ begin
+ mii_rx_nxt_st = mii_rx_pre_st;
+ end
+ else if(!rx_dv && rx_er && cf_mac_mode)
+ begin
+ mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
+ mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
+ mii_rx_nxt_st = mii_rx_pre_st;
+ end
+ else
+ begin
+ mi2rx_end_frame_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_idle_st;
+ end
+ end
+
+ mii_rx_byte_st:
+ // This state looks for data validity and latches di-bit2 and
+ // sends it to the receiver
+ begin
+ if(rx_dv)
+ begin
+ rcv_valid_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_byte_st;
+ end
+ else if (!rx_dv && rx_er && cf_mac_mode)
+ begin
+ mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
+ mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_pre_st;
+ end
+ else
+ begin
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_end_st;
+ end
+ end
+
+ mii_rx_end_st:
+ // This state looks for data validity and latches di-bit2 and
+ // sends it to the receiver
+ mii_rx_nxt_st = mii_rx_idle_st;
+
+ mii_rx_nibble_st:
+ begin
+ if(rx_dv)
+ begin
+ rcv_valid_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_nibble_st;
+ end
+ else
+ begin
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_end_st;
+ if(rx_xfr_cnt[0])
+ rcv_err_in = 1'b1;
+ end
+ end
+
+ mii_rx_dibit_st:
+ begin
+ if(rx_dv)
+ begin
+ rcv_valid_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_dibit_st;
+ end
+ else
+ begin
+ end_rcv_in = 1'b1;
+ mii_rx_nxt_st = mii_rx_end_st;
+ if(!(!rx_xfr_cnt[0] && !rx_xfr_cnt[1]))
+ rcv_err_in = 1'b1;
+ end
+ end
+
+ endcase
+ end // always @ (mii_rx_cur_st...
+
+ // counter for the number receives
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ rx_xfr_cnt <= 2'd0;
+ else if(mi2rx_end_rcv)
+ rx_xfr_cnt <= 2'd0;
+ else if(rcv_valid_in)
+ rx_xfr_cnt <= rx_xfr_cnt + 1;
+ end
+
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mi2rx_rx_byte_in <= 8'b0;
+ rxd <= 8'b0;
+ rxd_del <= 2'b0;
+ end
+ else
+ begin
+ rxd <= rxd_in;
+// rxd_del <= rxd_in[1:0];
+ rxd_del <= rxd[1:0];
+
+ if (cf_mac_mode)
+ mi2rx_rx_byte_in <= rxd;
+ else if (!cf_mac_mode && !cf2mi_rmii_en)
+ begin
+ if(!rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[3:0] <= rxd[3:0];
+ else
+ mi2rx_rx_byte_in[7:4] <= rxd[3:0];
+ end
+ else if(!cf_mac_mode && cf2mi_rmii_en)
+ begin
+ if(!rx_xfr_cnt[1] && !rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[1:0] <= rxd[1:0];
+ else if(!rx_xfr_cnt[1] && rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[3:2] <= rxd[1:0];
+ else if(rx_xfr_cnt[1] && !rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[5:4] <= rxd[1:0];
+ else if(rx_xfr_cnt[1] && rx_xfr_cnt[0])
+ mi2rx_rx_byte_in[7:6] <= rxd[1:0];
+ end
+ end
+ end
+
+ reg rx_sts_rx_er_reg;
+ always @(posedge phy_rx_clk or negedge rx_reset_n) begin
+ if(!rx_reset_n) begin
+ rx_sts_rx_er_reg <= 1'b0;
+ end
+ else if (mi2rx_strt_rcv) begin
+ rx_sts_rx_er_reg <= 1'b0;
+ end
+ else if(phy_rx_dv && phy_rx_er) begin
+ rx_sts_rx_er_reg <= 1'b1;
+ end
+ end
+
+ always @(posedge phy_rx_clk
+ or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mi2rx_rcv_vld <= 1'b0;
+ end
+ else if(cf_mac_mode)
+ mi2rx_rcv_vld <= rcv_valid_in;
+ else if(!cf_mac_mode && cf2mi_rmii_en && rx_xfr_cnt[0] && rx_xfr_cnt[1])
+ mi2rx_rcv_vld <= rcv_valid_in;
+ else if(!cf_mac_mode && !cf2mi_rmii_en && rx_xfr_cnt[0])
+ mi2rx_rcv_vld <= rcv_valid_in;
+ else
+ mi2rx_rcv_vld <= 1'b0;
+ end
+ // All the data, enable and ack signals out of RX block are
+ // registered
+ always @(posedge phy_rx_clk or negedge rx_reset_n)
+ begin
+ if(!rx_reset_n)
+ begin
+ mi2rx_strt_rcv <= 1'b0;
+ mi2rx_end_rcv <= 1'b0;
+ //mi2rx_rcv_vld <= 1'b0;
+ mi2rx_frame_err <= 1'b0;
+ mi2rx_extend <= 1'b0;
+ mi2rx_extend_err <= 1'b0;
+ mi2rx_end_frame <= 1'b0;
+ rx_dv <= 1'b0;
+ rx_er <= 1'b0;
+ rx_dv_del <= 1'b0;
+ end
+ else
+ begin
+ mi2rx_strt_rcv <= strt_rcv_in;
+ mi2rx_end_rcv <= end_rcv_in;
+ //mi2rx_rcv_vld <= rcv_valid_in;
+ mi2rx_frame_err <= rcv_err_in;
+ mi2rx_extend <= mi2rx_extend_in;
+ mi2rx_extend_err <= mi2rx_extend_err_in;
+ mi2rx_end_frame <= mi2rx_end_frame_in;
+ rx_dv <= rx_dv_in;
+ rx_er <= rx_er_in;
+ rx_dv_del <= rx_dv;
+ end
+ end
+
+
+ half_dup_dble_reg U_dble_reg0 (
+ //outputs
+ .sync_out_pulse(send_jam),
+ //inputs
+ .in_pulse(app_send_jam),
+ .dest_clk(phy_tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(receive_detect),
+ //inputs
+ .in_pulse(rx_dv_in),
+ .dest_clk(phy_tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+
+wire test;
+
+ half_dup_dble_reg U_dble_reg5 (
+ //outputs
+ .sync_out_pulse(tx_en),
+ //inputs
+ .in_pulse(lb_tx_en),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg6 (
+ //outputs
+ .sync_out_pulse(txd[0]),
+ //inputs
+ .in_pulse(phy_txd[0]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg7 (
+ //outputs
+ .sync_out_pulse(txd[1]),
+ //inputs
+ .in_pulse(phy_txd[1]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg8 (
+ //outputs
+ .sync_out_pulse(txd[2]),
+ //inputs
+ .in_pulse(phy_txd[2]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg9 (
+ //outputs
+ .sync_out_pulse(txd[3]),
+ //inputs
+ .in_pulse(phy_txd[3]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg10 (
+ //outputs
+ .sync_out_pulse(txd[4]),
+ //inputs
+ .in_pulse(phy_txd[4]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg11 (
+ //outputs
+ .sync_out_pulse(txd[5]),
+ //inputs
+ .in_pulse(phy_txd[5]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg12 (
+ //outputs
+ .sync_out_pulse(txd[6]),
+ //inputs
+ .in_pulse(phy_txd[6]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg13 (
+ //outputs
+ .sync_out_pulse(txd[7]),
+ //inputs
+ .in_pulse(phy_txd[7]),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg14 (
+ //outputs
+ .sync_out_pulse(tx_er),
+ //inputs
+ .in_pulse(lb_tx_er),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg15 (
+ //outputs
+ .sync_out_pulse(mi2rx_crs),
+ //inputs
+ .in_pulse(crs_in),
+ .dest_clk(phy_rx_clk),
+ .reset_n(rx_reset_n)
+ );
+
+endmodule
+
trunk/rtl/gmac/mac/g_mii_intf.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_tx_fsm.v
===================================================================
--- trunk/rtl/gmac/mac/g_tx_fsm.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_tx_fsm.v (revision 12)
@@ -0,0 +1,954 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+/***************************************************************
+ Description:
+
+ tx_fsm.v: Frames are queued in TX FIFO, when the TX FIFO has enough
+ data to sustain a 100Mb or 10 Mb transfer on the TX transmit is enabled.
+ Each dword has 3 extra bits, which indicate the end of the frame and
+ the number of valid bytes in the current dword.
+
+ ***********************************************************************/
+
+
+module g_tx_fsm (
+ //Outputs
+ //FIFO
+ tx_commit_read,
+ tx_dt_rd,
+
+ //FCS
+ tx2tc_fcs_active,
+ tx2tc_gen_crc,
+
+ //MII interface
+ tx2mi_strt_preamble,
+ tx2mi_byte_valid,
+ tx2mi_byte,
+ tx2mi_end_transmit,
+ phy_tx_en,
+ tx_ch_en,
+
+ //Application
+ tx_sts_vld,
+ tx_sts_byte_cntr,
+ tx_sts_fifo_underrun,
+
+ //Inputs
+ //FIFO
+ app_tx_rdy,
+ tx_end_frame,
+ app_tx_dt_in,
+ app_tx_fifo_empty,
+
+ //dfl and back
+ df2tx_dfl_dn,
+
+ //application
+ app_send_pause,
+
+ //FCS
+ tc2tx_fcs,
+
+ //Configuration
+ cf2tx_tstate_mode,
+ cf2tx_ch_en,
+ cf2tx_pad_enable,
+ cf2tx_append_fcs,
+ cf_mac_mode,
+ cf_mac_sa,
+ cf2tx_pause_quanta,
+ cf2tx_force_bad_fcs,
+
+ //RX pause
+ rx2tx_pause,
+ send_pause_active_out,
+ app_clk,
+ set_fifo_undrn,
+
+ //MII interface
+ mi2tx_byte_ack,
+ tx_clk,
+ tx_reset_n,
+ app_reset_n);
+
+
+parameter CORE_MIN_FRAME_SIZE = 16'h40; //64 bytes =>
+// (12(add)+2(len)+46(pay) + 4CRC)*2
+parameter CORE_MIN_FRAME_COL_SIZE = 16'h40; //63 bytes =>
+// tx_fsm lags MII by one byte
+parameter CORE_PAYLOAD_SIZE = 16'h3C ; //60 bytes =>
+// (12(add)+2(len)+46(pay))*2
+
+
+ input cf2tx_ch_en; //transmit enable application clock
+ input cf2tx_tstate_mode; //used for OFN's tstate enable on authentication interface
+ input app_tx_rdy; //tx fifo management, enough buffer to tx
+ input tx_end_frame; //Current DWORD marks end of frame
+ input [7:0] app_tx_dt_in; //double word data from the TX fifo mgmt
+ input app_tx_fifo_empty; //TX fifo is empty, if there were a data
+ //data request when app_tx_fifo_empty is asserted
+ //would result in FIFO underrun and error cond
+ input app_send_pause;
+ input [31:0] tc2tx_fcs;
+
+ //defferral inputs
+ input df2tx_dfl_dn; //IPG time between frames is satisfied
+
+ //configuration inputs
+ input cf2tx_pad_enable; //pad the TX frame if they are small
+ input cf2tx_append_fcs; //on every TX, compute and append FCS, when
+ //cf2tx_pad_enable and the current frame is small
+ //FCS is computed and appended to the frame
+ //irrespective of this signal
+ input cf_mac_mode; // 1 is GMII 0 10/100
+ input [47:0] cf_mac_sa;
+ input [15:0] cf2tx_pause_quanta;
+ input cf2tx_force_bad_fcs;
+ //RX pause frame received
+ input rx2tx_pause; //in full duplex mode, the RX has received
+ //a pause frame, hence the TX is requested to
+ //hold transfers after the transmission of the
+ //current transfer. level signal
+ //from MII or RMII
+ input mi2tx_byte_ack; //MII interface accepted last byte
+ input tx_clk;
+ input tx_reset_n;
+ input app_reset_n;
+
+ //tx fifo management outputs
+ output tx_commit_read; //64 bytes have been transmitted successfully
+ //hence advance the rd pointer
+ output tx_dt_rd; //get net dword from the TX FIFO
+ //FCS interface
+ output tx2tc_fcs_active; //FCS being shipped to RMII or MII interface
+ output tx2tc_gen_crc; //update the CRC with new byte
+
+
+ //MII or RMII interface signals
+ output tx2mi_strt_preamble; //ask RMII or MII interface to send preamable
+ output tx2mi_byte_valid; //current byte to RMII or MII is valid
+ output [7:0] tx2mi_byte; //data to RMII and MII interface
+ output tx2mi_end_transmit; //frame transfer done
+ output tx_sts_vld; //tx status is valid
+ output [15:0] tx_sts_byte_cntr;
+ output tx_sts_fifo_underrun;
+ output tx_ch_en; // MANDAR
+
+ input phy_tx_en; // mfilardo ofn auth fix.
+
+ input app_clk;
+ output send_pause_active_out;
+ output set_fifo_undrn; // Description: At GMII Interface ,
+ // abug after a transmit fifo underun was found.
+ // The packet after a packet that
+ // underran has 1 too few bytes .
+
+
+ parameter mn_idle_st = 3'd0;
+ parameter mn_snd_full_dup_frm_st = 3'd1;
+
+ parameter fcs_idle_st = 0;
+ parameter fcs_snd_st = 1;
+
+ parameter dt_idle_st = 12'b000000000000;
+ parameter dt_xfr_st = 12'b000000000001;
+ parameter dt_pad_st = 12'b000000000010;
+ parameter dt_fcs_st = 12'b000000000100;
+ parameter dt_pause_xfr_st = 12'b000010000000;
+ parameter dt_pause_pad_st = 12'b000100000000;
+ parameter dt_pause_fcs_st = 12'b001000000000;
+
+
+ wire tx_commit_read;
+ wire tx_dt_rd; //request TX FIFO for more data
+ wire tx2tc_fcs_active; //FCS is currently transmitted
+ wire tx2tc_gen_crc;
+ wire tx2mi_strt_preamble;
+ wire tx2mi_end_transmit;
+ wire [7:0] tx2mi_byte;
+ wire tx2mi_byte_valid;
+ wire cfg_force_bad_fcs_pulse;
+ reg [15:0] tx_sts_byte_cntr;
+ reg tx_sts_fifo_underrun;
+
+
+ reg [11:0] curr_dt_st, nxt_dt_st;
+ reg tx_fcs_dn, tx_fcs_dn_reg; //FCS fsm on completion of appending FCS
+ reg curr_fcs_st, nxt_fcs_st; //FSM for FCS
+ reg fcs_active; //FCS is currently transmitted
+
+ reg init_fcs_select; //initiliaze FCS mux select
+ reg clr_bad_fcs; //tx_reset the bad FCS requirement
+ reg clr_pad_byte; //clear the padded condition
+ reg [2:0] fcs_mux_select; //mux select for FCS
+ reg send_bad_fcs; //registered send bad FCS requirement
+ reg set_bad_fcs; //set the above register
+ reg [15:0] tx_byte_cntr; //count the number of bytes xfr'ed
+ reg tx_fsm_rd; //request TX FIFO for more data
+ reg tx_byte_valid; //current byte to MII is valdi
+ reg strt_fcs, strt_fcs_reg; //data is done, send FCS
+ reg frm_padded; //current frame is padded
+
+
+ reg set_pad_byte; //send zero filled bytes
+ reg e_tx_sts_vld; //current packet is transferred
+ reg tx_sts_vld; //02999
+ reg strt_preamble;
+ reg [7:0] tx_byte;
+ reg [7:0] tx_fsm_dt_reg;
+ reg tx_end_frame_reg;
+ reg tx_lst_xfr_dt, tx_lst_xfr_fcs;
+ reg commit_read;
+ reg set_max_retry_reached;
+ reg gen_tx_crc;
+ reg set_fifo_undrn, clr_fifo_undrn, fifo_undrn;
+ reg commit_read_sent;
+ reg clr_first_dfl, set_first_dfl;
+
+ wire tx_lst_xfr;
+ wire tx_pause_sync;
+ reg inc_pause_index, clr_pause_index;
+ reg send_pause_active;
+ wire send_pause_sync;
+
+ reg [4:0] pause_index;
+
+ reg tx_lst_xfr_fcs_reg;
+ wire [15:0] tx_byte_cntr_int;
+
+ reg cur_idle_st_del;
+
+ reg app_tx_rdy_dly;
+
+ reg send_pause_active_s1;
+ reg send_pause_active_out;
+
+ always @(posedge app_clk or negedge app_reset_n) begin
+ if (!app_reset_n) begin
+ send_pause_active_s1 <= 1'b0;
+ send_pause_active_out <= 1'b0;
+ end
+ else begin
+ send_pause_active_s1 <= send_pause_active;
+ send_pause_active_out <= send_pause_active_s1;
+ end
+ end
+
+ always @(posedge tx_clk or negedge tx_reset_n) begin
+ if (!tx_reset_n) begin
+ app_tx_rdy_dly <= 1'b0;
+ end
+ else begin
+ app_tx_rdy_dly <= app_tx_rdy;
+ end
+ end
+
+
+
+ assign tx_commit_read = commit_read;
+ assign tx_dt_rd = tx_fsm_rd;
+ assign tx2tc_fcs_active = fcs_active;
+ assign tx2tc_gen_crc = gen_tx_crc;
+ assign tx2mi_strt_preamble = strt_preamble;
+ assign tx2mi_byte_valid = tx_byte_valid;
+ assign tx2mi_byte = tx_byte;
+ assign tx2mi_end_transmit = tx_lst_xfr;
+
+ assign tx_lst_xfr = tx_lst_xfr_dt || tx_lst_xfr_fcs;
+
+//To take care of 1 less byte count when fcs is not appended.
+ assign tx_byte_cntr_int = ((curr_dt_st == dt_fcs_st) ||
+ (curr_dt_st == dt_pause_fcs_st)) ? tx_byte_cntr : tx_byte_cntr + 16'h1;
+
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ tx_sts_vld <= 1'b0;
+ tx_sts_byte_cntr <= 16'b0;
+ tx_sts_fifo_underrun <= 1'b0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ tx_sts_vld <= e_tx_sts_vld;
+ if (e_tx_sts_vld)
+ begin
+ tx_sts_byte_cntr <= tx_byte_cntr_int;
+ tx_sts_fifo_underrun <= fifo_undrn || set_fifo_undrn;
+ end
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+
+
+
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(tx_pause_sync),
+ //inputs
+ .in_pulse(rx2tx_pause),
+ .dest_clk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg2 (
+ //outputs
+ .sync_out_pulse(tx_ch_en),
+ //inputs
+ .in_pulse(cf2tx_ch_en),
+ .dest_clk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+
+ half_dup_dble_reg U_dble_reg3 (
+ //outputs
+ .sync_out_pulse(send_pause_sync),
+ //inputs
+ .in_pulse(app_send_pause),
+ .dest_clk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+ half_dup_dble_reg U_dble_reg4 (
+ //outputs
+ .sync_out_pulse(cfg_force_bad_fcs_pulse),
+ //inputs
+ .in_pulse(cf2tx_force_bad_fcs),
+ .dest_clk(tx_clk),
+ .reset_n(tx_reset_n)
+ );
+
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ cur_idle_st_del <= 1'b1;
+ else
+ cur_idle_st_del <= (curr_dt_st==dt_idle_st);
+ end
+
+ //Data pump, this state machine gets triggered by TX FIFO
+ //This FSM control's the MUX loging to channel the 32 bit
+ //data to byte wide and also keeps track of the end of the
+ //frame and the valid bytes for the last double word. tx_sts_vld
+ //is generated by this fsm.
+ //Collission handling, retry operations are done in this FSM.
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ curr_dt_st <= dt_idle_st;
+ else if (tx_ch_en)
+ curr_dt_st <= nxt_dt_st;
+ else
+ curr_dt_st <= dt_idle_st;
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //combinatorial process
+ //always @(curr_dt_st or mi2tx_byte_ack or app_tx_fifo_empty
+ always @(curr_dt_st or mi2tx_byte_ack or app_tx_fifo_empty
+ or tx_end_frame_reg or commit_read_sent
+ or tx_byte_cntr or tx_fcs_dn_reg or cf2tx_pad_enable or tx_ch_en
+ or df2tx_dfl_dn or tx_pause_sync or app_tx_rdy
+ or strt_fcs_reg
+ or tx_end_frame or tx_clk
+ or cf2tx_append_fcs
+ or app_tx_rdy_dly or send_pause_sync or pause_index or cur_idle_st_del)
+ begin
+ nxt_dt_st = curr_dt_st;
+ tx_fsm_rd = 0;
+ tx_byte_valid = 0;
+ set_bad_fcs = 0;
+ strt_fcs = 0;
+ set_pad_byte = 0;
+ set_max_retry_reached = 0;
+ e_tx_sts_vld = 0;
+ commit_read = 0;
+ strt_preamble = 0;
+ tx_lst_xfr_dt = 0;
+ clr_pad_byte = 0;
+ set_fifo_undrn = 0;
+ clr_fifo_undrn = 0;
+ clr_first_dfl = 0;
+ set_first_dfl = 0;
+ send_pause_active = 0;
+ inc_pause_index = 0;
+ clr_pause_index = 0;
+ case (curr_dt_st)
+ dt_idle_st :
+ begin
+ //clear early state
+ clr_pad_byte = 1;
+ clr_fifo_undrn = 1;
+ clr_first_dfl = 1'b1;
+ //wait until there is enough data in the TX FIFO
+ //and tx_enabled and not waiting for pause period
+ //in the case of full duplex
+ if (tx_ch_en) //config, channel enable
+ begin
+ if (send_pause_sync && df2tx_dfl_dn)
+ begin
+ // this ifdef is a bug fix. A pending pause can cause ifg to be 1 cycle short.
+ nxt_dt_st = dt_pause_xfr_st;
+ strt_preamble = 1;
+ end
+ else if (app_tx_rdy && df2tx_dfl_dn && !tx_pause_sync)
+ begin
+ tx_fsm_rd = 1;
+ nxt_dt_st = dt_xfr_st;
+ strt_preamble = 1;
+ end
+ else
+ nxt_dt_st = dt_idle_st;
+ end // if (tx_ch_en)
+ else
+ nxt_dt_st = dt_idle_st;
+ end // case: dt_idle_st
+
+ dt_xfr_st :
+ begin
+ tx_byte_valid = 1;
+ //compare the mux_select to max bytes to be transmitted
+ //on the last dword of the frame
+ if (mi2tx_byte_ack && (tx_end_frame_reg))
+ begin
+ // If it is end of frame detection and the count
+ // indicates that there is no need for padding then if
+ // pad is enabled dont check for cf2tx_append_fcs and Append
+ // the CRC with the data packet
+ if ((tx_byte_cntr >= ( CORE_PAYLOAD_SIZE - 1)) && cf2tx_append_fcs)
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (cf2tx_append_fcs)
+ else
+ //ending the current transfer, check the frame size
+ //padding or FCS needs to be performed
+ if (tx_byte_cntr < ( CORE_PAYLOAD_SIZE - 1))
+ begin
+ //less than min frame size, check to see if
+ //padding can be done
+ if(cf2tx_pad_enable)
+ begin
+ nxt_dt_st = dt_pad_st;
+ end // if (cf2tx_pad_enable)
+ else
+ begin
+ //if no padding, check to see if FCS needs
+ //to be computed
+ if (cf2tx_append_fcs)
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (cf2tx_append_fcs)
+ else
+ //if no FCS, complete the transfer
+ begin
+ e_tx_sts_vld = 1;
+ commit_read = 1;
+ nxt_dt_st = dt_idle_st;
+ end // else: !if(cf2tx_append_fcs)
+ end // else: !if(cf2tx_pad_enable)
+ end // if (tx_byte_cntr < ( CORE_MIN_FRAME_SIZE - 1))
+ else
+ //minimmum frame sent, check to see if FCS needs to
+ //be computed else transfer is done
+ begin
+ if (cf2tx_append_fcs)
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (cf2tx_append_fcs)
+ else
+ begin
+ commit_read = !commit_read_sent;
+ e_tx_sts_vld = 1;
+ nxt_dt_st = dt_idle_st;
+ end // else: !if(cf2tx_append_fcs)
+ end // else: !if(tx_byte_cntr < ( CORE_MIN_FRAME_SIZE - 1))
+ end
+ else if (mi2tx_byte_ack)
+ begin
+ //time to fetch the new dword
+ //check to see if the fifo is empty
+ //if it is then send the crc with last bit
+ //inverted as bad CRC so that the destination
+ //can throw away the frame
+ if (app_tx_fifo_empty)
+ begin
+ //TX has encountered error, finish the current byte
+ //append wrong fcs
+ set_bad_fcs = 1;
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ set_fifo_undrn = 1;
+ end // if (mi2tx_byte_ack && ((mux_select == 1) ||...
+ tx_fsm_rd = 1; //just to set error, or
+ //get next word
+ end // if (mi2tx_byte_ack && mux_selectl == 1)
+ //provide end of transfer to MII/RMII interface
+ //commit_read pointer
+ if (mi2tx_byte_ack )
+ commit_read = !commit_read_sent;
+
+ if (tx_end_frame_reg)
+ begin
+ if (tx_byte_cntr < (CORE_PAYLOAD_SIZE - 1))
+ begin
+ if(!cf2tx_pad_enable)
+ begin
+ if (!cf2tx_append_fcs)
+ tx_lst_xfr_dt = 1;
+ end // if (!cf2tx_pad_enable)
+ end // if (tx_byte_cntr < (CORE_MIN_FRAME_SIZE - 1))
+ else
+ begin
+ if (!cf2tx_append_fcs)
+ tx_lst_xfr_dt = 1;
+ end
+ end // if ((mux_select == mux_max_select) && (tx_end_frame_reg))
+ end // case: dt_xfr_st
+
+ dt_pad_st :
+ begin
+ //wait until the padded data is enough to satisfy
+ //the minimum packet size and then return to idle
+ tx_byte_valid = 1;
+ set_pad_byte = 1;
+ //check to see if the 48 bytes are sent and then move to the
+ //crc state
+ if (mi2tx_byte_ack && (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_fcs_st;
+ end // if (mi2tx_byte_ack && (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
+ end // case: dt_pad_st
+
+ dt_fcs_st :
+ begin
+ if (tx_fcs_dn_reg && !strt_fcs_reg)
+ //last byte of crc is transmitted to MII and
+ //a new set of CRC is not transmitted to MII (this
+ //could be because of JAM sequence)
+ begin
+ //In the case of MII, while in this state the
+ //MII interface will be transferring the last
+ //byte to the PHY. If a collision is seen in this
+ //state then do the appropriate
+ commit_read = !commit_read_sent;
+ nxt_dt_st = dt_idle_st;
+ e_tx_sts_vld = 1;
+ end // if (tx_fcs_dn)
+ else
+ begin
+ nxt_dt_st = dt_fcs_st;
+ end // else: !if(tx_fcs_dn)
+ end // case: dt_fcs_st
+
+ dt_pause_xfr_st :
+ begin
+ tx_byte_valid = 1;
+ send_pause_active = 1;
+ // Send the Pause Frame out
+ if (mi2tx_byte_ack)
+ begin
+ if (pause_index == 5'd18)
+ begin
+ clr_pause_index = 1;
+ nxt_dt_st = dt_pause_pad_st;
+ end
+ else
+ begin
+ inc_pause_index = 1;
+ nxt_dt_st = dt_pause_xfr_st;
+ end
+ end
+ else
+ begin
+ nxt_dt_st = dt_pause_xfr_st;
+ end
+ end // case: dt_pause_xfr_st
+
+ dt_pause_pad_st :
+ begin
+ // Append Padding to the Packet
+ tx_byte_valid = 1;
+ set_pad_byte = 1;
+ if (mi2tx_byte_ack && (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
+ begin
+ strt_fcs = 1;
+ nxt_dt_st = dt_pause_fcs_st;
+ end // if (mi2tx_byte_ack &&
+ // (tx_byte_cntr == CORE_PAYLOAD_SIZE - 1))
+ else
+ nxt_dt_st = dt_pause_pad_st;
+ end // case: dt_pause_pad_st
+
+ dt_pause_fcs_st :
+ begin
+ // Wait for the FCS to be sent
+ if (tx_fcs_dn_reg)
+ begin
+ e_tx_sts_vld = 1;
+ nxt_dt_st = dt_idle_st;
+ end
+ else
+ begin
+ nxt_dt_st = dt_pause_fcs_st;
+ end
+ end // case: dt_pause_fcs_st
+
+
+ default :
+ begin
+ nxt_dt_st = dt_idle_st;
+ end
+ endcase // case (curr_dt_st)
+ end // always @ (curr_dt_st or )
+
+ //counter to track the number of bytes transferred excluding
+ //the preamble and SOF
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ tx_byte_cntr <= 16'd0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ if (mi2tx_byte_ack)
+ begin
+ tx_byte_cntr <= tx_byte_cntr + 1;
+ end // if (mi2tx_byte_ack)
+ else if (strt_preamble)
+ begin
+ tx_byte_cntr <= 16'd0;
+ end // else: !if(mi2tx_byte_ack)
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+// So, introduce strt_preamble_pls to compensate for delay.
+ reg s_p_d1, s_p_d2, s_p_d3;
+ wire strt_preamble_pls;
+ always @(posedge tx_clk or negedge tx_reset_n) begin
+ if (!tx_reset_n) begin
+ s_p_d1 <= 1'b0;
+ s_p_d2 <= 1'b0;
+ s_p_d3 <= 1'b0;
+ end // if (!tx_reset_n)
+ else begin
+ s_p_d1 <= strt_preamble;
+ s_p_d2 <= s_p_d1;
+ s_p_d3 <= s_p_d2;
+ end
+ end // always
+
+ wire strt_preamble_prog;
+ assign strt_preamble_pls = strt_preamble || s_p_d1 || s_p_d2 || s_p_d3;
+ assign strt_preamble_prog = strt_preamble;
+//ECO fix, part1 end
+
+ //fsm to transmit the FCS
+ //synchronous process
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ curr_fcs_st <= fcs_idle_st;
+ else
+ curr_fcs_st <= nxt_fcs_st;
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //set bad fcs requirement
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ send_bad_fcs <= 0;
+ else
+ begin
+ //if (set_bad_fcs)
+ if (set_bad_fcs | cfg_force_bad_fcs_pulse)
+ send_bad_fcs <= 1;
+ else if (clr_bad_fcs)
+ send_bad_fcs <= 0;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+ //set the error condition flags
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ fifo_undrn <= 0;
+ end // if (!tx_reset_n)
+ else
+ begin
+
+ if (set_fifo_undrn)
+ fifo_undrn <= 1;
+ else if (clr_fifo_undrn)
+ fifo_undrn <= 0;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //sync block for tx_fcs_dn
+
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ strt_fcs_reg <= 0;
+ tx_fcs_dn_reg <= 0;
+ tx_lst_xfr_fcs_reg <= 0; //naveen 052799
+ end // if (!tx_reset_n)
+ else
+ begin
+ tx_fcs_dn_reg <= tx_fcs_dn;
+ strt_fcs_reg <= strt_fcs;
+ tx_lst_xfr_fcs_reg <= tx_lst_xfr_fcs; //naveen 052799
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //combinatorial process
+ //bad fcs or good fcs could have been requested, in either case
+ //the 8 bytes have to be shifted out, in the case of bad fcs
+ //the last bit of the last byte will up toggled.
+ always @(curr_fcs_st or mi2tx_byte_ack or fcs_mux_select or
+ strt_fcs or strt_fcs_reg)
+ begin
+ nxt_fcs_st = curr_fcs_st;
+ fcs_active = 0;
+ init_fcs_select = 0;
+ tx_fcs_dn = 0;
+ clr_bad_fcs = 0;
+ tx_lst_xfr_fcs = 0;
+ case (curr_fcs_st)
+ fcs_idle_st :
+ if (strt_fcs || strt_fcs_reg)
+ begin
+ nxt_fcs_st = fcs_snd_st;
+ init_fcs_select = 1;
+ end // if (strt_fcs)
+ fcs_snd_st :
+ begin
+ fcs_active = 1;
+ if (fcs_mux_select == 3'd3)
+ tx_lst_xfr_fcs = 1;
+ if (mi2tx_byte_ack && fcs_mux_select == 3'd3)
+ begin
+ tx_fcs_dn = 1;
+ clr_bad_fcs = 1;
+ nxt_fcs_st = fcs_idle_st;
+ end // if (mi2tx_byte_ack)
+ end // case: fcs_snd_st
+ default :
+ begin
+ nxt_fcs_st = fcs_idle_st;
+ end
+ endcase // case (curr_fcs_st)
+ end // always @ (curr_fcs_st or)
+
+ //fcs mux select counter
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ fcs_mux_select <= 3'd0;
+ else
+ begin
+ if (strt_fcs)
+ fcs_mux_select <= 3'd0;
+ else if (mi2tx_byte_ack)
+ fcs_mux_select <= fcs_mux_select + 1 ;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //remmember if frame is padded
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ frm_padded <= 0;
+ else
+ begin
+ if (clr_pad_byte)
+ frm_padded <= 0;
+ else if (set_pad_byte)
+ frm_padded <= 1;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+
+ //register the TX fifo data on tx_fsm_rd and demux
+ //it for byte access
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ begin
+ tx_fsm_dt_reg <= 8'd0;
+ tx_end_frame_reg <= 0;
+ end // if (!tx_reset_n)
+ else
+ begin
+ if (tx_fsm_rd)
+ begin
+ tx_fsm_dt_reg <= app_tx_dt_in;
+ tx_end_frame_reg <= tx_end_frame;
+ end // if (tx_fsm_rd)
+ if (e_tx_sts_vld)
+ tx_end_frame_reg <= 0;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //Pause index counters
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ pause_index <= 5'd0;
+ else
+ begin
+ if (clr_pause_index)
+ pause_index <= 5'd0;
+ else if (inc_pause_index)
+ pause_index <= pause_index + 1;
+ end // else: !if(!tx_reset_n)
+ end // always @ (posedge tx_clk or negedge tx_reset_n)
+
+ //Data mux, is controlled either by the mux select from the
+ //primary data flow or from the FCS mux select. When PAD
+ //data option is used bytes of all zeros are transmitted
+ always @(fcs_active or app_tx_dt_in or tc2tx_fcs
+ or send_bad_fcs or fcs_mux_select or
+ set_pad_byte or tx_fsm_dt_reg or send_pause_active or pause_index
+ or cf_mac_sa or cf2tx_pause_quanta)
+ begin
+ if (send_pause_active)
+ begin
+ case (pause_index)
+ 5'd0 :
+ tx_byte = 8'h01;
+ 5'd1 :
+ tx_byte = 8'h80;
+ 5'd2 :
+ tx_byte = 8'hc2;
+ 5'd3 :
+ tx_byte = 8'h00;
+ 5'd4 :
+ tx_byte = 8'h00;
+ 5'd5 :
+ tx_byte = 8'h01;
+ 5'd6 :
+ tx_byte = cf_mac_sa[7:0];
+ 5'd7 :
+ tx_byte = cf_mac_sa[15:8];
+ 5'd8 :
+ tx_byte = cf_mac_sa[23:16];
+ 5'd9 :
+ tx_byte = cf_mac_sa[31:24];
+ 5'd10 :
+ tx_byte = cf_mac_sa[39:32];
+ 5'd11 :
+ tx_byte = cf_mac_sa[47:40];
+ 5'd12 :
+ tx_byte = 8'h88;
+ 5'd13 :
+ tx_byte = 8'h08;
+ 5'd14 :
+ tx_byte = 8'h00;
+ 5'd15 :
+ tx_byte = 8'h01;
+ 5'd16 :
+ tx_byte = cf2tx_pause_quanta[15:8];
+ 5'd17 :
+ tx_byte = cf2tx_pause_quanta[7:0];
+ default :
+ tx_byte = 8'h00;
+ endcase // case (mux_select)
+ end
+ else if (!fcs_active && !set_pad_byte)
+ begin
+ //primary data flow
+ tx_byte = tx_fsm_dt_reg[7:0];
+// $stop;
+ end // if (!fcs_active)
+ else if (fcs_active)
+ begin
+ tx_byte = tc2tx_fcs[7:0];
+ case (fcs_mux_select)
+ 3'd0 :
+ tx_byte = tc2tx_fcs[7:0];
+ 3'd1 :
+ tx_byte = tc2tx_fcs[15:8];
+ 3'd2 :
+ tx_byte = tc2tx_fcs[23:16];
+ default :
+ begin
+ if (send_bad_fcs)
+ tx_byte = {!tc2tx_fcs[31], tc2tx_fcs[30:24]};
+ else
+ tx_byte = tc2tx_fcs[31:24];
+ end // case: 3'd7
+ endcase // case (mux_select)
+ end // else: !if(!fcs_active)
+ else if (set_pad_byte)
+ tx_byte = 8'd0;
+ else
+ tx_byte = 8'd0;
+ end // always @ (fcs_active or app_tx_dt_in or tc2tx_fcs or mux_select...
+
+ //generate fcs computation enable. One cycle after the
+ //strt_preamble the tx_byte is stable and a cycle after the
+ //mi2tx_byte_ack also a new byte is stable
+ always @(posedge tx_clk or negedge tx_reset_n)
+ begin
+ if (!tx_reset_n)
+ gen_tx_crc <= 1'b0;
+ else
+ begin
+ if (fcs_active || strt_fcs)
+ gen_tx_crc <= 1'b0;
+ else
+ gen_tx_crc <= strt_preamble || mi2tx_byte_ack;
+ end // else: !if(!tx_reset_n)
+ end // always (posedge tx_clk or negedge tx_reset_n)
+
+
+endmodule // tx_fsm
trunk/rtl/gmac/mac/g_tx_fsm.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_md_intf.v
===================================================================
--- trunk/rtl/gmac/mac/g_md_intf.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_md_intf.v (revision 12)
@@ -0,0 +1,551 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+/***************************************************************
+ Description:
+
+ md_intf.v: This verilog file is for the mdio interface of the mac
+ This block enables the station to communicate with the
+ PHYs. This interface is kicked of by a go command from
+ the application. This intiates the read and write operation
+ to the PHY. Upon completion of the operation it returns
+ a indication called command done with the status of such
+ operation.
+
+***************************************************************/
+/************** MODULE DECLARATION ****************************/
+
+module g_md_intf(
+ scan_mode,
+ reset_n,
+ mdio_clk,
+ mdio_in,
+ mdio_outen_reg,
+ mdio_out_reg,
+ mdio_regad,
+ mdio_phyad,
+ mdio_op,
+ go_mdio,
+ mdio_datain,
+ mdio_dataout,
+ mdio_cmd_done,
+ mdio_stat,
+ mdc
+ );
+
+
+parameter FIVE = 5'h5;
+parameter SIXTEEN = 5'd16;
+parameter THIRTY_TWO = 5'd31;
+parameter WRITE = 1;
+
+/******* INPUT & OUTPUT DECLARATIONS *************************/
+
+ input scan_mode ; // scan_mode = 1
+ input reset_n; // reset from mac application interface
+ input mdio_in; // Input signal used to read data from PHY
+ input mdio_clk; // Input signal used to read data from PHY
+ input[4:0] mdio_regad; // register address for the current PHY operation
+ input[4:0] mdio_phyad; // Phy address to which the current operation is intended
+ input mdio_op; // 1 = READ 0 = WRITE
+ input go_mdio; // This is go command from the application for a MDIO
+ // transfer
+ input[15:0] mdio_datain; // 16 bit Write value from application to MDIO block
+ output[15:0] mdio_dataout; // 16 bit Read value for a MDIO transfer
+ output mdio_cmd_done; // This is from MDIO to indicate mdio command completion
+ output mdio_stat; // Status of completion. 0 = No error 1= Error
+ output mdio_out_reg; // Output signal used to write data to PHY
+ output mdio_outen_reg; // Enable signal 1= Output mode on 0 = Input mode
+ output mdc; // This is the MDIO clock
+
+/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
+ wire mdc;
+ wire [15:0] mdio_dataout;
+ wire go_mdio_sync;
+ reg mdio_stat;
+ reg mdio_cmd_done;
+ reg mdio_out_en;
+ reg mdio_out;
+
+ half_dup_dble_reg U_dble_reg1 (
+ //outputs
+ .sync_out_pulse(go_mdio_sync),
+ //inputs
+ .in_pulse(go_mdio),
+ .dest_clk(mdio_clk),
+ .reset_n(reset_n)
+ );
+
+
+
+
+/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
+ reg[3:0] mdio_cur_st;
+ reg[3:0] mdio_nxt_st;
+ parameter mdio_idle_st= 4'd0,
+ mdio_idle1_st = 4'd1,
+ mdio_sfd1_st= 4'd2,
+ mdio_sfd2_st= 4'd3,
+ mdio_op1_st= 4'd4,
+ mdio_op2_st= 4'd5,
+ mdio_phyaddr_st= 4'd6,
+ mdio_regaddr_st= 4'd7,
+ mdio_turnar_st= 4'd8,
+ mdio_wrturn_st= 4'd9,
+ mdio_rdturn_st= 4'd10,
+ mdio_read_st= 4'd11,
+ mdio_write_st= 4'd12,
+ mdio_complete_st= 4'd13,
+ mdio_preamble_st= 4'd14;
+
+ reg operation;
+ reg phyaddr_mux_sel;
+ reg regaddr_mux_sel;
+ reg write_data_mux_sel;
+ reg read_data_mux_sel;
+ wire[4:0] inc_temp_count;
+ reg[4:0] temp_count;
+ reg reset_temp_count;
+ reg inc_count;
+ reg[4:0] phy_addr;
+ reg[4:0] reg_addr;
+ reg[15:0] transmit_data;
+ reg[15:0] receive_data;
+ reg set_mdio_stat,clr_mdio_stat;
+
+/***************** WIRE ASSIGNMENTS *************************/
+ assign mdc = mdio_clk;
+ assign mdio_dataout = receive_data;
+
+/******** SEQUENTIAL LOGIC **********************************/
+
+ always @(mdio_cur_st or go_mdio_sync or inc_temp_count or
+ transmit_data or operation or phy_addr or reg_addr or temp_count or mdio_in)
+ begin
+ mdio_nxt_st = mdio_cur_st;
+ inc_count = 1'b0;
+ //mdio_cmd_done = 1'b0;
+ mdio_out = 1'b0;
+ mdio_out_en = 1'b0;
+ set_mdio_stat = 1'b0;
+ clr_mdio_stat = 1'b0;
+ phyaddr_mux_sel = 1'b0;
+ read_data_mux_sel = 1'b0;
+ regaddr_mux_sel = 1'b0;
+ reset_temp_count = 1'b0;
+ write_data_mux_sel = 1'b0;
+
+ casex(mdio_cur_st ) // synopsys parallel_case full_case
+
+ mdio_idle_st:
+ // This state waits for signal go_mdio
+ // upon this command from config block
+ // mdio state machine starts to send
+ // SOF delimter
+ begin
+ if(~go_mdio_sync)
+ mdio_nxt_st = mdio_idle1_st; //mdio_sfd1_st;
+ else
+ mdio_nxt_st = mdio_idle_st;
+ end
+
+ mdio_idle1_st:
+ begin
+ if (go_mdio_sync)
+ mdio_nxt_st = mdio_preamble_st;
+ else
+ mdio_nxt_st = mdio_idle1_st;
+ end
+
+ mdio_preamble_st:
+ begin
+ clr_mdio_stat = 1'b1;
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b1;
+ if (temp_count == THIRTY_TWO)
+ begin
+ mdio_nxt_st = mdio_sfd1_st;
+ reset_temp_count = 1'b1;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_nxt_st = mdio_preamble_st;
+ end
+ end
+
+ mdio_sfd1_st:
+ // This state shifts the first bit
+ // of Start of Frame De-limiter
+ begin
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b0;
+ mdio_nxt_st = mdio_sfd2_st;
+ end
+
+ mdio_sfd2_st:
+ // This state shifts the second bit
+ // of Start of Frame De-limiter
+ begin
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b1;
+ mdio_nxt_st = mdio_op1_st;
+ end
+
+ mdio_op1_st:
+ // This state shifts the first bit
+ // of type of operation read/write
+ begin
+ mdio_out_en = 1'b1;
+ if(operation)
+ mdio_out = 1'b0;
+ else
+ mdio_out = 1'b1;
+ //mdio_out = 1'b0; naveen 120199
+ mdio_nxt_st = mdio_op2_st;
+ end
+
+ mdio_op2_st:
+ // This state shifts the second bit
+ // of type of operation read/write and
+ // determines the appropriate next state
+ // needed for such operation
+ begin
+ mdio_out_en = 1'b1;
+ mdio_nxt_st = mdio_phyaddr_st;
+ if(operation)
+ mdio_out = 1'b1;
+ else
+ mdio_out = 1'b0;
+ end
+
+ mdio_phyaddr_st:
+ // This state shifts the phy-address on the mdio
+ begin
+ mdio_out_en = 1'b1;
+ phyaddr_mux_sel = 1'b1;
+ if(inc_temp_count == FIVE)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_out = phy_addr[4];
+ mdio_nxt_st = mdio_regaddr_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_out = phy_addr[4];
+ mdio_nxt_st = mdio_phyaddr_st;
+ end
+ end
+
+ mdio_regaddr_st:
+ // This state shifts the register in the phy to which
+ // this operation is intended
+ begin
+ mdio_out_en = 1'b1;
+ regaddr_mux_sel = 1'b1;
+ if(inc_temp_count == FIVE)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_out = reg_addr[4];
+ mdio_nxt_st = mdio_turnar_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_out = reg_addr[4];
+ mdio_nxt_st = mdio_regaddr_st;
+ end
+ end
+
+ mdio_turnar_st:
+ // This state determines whether the output enable
+ // needs to on or of based on the type of command
+ begin
+ //mdio_out_en = 1'b1;naveen 011299
+ mdio_out = 1'b1;
+ if(operation)
+ begin
+ mdio_out_en = 1'b1;
+ mdio_nxt_st = mdio_wrturn_st;
+ end
+ else
+ begin
+ mdio_out_en = 1'b0;
+ mdio_nxt_st = mdio_rdturn_st;
+ end
+ end
+
+ mdio_wrturn_st:
+ // This state is used for write turn around
+ begin
+ mdio_out_en = 1'b1;
+ mdio_out = 1'b0;
+ mdio_nxt_st = mdio_write_st;
+ end
+
+ mdio_rdturn_st:
+ // This state is used to read turn around state
+ // the output enable is switched off
+ begin
+ if (mdio_in)
+ set_mdio_stat = 1'b1;
+ mdio_out_en = 1'b0;
+ mdio_nxt_st = mdio_read_st;
+ end
+
+ mdio_write_st:
+ // This state transfers the 16 bits of data to the
+ // PHY
+ begin
+ mdio_out_en = 1'b1;
+ write_data_mux_sel = 1'b1;
+ if(inc_temp_count == SIXTEEN)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_out = transmit_data[15];
+ mdio_nxt_st = mdio_complete_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_out = transmit_data[15];
+ mdio_nxt_st = mdio_write_st;
+ end
+ end
+
+ mdio_read_st:
+ // This state receives the 16 bits of data from the
+ // PHY
+ begin
+ mdio_out_en = 1'b0;
+ read_data_mux_sel = 1'b1;
+ if(inc_temp_count == SIXTEEN)
+ begin
+ reset_temp_count = 1'b1;
+ mdio_nxt_st = mdio_complete_st;
+ end
+ else
+ begin
+ inc_count = 1'b1;
+ mdio_nxt_st = mdio_read_st;
+ end
+ end
+
+ mdio_complete_st:
+ // This completes the mdio transfers indicates to the
+ // application of such complete
+ begin
+ mdio_nxt_st = mdio_idle_st;
+ mdio_out_en = 1'b0;
+ read_data_mux_sel = 1'b0;
+ //mdio_cmd_done = 1'b1;
+// mdio_stat = 1'b0;
+ end
+ endcase
+ end
+always @(mdio_cur_st)
+ mdio_cmd_done = (mdio_cur_st == 4'd13);
+
+
+always @(posedge mdio_clk or negedge reset_n)
+begin
+ if (!reset_n)
+ mdio_stat <= 1'b0;
+ else if (set_mdio_stat)
+ mdio_stat <= 1'b1;
+ else if (clr_mdio_stat)
+ mdio_stat <= 1'b0;
+end
+
+
+// This latches the PHY address, Register address and the
+// Transmit data and the type of operation
+//
+ always @(posedge mdio_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ phy_addr <= 5'd0;
+ reg_addr <= 5'd0;
+ transmit_data <= 16'd0;
+ operation <= 1'b0;
+ receive_data <= 16'd0;
+ end
+ else
+ begin
+ if(go_mdio_sync)
+ begin
+ phy_addr <= mdio_phyad;
+ reg_addr <= mdio_regad;
+ if(mdio_op == WRITE)
+ begin
+ operation <= 1'b1;
+ transmit_data <= mdio_datain;
+ end
+ end
+ else
+ begin
+ operation <= 1'b0;
+ phy_addr <= phy_addr;
+ transmit_data <= transmit_data;
+ reg_addr <= reg_addr;
+ // receive_data <= receive_data; naveen 011299
+ end // else: !if(go_mdio)
+
+ if(phyaddr_mux_sel)
+ begin
+ /*
+ phy_addr[0] <= phy_addr[1];
+ phy_addr[1] <= phy_addr[2];
+ phy_addr[2] <= phy_addr[3];
+ phy_addr[3] <= phy_addr[4];
+ */
+ phy_addr[4] <= phy_addr[3];
+ phy_addr[3] <= phy_addr[2];
+ phy_addr[2] <= phy_addr[1];
+ phy_addr[1] <= phy_addr[0];
+ end
+ if(regaddr_mux_sel)
+ begin
+ reg_addr[4] <= reg_addr[3];
+ reg_addr[3] <= reg_addr[2];
+ reg_addr[2] <= reg_addr[1];
+ reg_addr[1] <= reg_addr[0];
+ end
+ if(write_data_mux_sel)
+ begin
+ transmit_data[15] <= transmit_data[14];
+ transmit_data[14] <= transmit_data[13];
+ transmit_data[13] <= transmit_data[12];
+ transmit_data[12] <= transmit_data[11];
+ transmit_data[11] <= transmit_data[10];
+ transmit_data[10] <= transmit_data[9];
+ transmit_data[9] <= transmit_data[8];
+ transmit_data[8] <= transmit_data[7];
+ transmit_data[7] <= transmit_data[6];
+ transmit_data[6] <= transmit_data[5];
+ transmit_data[5] <= transmit_data[4];
+ transmit_data[4] <= transmit_data[3];
+ transmit_data[3] <= transmit_data[2];
+ transmit_data[2] <= transmit_data[1];
+ transmit_data[1] <= transmit_data[0];
+ end
+ if(read_data_mux_sel)
+ begin
+ receive_data[0] <= mdio_in;
+ receive_data[1] <= receive_data[0];
+ receive_data[2] <= receive_data[1];
+ receive_data[3] <= receive_data[2];
+ receive_data[4] <= receive_data[3];
+ receive_data[5] <= receive_data[4];
+ receive_data[6] <= receive_data[5];
+ receive_data[7] <= receive_data[6];
+ receive_data[8] <= receive_data[7];
+ receive_data[9] <= receive_data[8];
+ receive_data[10] <= receive_data[9];
+ receive_data[11] <= receive_data[10];
+ receive_data[12] <= receive_data[11];
+ receive_data[13] <= receive_data[12];
+ receive_data[14] <= receive_data[13];
+ receive_data[15] <= receive_data[14];
+ end
+ // end // else: !if(go_mdio) naveen 011298
+ end // else: !if(!reset_n)
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+ // Temporary counter used to shift the data on the mdio line
+ // This is also used to receive data on the line
+ assign inc_temp_count = temp_count + 5'h1;
+
+ always @(posedge mdio_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ mdio_cur_st <= mdio_idle_st;
+ else
+ mdio_cur_st <= mdio_nxt_st;
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+ reg mdio_outen_reg, mdio_out_reg;
+
+ //----------------------------------------------
+ // Scan fix done for negedge FF-Dinesh-A for A200
+ // Note: Druring Scan Mode inverted mdio_clk used for
+ // mdio_outen_reg & mdio_out_reg
+ //-----------------------------------------------
+ wire mdio_clk_scan = (scan_mode) ? !mdio_clk : mdio_clk;
+
+ always @(negedge mdio_clk_scan or negedge reset_n)
+ begin
+ if(!reset_n)
+ begin
+ mdio_outen_reg <= 1'b0;
+ mdio_out_reg <= 1'b0;
+ end
+ else
+ begin
+ mdio_outen_reg <= mdio_out_en;
+ mdio_out_reg <= mdio_out;
+ end
+
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+ always @(posedge mdio_clk or negedge reset_n)
+ begin
+ if(!reset_n)
+ temp_count <= 5'b0;
+ else
+ begin
+ if(reset_temp_count)
+ temp_count <= 5'b0;
+ else if(inc_count)
+ temp_count <= inc_temp_count;
+ end // else: !if(reset_n)
+ end // always @ (posedge mdio_clk or negedge reset_n)
+
+
+
+endmodule
+
+
trunk/rtl/gmac/mac/g_md_intf.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/s2f_sync.v
===================================================================
--- trunk/rtl/gmac/mac/s2f_sync.v (nonexistent)
+++ trunk/rtl/gmac/mac/s2f_sync.v (revision 12)
@@ -0,0 +1,86 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+ Synchronizes the pulse from one clock to another
+ * clock domain
+***********************************************************************/
+//`timescale 1ns/100ps
+module s2f_sync (
+ //outputs
+ sync_out_pulse,
+ //inputs
+ in_pulse,
+ dest_clk,
+ reset_n);
+
+ output sync_out_pulse; //output synchronised to slow clock
+ input in_pulse; //input based on fast clock, pulse
+ input dest_clk; //slow clock
+ input reset_n;
+
+ reg sync1_out, sync2_out, sync3_out;
+
+ always @(posedge dest_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ sync1_out <= 0;
+ sync2_out <= 0;
+ sync3_out <= 0;
+ end // if (!reset_n)
+ else
+ begin
+ sync1_out <= in_pulse;
+ sync2_out <= sync1_out;
+ sync3_out <= sync2_out;
+ end // else: !if(reset_n)
+ end // always @ (posedge dest_clk or negedge reset_n)
+
+ assign sync_out_pulse = sync2_out && !sync3_out;
+endmodule // s2f_sync
+
+
+
+
+
trunk/rtl/gmac/mac/s2f_sync.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_cfg_mgmt.v
===================================================================
--- trunk/rtl/gmac/mac/g_cfg_mgmt.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_cfg_mgmt.v (revision 12)
@@ -0,0 +1,819 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+ cfg_mgmt.v: contains the configuration, register information, Application
+ read from any location. But can write to a limited set of locations,
+ Please refer to the design data sheets for register locations
+***********************************************************************/
+//`timescale 1ns/100ps
+module g_cfg_mgmt (
+ //List of Inputs
+
+ // Reg Bus Interface Signal
+ reg_cs,
+ reg_wr,
+ reg_addr,
+ reg_wdata,
+ reg_be,
+
+ // Outputs
+ reg_rdata,
+ reg_ack,
+
+ // Rx Status
+ rx_sts_vld,
+ rx_sts,
+
+ // Rx Status
+ tx_sts_vld,
+ tx_sts,
+
+ // MDIO READ DATA FROM PHY
+ md2cf_cmd_done,
+ md2cf_status,
+ md2cf_data,
+
+ app_clk,
+ app_reset_n,
+
+ //List of Outputs
+ // MII Control
+ cf2mi_loopback_en,
+ cf_mac_mode,
+ cf_chk_rx_dfl,
+ cf2mi_rmii_en,
+
+ cfg_uni_mac_mode_change_i,
+ cfg_crs_flow_ctrl_enb_i,
+
+ //CHANNEL enable
+ cf2tx_ch_en,
+ //CHANNEL CONTROL TX
+ cf_silent_mode,
+ cf2df_dfl_single,
+ cf2df_dfl_single_rx,
+ cf2tx_pad_enable,
+ cf2tx_append_fcs,
+ //CHANNEL CONTROL RX
+ cf2rx_ch_en,
+ cf2rx_strp_pad_en,
+ cf2rx_snd_crc,
+ cf2rx_pause_en,
+ cf2rx_addrchk_en,
+ cf2rx_runt_pkt_en,
+ cf2af_broadcast_disable,
+ cf_mac_sa,
+ cf2tx_pause_quanta,
+ cf2rx_max_pkt_sz,
+ cf2tx_force_bad_fcs,
+ cf2tx_tstate_mode,
+ //MDIO CONTROL & DATA
+ cf2md_datain,
+ cf2md_regad,
+ cf2md_phyad,
+ cf2md_op,
+ cf2md_go);
+
+ parameter mac_mdio_en = 1'b1;
+
+
+ //pin out definations
+ //---------------------------------
+ // Reg Bus Interface Signal
+ //---------------------------------
+ input reg_cs ;
+ input reg_wr ;
+ input [3:0] reg_addr ;
+ input [31:0] reg_wdata ;
+ input [3:0] reg_be ;
+
+ // Outputs
+ output [31:0] reg_rdata ;
+ output reg_ack ;
+
+ input rx_sts_vld ; // rx status valid indication, sync w.r.t app clk
+ input [7:0] rx_sts ; // rx status bits
+
+ input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
+ input tx_sts ; // tx status bits
+
+ //List of Inputs
+
+ input app_clk, app_reset_n;
+ input md2cf_cmd_done; // Read/Write MDIO completed
+ input md2cf_status; // MDIO transfer error
+ input [15:0] md2cf_data; // Data from PHY for a
+ // mdio read access
+
+
+ //List of Outputs
+ output cf2mi_rmii_en; // Working in RMII when set to 1
+ output cf_mac_mode; // mac mode set this to 1 for 100Mbs/10Mbs
+ output cf_chk_rx_dfl; // Check for RX Deferal
+ output [47:0] cf_mac_sa;
+ output [15:0] cf2tx_pause_quanta;
+ output cf2tx_ch_en; //enable the TX channel
+ output cf_silent_mode; // PHY Inactive
+ output [7:0] cf2df_dfl_single; //number of clk ticks for dfl
+ output [7:0] cf2df_dfl_single_rx; //number of clk ticks for dfl
+
+ output cf2tx_tstate_mode; //used for OFN's tstate enable on authentication interface
+ output cf2tx_pad_enable; //enable padding, < 64 bytes
+ output cf2tx_append_fcs; //append CRC for TX frames
+ output cf2rx_ch_en; //Enable RX channel
+ output cf2rx_strp_pad_en; //strip the padded bytes on RX frame
+ output cf2rx_snd_crc; //send FCS to application, else strip
+ //the FCS before sending to application
+ output cf2rx_pause_en; //enable flow control for full duplex using
+ //pause control frames
+ output cf2mi_loopback_en; // TX to RX loop back enable
+ output cf2rx_addrchk_en; //check the destination address, filter
+ output cf2rx_runt_pkt_en; //don't throw packets less than 64 bytes
+ output cf2af_broadcast_disable;
+ output [15:0] cf2md_datain;
+ output [4:0] cf2md_regad;
+ output [4:0] cf2md_phyad;
+ output cf2md_op;
+ output cf2md_go;
+
+ output [15:0] cf2rx_max_pkt_sz; //max rx packet size
+ output cf2tx_force_bad_fcs; //force bad fcs on tx
+
+ output cfg_uni_mac_mode_change_i;
+ output cfg_crs_flow_ctrl_enb_i;
+
+
+// Wire assignments for output signals
+ wire [15:0] cf2md_datain;
+ wire [4:0] cf2md_regad;
+ wire [4:0] cf2md_phyad;
+ wire cf2md_op;
+ wire cf2md_go;
+ wire mdio_cmd_done_sync;
+
+ wire int_mdio_cmd_done_sync;
+ assign mdio_cmd_done_sync = (mac_mdio_en) ? int_mdio_cmd_done_sync : 1'b0;
+
+ s2f_sync U1_s2f_sync ( .sync_out_pulse(int_mdio_cmd_done_sync),
+ .in_pulse(md2cf_cmd_done),
+ .dest_clk(app_clk),
+ .reset_n(app_reset_n));
+
+
+
+// Wire and Reg assignments for local signals
+ reg int_md2cf_status;
+ wire [7:0] mac_mode_out;
+ wire [7:0] tx_cntrl_out_1, rx_cntrl_out_1;
+ wire [7:0] tx_cntrl_out_2, rx_cntrl_out_2;
+ wire [7:0] dfl_params_rx_out;
+ wire [7:0] dfl_params1_out;
+ wire [7:0] slottime_out_1;
+ wire [7:0] slottime_out_2;
+ wire [31:0] mdio_cmd_out;
+ wire [7:0] mdio_stat_out_1;
+ wire [7:0] mdio_stat_out_2;
+ wire [7:0] mdio_stat_out_3;
+ wire [7:0] mdio_stat_out_4;
+ wire [7:0] mdio_cmd_out_1;
+ wire [7:0] mdio_cmd_out_2;
+ wire [7:0] mdio_cmd_out_3;
+ wire [7:0] mdio_cmd_out_4;
+ wire [7:0] mac_sa_out_1;
+ wire [7:0] mac_sa_out_2;
+ wire [7:0] mac_sa_out_3;
+ wire [7:0] mac_sa_out_4;
+ wire [7:0] mac_sa_out_5;
+ wire [7:0] mac_sa_out_6;
+ wire [7:0] pause_quanta_out_1;
+ wire [7:0] pause_quanta_out_2;
+ wire [47:0] cf_mac_sa;
+ wire [15:0] cf2tx_pause_quanta;
+ wire [15:0] cf2rx_max_pkt_sz;
+ wire cf2tx_force_bad_fcs;
+ wire cf2tx_tstate_mode;
+ reg force_bad_fcs;
+ reg cont_force_bad_fcs;
+ wire [31:0] mdio_stat_out;
+ reg cf2tx_force_bad_fcs_en;
+ reg cf2tx_cont_force_bad_fcs_en;
+ reg [15:0] int_mdio_stat_out;
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+wire sw_rd_en;
+wire sw_wr_en;
+wire [3:0] sw_addr ; // addressing 16 registers
+wire [3:0] wr_be ;
+
+reg [31:0] reg_rdata ;
+reg reg_ack ;
+
+wire [31:0] reg_0; // Software_Reg_0
+wire [31:0] reg_1; // Software-Reg_1
+wire [31:0] reg_2; // Software-Reg_2
+wire [31:0] reg_3; // Software-Reg_3
+wire [31:0] reg_4; // Software-Reg_4
+wire [31:0] reg_5; // Software-Reg_5
+wire [31:0] reg_6; // Software-Reg_6
+wire [31:0] reg_7; // Software-Reg_7
+wire [31:0] reg_8; // Software-Reg_8
+wire [31:0] reg_9; // Software-Reg_9
+wire [31:0] reg_10; // Software-Reg_10
+wire [31:0] reg_11; // Software-Reg_11
+wire [31:0] reg_12; // Software-Reg_12
+wire [31:0] reg_13; // Software-Reg_13
+wire [31:0] reg_14; // Software-Reg_14
+wire [31:0] reg_15; // Software-Reg_15
+reg [31:0] reg_out;
+
+//-----------------------------------------------------------------------
+// Internal Logic Starts here
+//-----------------------------------------------------------------------
+ assign sw_addr = reg_addr [3:0];
+ assign sw_rd_en = reg_cs & !reg_wr;
+ assign sw_wr_en = reg_cs & reg_wr;
+ assign wr_be = reg_be;
+
+
+//-----------------------------------------------------------------------
+// Read path mux
+//-----------------------------------------------------------------------
+
+always @ (posedge app_clk or negedge app_reset_n)
+begin : preg_out_Seq
+ if (app_reset_n == 1'b0)
+ begin
+ reg_rdata [31:0] <= 32'h0000_0000;
+ reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !reg_ack)
+ begin
+ reg_rdata [31:0] <= reg_out [31:0];
+ reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !reg_ack)
+ reg_ack <= 1'b1;
+ else
+ begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
+wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
+wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
+wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
+wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
+wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
+wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
+wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
+wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
+wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
+wire sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
+wire sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
+wire sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
+wire sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
+wire sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
+wire sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
+wire sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
+wire sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
+
+
+always @( *)
+begin : preg_sel_Com
+
+ reg_out [31:0] = 32'd0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0 [31:0];
+ 4'b0001 : reg_out [31:0] = reg_1 [31:0];
+ 4'b0010 : reg_out [31:0] = reg_2 [31:0];
+ 4'b0011 : reg_out [31:0] = reg_3 [31:0];
+ 4'b0100 : reg_out [31:0] = reg_4 [31:0];
+ 4'b0101 : reg_out [31:0] = reg_5 [31:0];
+ 4'b0110 : reg_out [31:0] = reg_6 [31:0];
+ 4'b0111 : reg_out [31:0] = reg_7 [31:0];
+ 4'b1000 : reg_out [31:0] = reg_8 [31:0];
+ 4'b1001 : reg_out [31:0] = reg_9 [31:0];
+ 4'b1010 : reg_out [31:0] = reg_10 [31:0];
+ 4'b1011 : reg_out [31:0] = reg_11 [31:0];
+ 4'b1100 : reg_out [31:0] = reg_12 [31:0];
+ 4'b1101 : reg_out [31:0] = reg_13 [31:0];
+ 4'b1110 : reg_out [31:0] = reg_14 [31:0];
+ 4'b1111 : reg_out [31:0] = reg_15 [31:0];
+ endcase
+end
+
+
+ //instantiate all the registers
+
+ //========================================================================//
+ // TX_CNTRL_REGISTER : Address value 00H
+ // BIT[0] = Transmit Channel Enable
+ // BIT[1] = DONT CARE
+ // BIT[2] = Retry Packet in case of Collisions
+ // BIT[3] = Enable padding
+ // BIT[4] = Append CRC
+ // BIT[5] = Perform a Two Part Deferral
+ // BIT[6] = RMII Enable bit
+ // BIT[7] = Force TX FCS Error
+
+
+generic_register #(8,0 ) tx_cntrl_reg_1 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[0] }} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (tx_cntrl_out_1[7:0] )
+ );
+
+generic_register #(8,0 ) tx_cntrl_reg_2 (
+ .we ({8{sw_wr_en_0 &
+ wr_be[1] }} ),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (tx_cntrl_out_2[7:0] )
+ );
+
+ assign cf2tx_ch_en = tx_cntrl_out_1[0];
+ assign cf2tx_pad_enable = tx_cntrl_out_1[3];
+ assign cf2tx_append_fcs = tx_cntrl_out_1[4];
+ assign cf2tx_tstate_mode = tx_cntrl_out_1[6];
+ assign cf2tx_force_bad_fcs = tx_cntrl_out_1[7];
+
+assign reg_0[15:0] = {tx_cntrl_out_2,tx_cntrl_out_1};
+
+ //=========================================================================//
+ // RX_CNTRL_REGISTER 1 : Address Value 04H
+ // BIT[0] = Receive Channel Enable
+ // BIT[1] = Strip Padding from the Receive data
+ // BIT[2] = Send CRC along with data to the host
+ // BIT[3] = Enable pause frame detect
+ // BIT[4] = Check RX Deferral
+ // BIT[5] = Receive Address Check Enable
+ // BIT[6] = Receive Runt Packet
+ // BIT[7] = Broad Cast Rx Disable
+ // BIT[31:8] = Reserved
+ generic_register #(8,0 ) rx_cntrl_reg_1 (
+ .we ({8{sw_wr_en_1 &
+ wr_be[0] }} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (rx_cntrl_out_1[7:0] )
+ );
+
+ assign cf2rx_ch_en = rx_cntrl_out_1[0];
+ assign cf2rx_strp_pad_en = rx_cntrl_out_1[1];
+ assign cf2rx_snd_crc = rx_cntrl_out_1[2];
+ assign cf2rx_pause_en = rx_cntrl_out_1[3];
+ assign cf_chk_rx_dfl = rx_cntrl_out_1[4];
+ assign cf2rx_addrchk_en = rx_cntrl_out_1[5];
+ assign cf2rx_runt_pkt_en = rx_cntrl_out_1[6];
+ assign cf2af_broadcast_disable = rx_cntrl_out_1[7];
+
+
+assign reg_1[7:0] = {rx_cntrl_out_1};
+ //========================================================================//
+ //TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
+ //BIT[7:0] = Defferal TX
+ //BIT[15:8] = Defferal RX
+
+ generic_register #(8,0 ) dfl_params1_en_reg (
+ .we ({8{sw_wr_en_2 &
+ wr_be[0] }} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (dfl_params1_out[7:0] )
+ );
+
+ assign cf2df_dfl_single = dfl_params1_out[7:0];
+
+ generic_register #(8,0 ) dfl_params_rx_en_reg (
+ .we ({8{sw_wr_en_2 &
+ wr_be[1] }} ),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (dfl_params_rx_out[7:0] )
+ );
+ assign cf2df_dfl_single_rx = dfl_params_rx_out[7:0];
+
+assign reg_2[15:0] = {dfl_params_rx_out,dfl_params1_out};
+
+ //========================================================================//
+ // MAC_MODE REGISTER: Address value 0CH
+ // BIT[0] = 10/100 or 1000 1 1000, 0 is 10/100 Channel Enable
+ // BIT[1] = Mii/Rmii Default is Mii
+ // BIT[2] = MAC used in Loop back Mode
+ // BIT[3] = Burst Enable
+ // BIT[4] = Half Duplex
+ // BIT[5] = Silent Mode (During Loopback the Tx --> RX and NOT to PHY)
+ // BIT[6] = crs based flow control enable
+ // BIT[7] = Mac Mode Change
+
+ generic_register #(8,0 ) mac_mode_reg (
+ .we ({8{sw_wr_en_3 & wr_be[0]}}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_mode_out[7:0] )
+ );
+
+ assign cf_mac_mode = mac_mode_out[0];
+ assign cf2mi_rmii_en = mac_mode_out[1];
+ assign cf2mi_loopback_en = mac_mode_out[2];
+ assign cf_silent_mode = mac_mode_out[5];
+ assign cfg_crs_flow_ctrl_enb_i = mac_mode_out[6];
+ assign cfg_uni_mac_mode_change_i = mac_mode_out[7];
+
+
+assign reg_3[7:0] = {mac_mode_out};
+ //========================================================================//
+ //MDIO COMMAND REGISTER: ADDRESS 10H
+ //BIT[15:0] = MDIO DATA TO PHY
+ //BIT[20:16] = MDIO REGISTER ADDR
+ //BIT[25:21] = MDIO PHY ADDR
+ //BIT[26] = MDIO COMMAND OPCODE READ/WRITE(0:read,1:write)
+ //BIT[31] = GO MDIO
+
+ generic_register #(8,0 ) mdio_cmd_reg_1 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[0] }} ),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_1[7:0] )
+ );
+
+ generic_register #(8,0 ) mdio_cmd_reg_2 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[1] }} ),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_2[7:0] )
+ );
+
+ generic_register #(8,0 ) mdio_cmd_reg_3 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[2] }} ),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_3[7:0] )
+ );
+
+
+
+ //byte_reg mdio_cmd_reg_4 (.we({8{mdio_cmd_en_4 && cfg_rw}}), .data_in(reg_wdata),
+ // .reset_n(app_reset_n), .clk(app_clk), .data_out(mdio_cmd_out_4));
+
+
+ generic_register #(7,0 ) mdio_cmd_reg_4 (
+ .we ({7{sw_wr_en_4 &
+ wr_be[3] }} ),
+ .data_in (reg_wdata[30:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_4[6:0] )
+ );
+
+req_register #(0 ) u_mdio_req (
+ .cpu_we ({sw_wr_en_4 &
+ wr_be[3] } ),
+ .cpu_req (reg_wdata[31] ),
+ .hware_ack (mdio_cmd_done_sync ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mdio_cmd_out_4[7] )
+ );
+
+
+ assign mdio_cmd_out = {mdio_cmd_out_4, mdio_cmd_out_3,mdio_cmd_out_2,mdio_cmd_out_1};
+
+ assign reg_4 = {mdio_cmd_out};
+
+ assign cf2md_datain = mdio_cmd_out[15:0];
+ assign cf2md_regad = mdio_cmd_out[20:16];
+ assign cf2md_phyad = mdio_cmd_out[25:21];
+ assign cf2md_op = mdio_cmd_out[26];
+ assign cf2md_go = mdio_cmd_out[31];
+
+
+ //========================================================================//
+ //MDIO STATUS REGISTER: ADDRESS 14H
+ //BIT[15:0] = MDIO DATA FROM PHY
+ //BIT[31] = STATUS OF MDIO TRANSFER
+
+ always @(posedge app_clk
+ or negedge app_reset_n)
+ begin
+ if(!app_reset_n) begin
+ int_mdio_stat_out <= 16'b0;
+ int_md2cf_status <= 1'b0;
+ end
+ else
+ if(mdio_cmd_done_sync)
+ begin
+ int_mdio_stat_out[15:0] <= md2cf_data;
+ // int_mdio_stat_out[30:16] <= int_mdio_stat_out[30:16];
+ int_md2cf_status <= md2cf_status;
+ end // else: !if(reset)
+ end // always @ (posedge app_clk...
+
+ assign mdio_stat_out = (mac_mdio_en == 1'b1) ? {int_md2cf_status, 15'b0, int_mdio_stat_out} : 32'b0;
+
+
+ assign reg_5 = {mdio_stat_out};
+
+ //========================================================================//
+ //MAC Source Address Register 18-1C
+
+ generic_register #(8,0 ) mac_sa_reg_1 (
+ .we ({8{sw_wr_en_6 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_1[7:0] )
+ );
+ generic_register #(8,0 ) mac_sa_reg_2 (
+ .we ({8{sw_wr_en_6 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_2[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_3 (
+ .we ({8{sw_wr_en_6 & wr_be[2] }}),
+ .data_in (reg_wdata[23:16] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_3[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_4 (
+ .we ({8{sw_wr_en_6 & wr_be[3] }}),
+ .data_in (reg_wdata[31:24] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_4[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_5 (
+ .we ({8{sw_wr_en_7 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_5[7:0] )
+ );
+
+ generic_register #(8,0 ) mac_sa_reg_6 (
+ .we ({8{sw_wr_en_7 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (mac_sa_out_6[7:0] )
+ );
+
+// assign cf_mac_sa = { mac_sa_out_1, mac_sa_out_2, mac_sa_out_3,
+// mac_sa_out_4, mac_sa_out_5, mac_sa_out_6};
+ assign cf_mac_sa = { mac_sa_out_6, mac_sa_out_5, mac_sa_out_4,
+ mac_sa_out_3, mac_sa_out_2, mac_sa_out_1};
+
+ assign reg_6[31:0] = cf_mac_sa[31:0];
+ assign reg_7[15:0] = cf_mac_sa[47:32];
+//========================================================================//
+//MAC max packet size Register 20
+
+ generic_register #(8,0 ) max_pkt_sz_reg0 (
+ .we ({8{sw_wr_en_8 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cf2rx_max_pkt_sz[7:0] )
+ );
+
+ generic_register #(8,0 ) max_pkt_sz_reg1 (
+ .we ({8{sw_wr_en_8 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (cf2rx_max_pkt_sz[15:8] )
+ );
+
+ assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
+ //========================================================================//
+ //Pause Quanta Register 24
+
+ generic_register #(8,0 ) pause_quanta_reg_1 (
+ .we ({8{sw_wr_en_9 & wr_be[0] }}),
+ .data_in (reg_wdata[7:0] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (pause_quanta_out_1[7:0] )
+ );
+
+ generic_register #(8,0 ) pause_quanta_reg_2 (
+ .we ({8{sw_wr_en_9 & wr_be[1] }}),
+ .data_in (reg_wdata[15:8] ),
+ .reset_n (app_reset_n ),
+ .clk (app_clk ),
+
+ //List of Outs
+ .data_out (pause_quanta_out_2[7:0] )
+ );
+
+
+ assign cf2tx_pause_quanta = {pause_quanta_out_1 , pause_quanta_out_2};
+
+
+ assign reg_9[15:0] = cf2tx_pause_quanta;
+
+
+
+//-----------------------------------------------------------------------
+// RX-Clock Static Counter Status Signal
+//-----------------------------------------------------------------------
+// Note: rx_sts_vld signal is only synchronised w.r.t application clock, and
+// assumption is rx_sts is stable untill next packet received
+ assign rx_good_frm_trig = rx_sts_vld && (rx_sts[7:0] == 'h0);
+ assign rx_bad_frm_trig = rx_sts_vld && (rx_sts[7:0] != 'h0);
+
+
+stat_counter #(16) u_stat_rx_good_frm (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_trigger (rx_good_frm_trig),
+
+ . reg_sel (sw_wr_en_10 ),
+ . reg_wr_data (reg_wdata[15:0] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (reg_10[15:0] )
+ );
+
+stat_counter #(16) u_stat_rx_bad_frm (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_trigger (rx_bad_frm_trig ),
+
+ . reg_sel (sw_wr_en_11 ),
+ . reg_wr_data (reg_wdata[15:0] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (reg_11[15:0] )
+ );
+
+
+ wire tx_good_frm_trig = tx_sts_vld ;
+
+stat_counter #(16) u_stat_tx_good_frm (
+ // Clock and Reset Signals
+ . sys_clk (app_clk ),
+ . s_reset_n (app_reset_n ),
+
+ . count_trigger (tx_good_frm_trig ),
+
+ . reg_sel (sw_wr_en_12 ),
+ . reg_wr_data (reg_wdata[15:0] ),
+ . reg_wr (wr_be[0] ), // Byte write not supported for cntr
+
+ . cntr_intr ( ),
+ . cntrout (reg_12[15:0] )
+ );
+
+// reg_13 is free
+
+generic_intr_stat_reg #(9) u_intr_stat (
+ //inputs
+ . clk (app_clk ),
+ . reset_n (app_reset_n ),
+ . reg_we ({{1{sw_wr_en_13 & wr_be[1]}},
+ {8{sw_wr_en_13 & wr_be[0]}}} ),
+ . reg_din (reg_wdata[8:0] ),
+ . hware_req ({tx_sts,rx_sts[7:0]} ),
+
+ //outputs
+ . data_out (reg_14[8:0] )
+ );
+
+
+
+
+
+endmodule
+
+
trunk/rtl/gmac/mac/g_cfg_mgmt.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/mac/g_deferral.v
===================================================================
--- trunk/rtl/gmac/mac/g_deferral.v (nonexistent)
+++ trunk/rtl/gmac/mac/g_deferral.v (revision 12)
@@ -0,0 +1,197 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//`timescale 1ns/100ps
+
+/***************************************************************
+ Description:
+ deferral.v : This block performs the deferral algorithm for
+ half duplex mode, as per the IEEE 802.3 section 4.2.3.2.2
+ This block also implements the optional two part deferral
+ mechanism.
+***********************************************************************/
+
+module g_deferral (
+ df2tx_dfl_dn,
+ cf2df_dfl_single,
+ phy_tx_en,
+ phy_tx_er,
+ tx_clk,
+ app_reset_n);
+
+
+ input [7:0] cf2df_dfl_single; //program with 9.6 ms
+ input phy_tx_en; //TX frame is done, wait for IPG
+ //used in FULL duplex
+ input phy_tx_er; //TX Error
+ input tx_clk; //MII provided tx_clk
+ input app_reset_n;
+
+ output df2tx_dfl_dn; //when active hold the TX, else
+ //TX can send preamble
+
+ wire df2tx_dfl_dn;
+
+ parameter dfl_idle_st = 6'b000000;
+ parameter dfl_dfl_st = 6'b000010;
+ parameter dfl_full_tx_dn_st = 6'b010000;
+ parameter dfl_wipg_st = 6'b100000;
+
+ reg [5:0] curr_dfl_st, nxt_dfl_st;
+ reg dfl_dn;
+ reg strt_dfl;
+ reg [7:0] dfl_cntr;
+
+ reg phy_tx_en_d;
+
+ wire was_xmitted;
+
+ assign df2tx_dfl_dn = dfl_dn;
+ /*****************************************************************
+ * Synchronous process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(posedge tx_clk or negedge app_reset_n)
+ begin
+ if (!app_reset_n)
+ curr_dfl_st <= dfl_idle_st;
+ else
+ curr_dfl_st <= nxt_dfl_st;
+ end // always @ (posedge tx_clk or negedge app_reset_n)
+
+ /*****************************************************************
+ * comb process for the FSM to enable and disable TX on
+ * receive activity
+ *****************************************************************/
+ always @(curr_dfl_st or dfl_cntr
+ or phy_tx_en or phy_tx_er or was_xmitted)
+ begin
+ strt_dfl = 0;
+ dfl_dn = 0;
+ nxt_dfl_st = curr_dfl_st;
+
+ case (curr_dfl_st)
+ dfl_idle_st :
+ begin
+ dfl_dn = 1;
+ if (phy_tx_en)
+ begin
+ dfl_dn = 0;
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // if (phy_tx_en)
+ else
+ nxt_dfl_st = dfl_idle_st;
+ end // case: dfl_idle_st
+
+ dfl_full_tx_dn_st :
+ begin
+ // full duplex mode, wait till the current tx
+ // frame is transmitted and wait for IPG time,
+ // no need to wait for two part defferal
+ if (!phy_tx_en && !phy_tx_er)
+ begin
+ strt_dfl = 1;
+ nxt_dfl_st = dfl_wipg_st;
+ end // if (!phy_tx_en)
+ else
+ nxt_dfl_st = dfl_full_tx_dn_st;
+ end // case: dfl_full_tx_dn_st
+
+ dfl_wipg_st :
+ begin
+ // This state is reached when there is no transmit
+ // in progress. In this state IPG counter should checked
+ // and upon its expiry indicate deferral done
+ // to tx_fsm block
+ if (dfl_cntr == 8'd0)
+ begin
+ dfl_dn = 1;
+ nxt_dfl_st = dfl_idle_st;
+ end
+ else
+ nxt_dfl_st = dfl_wipg_st;
+ end // case: dfl_wipg_st
+
+ default :
+ begin
+ nxt_dfl_st = dfl_idle_st;
+ end
+ endcase // case (curr_dfl_st)
+ end // always @ (curr_dfl_st )
+
+ //counter for the single phase deferral scheme
+ always @(posedge tx_clk or negedge app_reset_n)
+ begin
+ if (!app_reset_n)
+ dfl_cntr <= 8'd0;
+ else
+ begin
+ if (strt_dfl)
+ begin
+ dfl_cntr <= cf2df_dfl_single;
+ end
+ else
+ dfl_cntr <= dfl_cntr - 1;
+ end // else: !if(app_reset_n)
+ end // always @ (posedge tx_clk or negedge app_reset_n)
+
+
+ // Mandar
+ // Detect Packet end
+ assign was_xmitted = (phy_tx_en_d == 1'b1 && phy_tx_en == 1'b0) ? 1'b1 : 1'b0;
+
+
+ always @(posedge tx_clk or negedge app_reset_n)
+ begin
+ if (!app_reset_n)
+ phy_tx_en_d <= 1'b0;
+ else
+ phy_tx_en_d <= phy_tx_en;
+ end // always @ (posedge tx_clk or negedge app_reset_n)
+
+
+
+endmodule // deferral
+
+
+
+
trunk/rtl/gmac/mac/g_deferral.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/top/filelist_top.f
===================================================================
--- trunk/rtl/gmac/top/filelist_top.f (nonexistent)
+++ trunk/rtl/gmac/top/filelist_top.f (revision 12)
@@ -0,0 +1,22 @@
+g_mac_top.v
+dble_reg.v
+g_tx_fsm.v
+g_deferral.v
+g_tx_top.v
+g_rx_fsm.v
+g_cfg_mgmt.v
+s2f_sync.v
+g_md_intf.v
+g_ad_fltr.v
+g_deferral_rx.v
+g_rx_top.v
+g_mii_intf.v
+g_mac_core.v
+g_rx_crc32.v
+g_tx_crc32.v
+async_fifo.v
+-v registers.v
+-v stat_counter.v
+-v toggle_sync.v
++lint=all
++v2k
Index: trunk/rtl/gmac/top/g_mac_top.v
===================================================================
--- trunk/rtl/gmac/top/g_mac_top.v (nonexistent)
+++ trunk/rtl/gmac/top/g_mac_top.v (revision 12)
@@ -0,0 +1,317 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+// ------------------------------------------------------------------------
+// Description :
+// This module instantiates the MAC block and the FIFO interface
+//
+// ------------------------------------------------------------------------
+module g_mac_top (
+ scan_mode,
+ s_reset_n,
+ tx_reset_n,
+ rx_reset_n,
+ reset_mdio_clk_n,
+ app_reset_n,
+
+ app_clk,
+ app_send_pause_i,
+ app_send_pause_active_o,
+ app_send_jam_i,
+
+ // Application RX FIFO Interface
+ app_txfifo_wren_i,
+ app_txfifo_wrdata_i,
+ app_txfifo_full_o,
+ app_txfifo_space_o,
+
+ // Application TX FIFO Interface
+ app_rxfifo_rden_i,
+ app_rxfifo_empty_o,
+ app_rxfifo_cnt_o,
+ app_rxfifo_rdata_o,
+
+ // Conntrol Bus Sync with Application Clock
+ reg_cs,
+ reg_wr,
+ reg_addr,
+ reg_wdata,
+ reg_be,
+
+ // Outputs
+ reg_rdata,
+ reg_ack,
+
+
+ // Phy Signals
+
+ // Line Side Interface TX Path
+ phy_tx_en,
+ phy_tx_er,
+ phy_txd,
+ phy_tx_clk,
+
+ // Line Side Interface RX Path
+ phy_rx_clk,
+ phy_rx_er,
+ phy_rx_dv,
+ phy_rxd,
+ phy_crs,
+
+ //MDIO interface
+ mdio_clk,
+ mdio_in,
+ mdio_out_en,
+ mdio_out
+ );
+
+parameter W = 8'd9;
+parameter DP = 8'd32;
+parameter AW = (DP == 2) ? 1 :
+ (DP == 4) ? 2 :
+ (DP == 8) ? 3 :
+ (DP == 16) ? 4 :
+ (DP == 32) ? 5 :
+ (DP == 64) ? 6 :
+ (DP == 128) ? 7 :
+ (DP == 256) ? 8 : 0;
+
+
+//-----------------------------------------------------------------------
+// INPUT/OUTPUT DECLARATIONS
+//-----------------------------------------------------------------------
+input scan_mode;
+input s_reset_n;
+input tx_reset_n;
+input rx_reset_n;
+input reset_mdio_clk_n;
+input app_reset_n;
+
+//-----------------------------------------------------------------------
+// Application Clock Related Declaration
+//-----------------------------------------------------------------------
+input app_clk;
+input app_send_pause_i;
+output app_send_pause_active_o;
+input app_send_jam_i;
+
+
+// Application RX FIFO Interface
+input app_txfifo_wren_i;
+input [8:0] app_txfifo_wrdata_i;
+output app_txfifo_full_o;
+output [AW:0] app_txfifo_space_o;
+
+// Application TX FIFO Interface
+input app_rxfifo_rden_i;
+output app_rxfifo_empty_o;
+output [AW:0] app_rxfifo_cnt_o;
+output [8:0] app_rxfifo_rdata_o;
+
+// Conntrol Bus Sync with Application Clock
+//---------------------------------
+// Reg Bus Interface Signal
+//---------------------------------
+input reg_cs ;
+input reg_wr ;
+input [3:0] reg_addr ;
+input [31:0] reg_wdata ;
+input [3:0] reg_be ;
+
+ // Outputs
+output [31:0] reg_rdata ;
+output reg_ack ;
+
+//-----------------------------------------------------------------------
+// Line-Tx Signal
+//-----------------------------------------------------------------------
+output phy_tx_en;
+output phy_tx_er;
+output [7:0] phy_txd;
+input phy_tx_clk;
+
+//-----------------------------------------------------------------------
+// Line-Rx Signal
+//-----------------------------------------------------------------------
+input phy_rx_clk;
+input phy_rx_er;
+input phy_rx_dv;
+input [7:0] phy_rxd;
+input phy_crs;
+
+
+//-----------------------------------------------------------------------
+// MDIO Signal
+//-----------------------------------------------------------------------
+ input mdio_clk;
+ input mdio_in;
+ output mdio_out_en;
+ output mdio_out;
+
+//---------------------
+// RX FIFO Interface Signal
+ wire clr_rx_error_from_rx_fsm_o;
+ wire rx_fifo_full_i;
+ wire rx_fifo_wr_o;
+ wire [8:0] rx_fifo_data_o;
+ wire rx_commit_wr_o;
+ wire rx_commit_write_done_o;
+ wire rx_rewind_wr_o;
+ wire rx_fifo_error = 1'b0;
+
+//-----------------------------------------------------------------------
+// TX-Clock Domain Status Signal
+//-----------------------------------------------------------------------
+ wire tx_commit_read;
+ wire tx_fifo_rd;
+
+ wire [8:0] tx_fifo_data;
+ wire tx_fifo_empty;
+ wire tx_fifo_rdy;
+ wire [AW:0] tx_fifo_aval;
+
+g_mac_core u_mac_core (
+ .scan_mode (scan_mode),
+ .s_reset_n (s_reset_n) ,
+ .tx_reset_n (tx_reset_n) ,
+ .rx_reset_n (rx_reset_n) ,
+ .reset_mdio_clk_n (reset_mdio_clk_n) ,
+ .app_reset_n (app_reset_n) ,
+
+ // Reg Bus Interface Signal
+ . reg_cs (reg_cs),
+ . reg_wr (reg_wr),
+ . reg_addr (reg_addr),
+ . reg_wdata (reg_wdata),
+ . reg_be (reg_be),
+
+ // Outputs
+ . reg_rdata (reg_rdata),
+ . reg_ack (reg_ack),
+
+ .app_clk (app_clk) ,
+ .app_send_pause_i (app_send_pause_i) ,
+ .app_send_pause_active_o (app_send_pause_active_o) ,
+ .app_send_jam_i (app_send_jam_i) ,
+
+ // Conntrol Bus Sync with Application Clock
+
+
+
+ // RX FIFO Interface Signal
+ .rx_fifo_full_i (rx_fifo_full_i) ,
+ .rx_fifo_wr_o (rx_fifo_wr_o) ,
+ .rx_fifo_data_o (rx_fifo_data_o) ,
+ .rx_commit_wr_o (rx_commit_wr_o) ,
+ .rx_rewind_wr_o (rx_rewind_wr_o) ,
+ .rx_commit_write_done_o (rx_commit_write_done_o) ,
+ .clr_rx_error_from_rx_fsm_o(clr_rx_error_from_rx_fsm_o) ,
+ .rx_fifo_error_i (rx_fifo_error) ,
+
+ // TX FIFO Interface Signal
+ .tx_fifo_data_i (tx_fifo_data) ,
+ .tx_fifo_empty_i (tx_fifo_empty) ,
+ .tx_fifo_rdy_i (tx_fifo_rdy) , // See to connect to config
+ .tx_fifo_rd_o (tx_fifo_rd) ,
+ .tx_commit_read_o (tx_commit_read) ,
+
+ // Phy Signals
+
+ // Line Side Interface TX Path
+ .phy_tx_en (phy_tx_en) ,
+ .phy_tx_er (phy_tx_er) ,
+ .phy_txd (phy_txd) ,
+ .phy_tx_clk (phy_tx_clk) ,
+
+ // Line Side Interface RX Path
+ .phy_rx_clk (phy_rx_clk) ,
+ .phy_rx_er (phy_rx_er) ,
+ .phy_rx_dv (phy_rx_dv) ,
+ .phy_rxd (phy_rxd) ,
+ .phy_crs (phy_crs) ,
+
+ //MDIO interface
+ .mdio_clk (mdio_clk) ,
+ .mdio_in (mdio_in) ,
+ .mdio_out_en (mdio_out_en) ,
+ .mdio_out (mdio_out)
+ );
+
+assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
+
+async_fifo #(W,DP,0,0) u_mac_txfifo (
+ .wr_clk (app_clk),
+ .wr_reset_n (app_reset_n),
+ .wr_en (app_txfifo_wren_i),
+ .wr_data (app_txfifo_wrdata_i),
+ .full (app_txfifo_full_o), // sync'ed to wr_clk
+ .wr_total_free_space (app_txfifo_space_o),
+
+ .rd_clk (phy_tx_clk),
+ .rd_reset_n (tx_reset_n),
+ .rd_en (tx_fifo_rd),
+ .empty (tx_fifo_empty), // sync'ed to rd_clk
+ .rd_total_aval (tx_fifo_aval),
+ .rd_data (tx_fifo_data)
+ );
+
+async_fifo #(W,DP,0,0) u_mac_rxfifo (
+ .wr_clk (phy_rx_clk),
+ .wr_reset_n (rx_reset_n),
+ .wr_en (rx_fifo_wr_o),
+ .wr_data (rx_fifo_data_o),
+ .full (rx_fifo_full_i), // sync'ed to wr_clk
+ .wr_total_free_space (),
+
+ .rd_clk (app_clk),
+ .rd_reset_n (app_reset_n),
+ .rd_en (app_rxfifo_rden_i),
+ .empty (app_rxfifo_empty_o), // sync'ed to rd_clk
+ .rd_total_aval (app_rxfifo_cnt_o),
+ .rd_data (app_rxfifo_rdata_o)
+ );
+
+
+
+endmodule
+
Index: trunk/rtl/gmac/crc32/g_rx_crc32.v
===================================================================
--- trunk/rtl/gmac/crc32/g_rx_crc32.v (nonexistent)
+++ trunk/rtl/gmac/crc32/g_rx_crc32.v (revision 12)
@@ -0,0 +1,302 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/***************************************************************
+ Description:
+ rx_crc32.v: This block contains the crc32 checker.
+ * CRC is generated in the receive data when mi2rc_rcv_valid is asserted.
+ * For the recieve data. crc_ok indicates whenther the packet was
+ * good or bad.
+ * The 32-bit crc shift register is reset to all 1's when
+ * mi2rc_strt_rcv is asserted.
+
+ *********************************************************************/
+module g_rx_crc32 (
+ // CRC Valid signal to rx_fsm
+ rc2rf_crc_ok,
+
+ // Global Signals
+ phy_rx_clk,
+ reset_n,
+ // CRC Data signals
+ mi2rc_strt_rcv,
+ mi2rc_rcv_valid,
+ mi2rc_rx_byte
+ );
+
+ // defx[ine inputs and outputs.
+
+ output rc2rf_crc_ok; // asserted when crc check is ok. to rx.
+
+ input phy_rx_clk; // serial clock from phy.
+ input reset_n; // global asynchronous reset.
+
+ input mi2rc_rcv_valid; // when asserted, crc is computed on
+ // rx_crc_data. from rx.
+ input mi2rc_strt_rcv; // when asserted, crc shift register is
+ // reset to all 1's. from rx.
+ input [7:0] mi2rc_rx_byte; // receive data. from rx.
+
+
+
+
+ // reg/wire declarations for primary outputs.
+ wire rc2rf_crc_ok;
+
+ // define constants and parameters here.
+ // define local signals here.
+
+ wire [7:0] crc_in;
+ wire gen_crc;
+ reg [31:0] current_crc, next_crc;
+ reg crc_ok_ul;
+
+ wire [31:0] rx_fcs;
+
+ // code starts here.
+
+ // select either rx_crc_data or tx_data as the input to crc generator.
+ assign crc_in = mi2rc_rx_byte;
+
+ // enable crc generator
+
+ assign gen_crc = mi2rc_rcv_valid ; //
+
+ // 32-bit crc shift register for crc calculation.
+
+ always @(posedge phy_rx_clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else
+ begin
+ if (mi2rc_strt_rcv)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else if (gen_crc) // generate crc
+ begin
+ current_crc <= next_crc;
+ end // else: !if(tx_reset_crc || mi2rc_strt_rcv)
+ end // else: !if(!reset_n)
+ end // always @ (posedge phy_rx_clk or negedge reset_n)
+
+ // combinational logic to generate next_crc
+
+ always @(current_crc or crc_in)
+ begin
+
+ next_crc[0] = current_crc[8] ^ current_crc[2] ^ crc_in[2];
+ next_crc[1] = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[3] ^ crc_in[3];
+ next_crc[2] = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[4] ^
+ crc_in[4];
+ next_crc[3] = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[4] = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[3] ^ crc_in[3] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[5] = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[7] ^
+ current_crc[1] ^ crc_in[1] ^ crc_in[7];
+ next_crc[6] = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[7] = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[8] = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[9] = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[10] = current_crc[18] ^ current_crc[2] ^ crc_in[2];
+ next_crc[11] = current_crc[19] ^ current_crc[3] ^ crc_in[3];
+ next_crc[12] = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[4] ^ crc_in[4];
+ next_crc[13] = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[14] = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[15] = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[16] = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4];
+ next_crc[17] = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[18] = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[19] = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[20] = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[21] = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[22] = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[23] = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[24] = current_crc[0] ^ crc_in[0] ^ current_crc[1] ^
+ crc_in[1] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[25] = current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[26] = current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[27] = current_crc[3] ^ crc_in[3] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[28] = current_crc[4] ^crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[29] = current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[30] = current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[31] = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ end // always
+
+assign rx_fcs[0] = current_crc[31];
+assign rx_fcs[1] = current_crc[30];
+assign rx_fcs[2] = current_crc[29];
+assign rx_fcs[3] = current_crc[28];
+assign rx_fcs[4] = current_crc[27];
+assign rx_fcs[5] = current_crc[26];
+assign rx_fcs[6] = current_crc[25];
+assign rx_fcs[7] = current_crc[24];
+assign rx_fcs[8] = current_crc[23];
+assign rx_fcs[9] = current_crc[22];
+assign rx_fcs[10] = current_crc[21];
+assign rx_fcs[11] = current_crc[20];
+assign rx_fcs[12] = current_crc[19];
+assign rx_fcs[13] = current_crc[18];
+assign rx_fcs[14] = current_crc[17];
+assign rx_fcs[15] = current_crc[16];
+assign rx_fcs[16] = current_crc[15];
+assign rx_fcs[17] = current_crc[14];
+assign rx_fcs[18] = current_crc[13];
+assign rx_fcs[19] = current_crc[12];
+assign rx_fcs[20] = current_crc[11];
+assign rx_fcs[21] = current_crc[10];
+assign rx_fcs[22] = current_crc[9];
+assign rx_fcs[23] = current_crc[8];
+assign rx_fcs[24] = current_crc[7];
+assign rx_fcs[25] = current_crc[6];
+assign rx_fcs[26] = current_crc[5];
+assign rx_fcs[27] = current_crc[4];
+assign rx_fcs[28] = current_crc[3];
+assign rx_fcs[29] = current_crc[2];
+assign rx_fcs[30] = current_crc[1];
+assign rx_fcs[31] = current_crc[0];
+
+ always @(rx_fcs)
+ begin
+ if (rx_fcs == 32'hc704dd7b)
+ crc_ok_ul = 1;
+ else
+ crc_ok_ul = 0;
+ end // always
+
+
+ assign rc2rf_crc_ok = crc_ok_ul;
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
trunk/rtl/gmac/crc32/g_rx_crc32.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/gmac/crc32/g_tx_crc32.v
===================================================================
--- trunk/rtl/gmac/crc32/g_tx_crc32.v (nonexistent)
+++ trunk/rtl/gmac/crc32/g_tx_crc32.v (revision 12)
@@ -0,0 +1,271 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Tubo 8051 cores MAC Interface Module ////
+//// ////
+//// This file is part of the Turbo 8051 cores project ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//// Description ////
+//// Turbo 8051 definitions. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+/***************************************************************
+ Description:
+ crc_32.v: This block contains the tx_crc32 generator.
+ CRC is generated on the tx data when gen_tx_crc asserted.
+ The 32-bit crc shift register is reset to all 1's when either
+ tx_reset_crc asserted
+
+ *********************************************************************/
+module g_tx_crc32 (
+ // List of outputs.
+ tx_fcs,
+
+ // List of inputs
+ gen_tx_crc,
+ tx_reset_crc,
+ tx_data,
+ sclk,
+ reset_n);
+
+ // defx[ine inputs and outputs.
+
+ input gen_tx_crc; // when asserted, crc is generated on the
+ // tx_data[3:0].
+ input tx_reset_crc; // when asserted, crc shift register is
+ // reset to all 1's. from link_phy_intfc.
+ input [7:0] tx_data; // trasnmit data.
+ input sclk; // serial clock from phy.
+ input reset_n; // global asynchronous reset.
+
+
+ output [31:0] tx_fcs; // 32-bit crc for tx_data. to link_phy_intfc.
+
+
+ // reg/wire declarations for primary outputs.
+ wire [31:0] tx_fcs;
+
+ // define constants and parameters here.
+
+ // define local signals here.
+
+ wire [7:0] crc_in;
+ wire gen_crc;
+ wire[7:0] tx_data_in;
+ wire carry0,carry1,carry2,carry3;
+ wire carry4,carry5,carry6,carry7;
+ reg [31:0] current_crc, next_crc;
+
+ // code starts here.
+ assign tx_data_in = tx_data;
+ assign crc_in = tx_data_in;
+
+ assign gen_crc = gen_tx_crc;
+
+ // 32-bit crc shift register for crc calculation.
+
+ always @(posedge sclk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else
+ begin
+ if (tx_reset_crc )
+ begin
+ current_crc <= 32'hffffffff;
+ end
+ else if (gen_crc) // generate crc
+ begin
+ current_crc <= next_crc;
+ end // else: !if(tx_reset_crc )
+ end // else: !if(reset_n)
+ end // always @ (posedge sclk or negedge reset_n)
+
+ // combinational logic to generate next_crc
+
+ always @(current_crc or crc_in)
+ begin
+
+ next_crc[0] = current_crc[8] ^ current_crc[2] ^ crc_in[2];
+ next_crc[1] = current_crc[9] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[3] ^ crc_in[3];
+ next_crc[2] = current_crc[10] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[4] ^
+ crc_in[4];
+ next_crc[3] = current_crc[11] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[4] = current_crc[12] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[3] ^ crc_in[3] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[5] = current_crc[13] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[7] ^
+ current_crc[1] ^ crc_in[1] ^ crc_in[7];
+ next_crc[6] = current_crc[14] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[7] = current_crc[15] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[8] = current_crc[16] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[9] = current_crc[17] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[10] = current_crc[18] ^ current_crc[2] ^ crc_in[2];
+ next_crc[11] = current_crc[19] ^ current_crc[3] ^ crc_in[3];
+ next_crc[12] = current_crc[20] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[4] ^ crc_in[4];
+ next_crc[13] = current_crc[21] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[5] ^
+ crc_in[5];
+ next_crc[14] = current_crc[22] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[15] = current_crc[23] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[16] = current_crc[24] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4];
+ next_crc[17] = current_crc[25] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[5] ^ crc_in[5];
+ next_crc[18] = current_crc[26] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[19] = current_crc[27] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[20] = current_crc[28] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[21] = current_crc[29] ^ current_crc[1] ^ crc_in[1] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[22] = current_crc[30] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6];
+ next_crc[23] = current_crc[31] ^ current_crc[0] ^ crc_in[0] ^
+ current_crc[1] ^ crc_in[1] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[24] = current_crc[0] ^ crc_in[0] ^ current_crc[1] ^
+ crc_in[1] ^ current_crc[2] ^ crc_in[2] ^
+ current_crc[4] ^ crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[25] = current_crc[1] ^ crc_in[1] ^ current_crc[2] ^
+ crc_in[2] ^ current_crc[3] ^ crc_in[3] ^
+ current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6];
+ next_crc[26] = current_crc[2] ^ crc_in[2] ^ current_crc[3] ^
+ crc_in[3] ^ current_crc[4] ^ crc_in[4] ^
+ current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[27] = current_crc[3] ^ crc_in[3] ^ current_crc[4] ^
+ crc_in[4] ^ current_crc[5] ^ crc_in[5] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[28] = current_crc[4] ^crc_in[4] ^ current_crc[5] ^
+ crc_in[5] ^ current_crc[6] ^ current_crc[0] ^
+ crc_in[0] ^ crc_in[6];
+ next_crc[29] = current_crc[5] ^ crc_in[5] ^ current_crc[6] ^
+ current_crc[0] ^ crc_in[0] ^ crc_in[6] ^
+ current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ next_crc[30] = current_crc[6] ^ current_crc[0] ^ crc_in[0] ^
+ crc_in[6] ^ current_crc[7] ^ current_crc[1] ^
+ crc_in[1] ^ crc_in[7];
+ next_crc[31] = current_crc[7] ^ current_crc[1] ^ crc_in[1] ^
+ crc_in[7];
+ end // always
+
+// assign tx_fcs = ~current_crc;
+ assign tx_fcs[0] = !current_crc[0];
+ assign tx_fcs[1] = !current_crc[1];
+ assign tx_fcs[2] = !current_crc[2];
+ assign tx_fcs[3] = !current_crc[3];
+ assign tx_fcs[4] = !current_crc[4];
+ assign tx_fcs[5] = !current_crc[5];
+ assign tx_fcs[6] = !current_crc[6];
+ assign tx_fcs[7] = !current_crc[7];
+ assign tx_fcs[8] = !current_crc[8];
+ assign tx_fcs[9] = !current_crc[9];
+ assign tx_fcs[10] = !current_crc[10];
+ assign tx_fcs[11] = !current_crc[11];
+ assign tx_fcs[12] = !current_crc[12];
+ assign tx_fcs[13] = !current_crc[13];
+ assign tx_fcs[14] = !current_crc[14];
+ assign tx_fcs[15] = !current_crc[15];
+ assign tx_fcs[16] = !current_crc[16];
+ assign tx_fcs[17] = !current_crc[17];
+ assign tx_fcs[18] = !current_crc[18];
+ assign tx_fcs[19] = !current_crc[19];
+ assign tx_fcs[20] = !current_crc[20];
+ assign tx_fcs[21] = !current_crc[21];
+ assign tx_fcs[22] = !current_crc[22];
+ assign tx_fcs[23] = !current_crc[23];
+ assign tx_fcs[24] = !current_crc[24];
+ assign tx_fcs[25] = !current_crc[25];
+ assign tx_fcs[26] = !current_crc[26];
+ assign tx_fcs[27] = !current_crc[27];
+ assign tx_fcs[28] = !current_crc[28];
+ assign tx_fcs[29] = !current_crc[29];
+ assign tx_fcs[30] = !current_crc[30];
+ assign tx_fcs[31] = !current_crc[31];
+
+endmodule
trunk/rtl/gmac/crc32/g_tx_crc32.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property