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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

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  • This comparison shows the changes necessary to convert path 
    /turbo8051
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/trunk/rtl/lib/wb_rd_mem2mem.v
195,7 → 195,9
reg wbo_cyc ;
reg mem_ack ;
 
wire mem_wr = wbo_ack;
wire mem_wr = wbo_ack;
// Generate Next Address, to fix the read to address inc issue
wire [15:0] taddr = mem_addr+1;
 
wire [7:0] mem_din = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
222,7 → 224,7
wbo_addr <= mem_addr[14:2];
wbo_stb <= 1'b1;
wbo_we <= 1'b0;
wbo_be <= {BE_WD{1'b1}};
wbo_be <= 1 << mem_addr[1:0];
wbo_cyc <= 1'b1;
mem_ack <= 1;
state <= TXFR;
232,7 → 234,8
mem_ack <= 0;
if(wbo_ack) begin
cnt <= cnt-1;
wbo_addr <= mem_addr[14:2];
wbo_addr <= taddr[14:2];
wbo_be <= 1 << taddr[1:0];
if(cnt == 1) begin
wbo_stb <= 1'b0;
wbo_cyc <= 1'b0;
/trunk/rtl/lib/wb_wr_mem2mem.v
179,8 → 179,9
reg [D_WD-1:0] wbo_din ;
reg state ;
 
wire mem_rd = wbo_ack;
reg mem_rd ;
 
 
always @(negedge rst_n or posedge clk) begin
if(rst_n == 0) begin
wbo_taddr <= 0;
190,6 → 191,7
wbo_be <= 0;
wbo_cyc <= 0;
wbo_din <= 0;
mem_rd <= 0;
state <= IDLE;
end
else begin
203,19 → 205,24
wbo_be <= 1 << mem_addr[1:0];
wbo_cyc <= 1;
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
mem_rd <= 1;
state <= XFR;
end
end
XFR: begin
if(wbo_ack) begin
wbo_addr <= mem_taddr;
wbo_addr <= mem_addr[14:2];
wbo_be <= 1 << mem_addr[1:0];
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
if(mem_aempty) begin
if(mem_aempty || mem_empty) begin
wbo_stb <= 1'b0;
wbo_cyc <= 0;
state <= IDLE;
end else begin
mem_rd <= 1;
end
end else begin
mem_rd <= 0;
end
end
endcase
/trunk/rtl/lib/dpath_ctrl.v
85,7 → 85,8
reg [15:0] rx_plen ;
reg [15:0] tx_plen ;
reg g_tx_mem_req ;
reg g_tx_mem_eop ;
 
wire g_tx_mem_eop = ((tx_plen +1) == g_tx_mem_req_length) ? 1'b1 : 1'b0;
 
always @(negedge rst_n or posedge clk) begin
94,7 → 95,6
g_tx_mem_addr <= 0;
rx_plen <= 0;
tx_plen <= 0;
g_tx_mem_eop <= 0;
end
else begin
//-----------------------------
103,7 → 103,7
if(g_rx_mem_rd) begin
g_rx_mem_addr <= g_rx_mem_addr+1;
if(g_rx_mem_eop) rx_plen <= 0;
rx_plen <= rx_plen +1;
else rx_plen <= rx_plen +1;
end
//------------------------
// Generate Tx Request at last transfer of RX Req
123,10 → 123,8
g_tx_mem_addr <= g_tx_mem_addr+1;
if(g_tx_mem_req_length == (tx_plen +1)) begin
tx_plen <= 0;
g_tx_mem_eop <= 1;
end else begin
tx_plen <= tx_plen +1;
g_tx_mem_eop <= 0;
end
end
end

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