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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

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  • This comparison shows the changes necessary to convert path
    /turbo8051
    from Rev 50 to Rev 51
    Reverse comparison

Rev 50 → Rev 51

/trunk/benchmark8051/verif/tb/oc8051_tb.v
344,6 → 344,7
$readmemb("./dat/oc8051_ea.in", ea);
 
 
`ifdef DEBUGGSY
initial begin
if ( $test$plusargs("DUMP") ) begin
$fsdbDumpfile("test_1.fsdb");
351,7 → 352,19
$fsdbDumpon;
end
end
`elsif SIGNALSCAN
initial begin
$shm_open("test_1.trn");
$shm_probe("AC",oc8051_tb);
end
`else
initial begin
$dumpfile("test_1.vcd");
$dumpvars(0,oc8051_tb);
end
 
`endif
 
 
 
endmodule
/trunk/benchmark8051/verif/sim/filelist_top.f
2,6 → 2,8
+incdir+../../rtl
+incdir+../tb
+define+OC8051_SIMULATION
+define+SIGNALSCAN
//+define+DEBUSSY
../tb/oc8051_tb.v
../tb/oc8051_xram.v
../tb/oc8051_uart_test.v
/trunk/benchmark8051/verif/sim/run_nc
0,0 → 1,139
#!/bin/csh -f
#
# testa all programs with oc8051 microcontroler
#
 
rm cds.lib hdl.var RUN_NC
rm nc*
rm -r INCA_libs
 
set failedi = 0;
set failedx = 0;
set all_testsi = 0;
set all_testsx = 0;
 
set internal_tests=(fib divmul sort gcd cast xram)
 
set external_tests=(fib divmul sort gcd cast xram)
 
# Prepare all .args files
iteration:
echo ""
echo ""
echo " preparing files"
echo ""
 
ncprep -f filelist_top.f > ../log/ncprep.log
 
if (`tail -1 ../log/ncprep.log | grep Failed` != "") then
echo ""
cat ../log/ncprep.log
exit
endif
 
# Run NC-Verilog compiler
echo ""
echo "\t@@@"
echo "\t@@@ Compiling sources"
echo "\t@@@"
 
ncvlog -NOCOPYRIGHT -f ncvlog.args > ../log/ncvlog.log
if ($status != 0) then
echo "\t@@@ FAILED"
echo ""
cat ../log/ncvlog.log
exit
else
echo "\t@@@ Passed"
endif
 
# Run the NC-Verilog elaborator (build the design hierarchy)
echo ""
echo "\t@@@"
echo "\t@@@ Building design hierarchy (elaboration)"
echo "\t@@@"
ncelab -access +r -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ../log/ncelab.log
if ($status != 0) then
echo "\t@@@ FAILED"
echo ""
cat ../log/ncelab.log
exit
else
echo "\t@@@ Passed"
endif
 
# Run the NC-Verilog simulator (simulate the design)
 
echo ""
echo "###########################################"
echo " Tesing programs from internal rom"
echo "###########################################"
 
cp ./dat/oc8051_eai.in ./dat/oc8051_ea.in
set i = 0;
echo "###########################################"
foreach internal_test ($internal_tests)
@ i += 1;
#echo ""
#echo "### Running test ${i}: ${internal_test}"
 
\cp ../tests/dat/${internal_test}.dat ./dat/oc8051_xrom.in
ncsim -NOCOPYRIGHT -f ncsim.args > ../log/ncsim.log
if ($status != 0) then
cat ../log/ncsim.log
exit
else if (`tail -100 ../log/ncsim.log | grep Passed` == "") then
echo "### test ${i}: ${internal_test} --> FAILED"
@ failedi += 1;
@ all_testsi += 1;
else
echo "### test ${i}: ${internal_test} --> PASSED"
@ all_testsi += 1;
endif
mv ../log/ncsim.log ../log/${internal_test}.log
 
 
end
echo "###########################################"
 
echo ""
echo ""
echo "###########################################"
echo "### tesing programs from external rom"
echo "###########################################"
 
\cp -rf ./dat/oc8051_eax.in ./dat/oc8051_ea.in
set i = 0;
echo "###########################################"
foreach external_test ($external_tests)
@ i += 1;
#echo ""
 
\cp ../tests/dat/${external_test}.dat ./dat/oc8051_xrom.in
ncsim -NOCOPYRIGHT -f ncsim.args > ../log/ncsim.log
if ($status != 0) then
cat ../log/ncsim.log
exit
else if (`tail -100 ../log/ncsim.log | grep Passed` == "") then
echo "### test ${i}: ${external_test} --> FAILED"
@ failedx += 1;
@ all_testsx += 1;
else
echo "### test ${i}: ${external_test} --> PASSED"
@ all_testsx += 1;
endif
mv ../log/ncsim.log ../log/x_${external_test}.log
 
end
echo "###########################################"
 
echo ""
echo "###########################################"
echo "### Test Summary "
echo "### "
echo "### Failed $failedi of $all_testsi internal tests"
echo "### Failed $failedx of $all_testsx external tests"
echo "###########################################"
 
 
trunk/benchmark8051/verif/sim/run_nc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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