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/tv80_docs.xml
0,0 → 1,242
<?xml version="1.0"?> |
<!DOCTYPE rfc SYSTEM "rfc2629.dtd"> |
<?rfc toc="yes"?> |
<?rfc private="$Revision: 1.5 $"?> |
<?rfc compact="yes"?> |
<rfc> |
<front> |
<title>tv80 Core Documentation</title> |
<author initials="G." surname="Hutchison" fullname="Guy Hutchison"> |
<organization>OpenCores.org</organization> |
<address> |
<email>ghutchis@opencores.org</email> |
</address> |
</author> |
<date month="October" year="2004" /> |
<area>General</area> |
<keyword>private</keyword> |
<keyword>XML</keyword> |
<keyword>Extensible Markup Language</keyword> |
<abstract><t> |
A synthesizable 8-bit microprocessor which is instruction-set compatable |
with the Z80, targetted at embedded and system-on-a-chip designs. |
</t></abstract> |
</front> |
<middle> |
<section title="Background"> |
<t>The tv80 core was created as a Verilog port of the <xref target="t80">VHDL T80 core</xref>, for use as a maintenence processor inside an ASIC. |
The tv80 has been modified since then for better synthesis |
timing/area results, and to incorporate several bug-fixes.</t> |
<t>The T80, and the tv80 derived from it, attempt to maintain the |
original cycle timings of the Z80, but have radically different |
internal designs and timings. With its target being ASIC and |
embedded applications, the tv80 does not attempt to maintain |
the original pinout of the Z80.</t> |
</section> |
|
<section title="Core Area and Technology Mapping"> |
<t> This section tracks synthesis results in various technologies. LSI 10K technology is |
used as a baseline because the library ships with Design Compiler. </t> |
<figure> |
<artwork> |
Component Clock Speed Area Technology (units) |
================ =========== ======== ===================== |
tv80 33 Mhz 10733 lsi_10k (gates) |
simple_gmii 33 Mhz 1247 lsi_10k (gates) |
</artwork> |
</figure> |
</section> |
|
<section title="TV80 Peripherals"> |
<t>The TV80 design includes a number (one, at this point) of peripherals. These peripherals |
are hardware-synthesizable, but may not be fully tested or functional.</t> |
<section title="Simple GMII Interface"> |
<t>This block presents a GMII interface on one side and a TV80 processor interface on |
the other. The processor-side controls are all mapped into I/O-space. The block |
can only process a single packet in each direction at one time. This is only really |
a limitation on the RX side, where any incoming packets will be dropped until the |
processor removes the first packet from the RX buffer.</t> |
<t>The GMII interface is signalling only, and does not support 10/100 operation, half duplex |
mode, flow control, or any other aspects of 802.3.</t> |
<section title="Register Interface"> |
<t>This block consumes 3 bits of I/O address space. The register addresses below are |
relative to the configurable base address of the block, which must be aligned to an |
8-byte boundary. Registers 0x6 and 0x7 are reserved.</t> |
<section title="Status Register (0x0)"> |
<t>Bit 0 of the status register indicates that a packet is available in the RX buffer. |
This bit will be cleared when the last byte of data is read out of the RX buffer.</t> |
<t>Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit |
will be cleared when the first byte of data of the next packet is written into the |
TX buffer.</t> |
<t>This register is read-only.</t> |
</section> |
<section title="Control Register (0x1)"> |
<t>Bit 0 controls sending packets. When a 1 is written to this bit, the data in |
the TX buffer will be sent as a single packet.</t> |
<t>This register is write-only.</t> |
</section> |
<section title="RX Length Register (Low, 0x2)"> |
<t>This register contains the low 8 bits of the length of the packet currently |
residing in the RX buffer.</t> |
<t>This register is read-only.</t> |
</section> |
<section title="RX Length Register (High, 0x3)"> |
<t>This register contains the high 8 bits of the length of the packet currently |
residing in the RX buffer.</t> |
<t>This register is read-only.</t> |
</section> |
<section title="RX Data Register (0x4)"> |
<t>This register contains the next byte of data in the RX packet buffer.</t> |
<t>This register is read-only.</t> |
</section> |
<section title="TX Data Register (0x5)"> |
<t>Writing to this register puts data in the TX packet buffer. This register does |
not perform bounds checking; it is the program's responsibility not to write more |
data than the size of the TX buffer.</t> |
<t>This register is write-only.</t> |
</section> |
</section> |
</section> |
</section> |
<section title="Verification Environment"> |
<section title="Memory Map"> |
<t> |
Environment memory space is divided into a 32k ROM region and a 32k RAM |
region, as follows: |
|
<figure> |
<artwork> |
0000-7FFF: ROM |
8000-FFFF: RAM |
</artwork> |
</figure> |
|
<t>Environment I/O space is allocated as follows:</t> |
|
<figure> |
<artwork> |
00-0F: Unused |
10-1F: Test devices |
20-7F: Unused |
80-9F: Environment control |
A0-FF: Unused |
</artwork></figure> |
</t> |
</section> |
<section title="Control Registers"> |
The tv80 environment is controlled by the program under simulation. The |
program can affect the environment through a set of control registers, |
which are mapped into I/O space. |
|
<section title="Simulation control (0x80)"> |
|
<list style="symbols"> |
<t> Write '01' to end simulation with test passed</t> |
<t> Write '02' to end with test failed</t> |
<t> Write '03' to turn on dumping</t> |
<t> Write '04' to turn off dumping</t> |
</list> |
</section> |
|
<section title="Message output (0x81)"> |
<t> |
Write characters to this port one at a time. When the |
newline ('\n', ASCII 0x0A) character is written, the |
environment will print out the collected string. |
</t> |
</section> |
<section title="Timeout control (0x82)"> |
<t> |
Bit[0] enables the timeout counter, |
Bit[1] resets the counter to 0. |
Timeout counter defaults to enabled at simulation start. |
</t> |
</section> |
|
<section title="Max timeout (0x84, 0x83)"> |
<t> |
Holds 16-bit timeout value (amount of time in clocks before |
timeout error occurs). |
</t> |
</section> |
<section title="Interrupt countdown (0x90)"> |
<t> |
When set, starts a countdown (in clocks) until assertion of |
the INT_N signal. |
</t> |
</section> |
<section title="Checksum value (0x91)"> |
<t>This register holds the checksum value of all data |
written to the accumulate register. The checksum is a simple |
twos-complement checksum, so it can be compared with a CPU-generated |
checksum.</t> |
<t>This register is readable and writeable. Writing the register sets |
the current checksum value.</t> |
</section> |
<section title="Checksum accumulate (0x92)"> |
<t>This write-only register adds the written value to the value |
contained in the Checksum Value register.</t> |
</section> |
<section title="Increment on read (0x93)"> |
<t>This register increments every time it is read, so reading it |
repeatedly generates an incrementing sequence. It can be reset |
by writing it to a new starting value.</t> |
</section> |
|
</section> |
<section title="Tool Chain"> |
<t>The minimum toolchain required to simulate the tv80 is the |
<xref target="cver">CVer</xref> Verilog simulator, and the |
<xref target="sdcc">SDCC</xref> compiler/assembler/linker. In |
addition, to run the <xref target="tvs80">tvs80</xref> instruction |
test suite, the <xref target="dosbox">DOSBox</xref> DOS emulator |
is required. |
</t> |
</section> |
<section title="Tests"> |
<t>Most of the tests in the tv80 environment are written in C, and should |
be compiled with the <xref target="sdcc">sdcc</xref> compiler. |
</t> |
<section anchor="tvs80" title="tvs80 test"> |
<t>The tvs80 test is different than the rest of the tests, and is |
written in its own flavor of assembly language. This test provides |
a fairly comprehensive Z80 instruction test.</t> |
<t>The assembler for this test only runs under DOS. To assemble |
under Unix/Linux, the <xref target="dosbox">"dosbox" DOS emulator</xref> is required. A script |
to run the assembler under dosbox, as well as the tvs80.asm source, |
is checked in under the "tests/tvs80" directory.</t> |
</section> |
</section> |
</section> |
</middle> |
<back> |
<references> |
<reference anchor="t80" target="http://www.opencores.org/projects.cgi/web/t80/overview"> |
<front> |
<title>VHDL T80 Core</title> |
<author initials="D." surname="Wallner" fullname="Daniel Wallner"> |
<organization>OpenCores.org</organization> |
</author> |
</front> |
</reference> |
<reference anchor="sdcc" target="http://sdcc.sourceforge.net"> |
<front> |
<title>Small Device C Compiler</title> |
</front> |
</reference> |
<reference anchor="cver" target="http://www.pragmatic-c.com/gpl-cver"> |
<front> |
<title>GPL Cver Simulator</title> |
<author initials="A." surname="Vanvick" fullname="Andrew Vanvick"> |
<organization>Pragmatic C Software</organization> |
</author> |
</front> |
</reference> |
<reference anchor="dosbox" target="http://dosbox.sourceforge.net"> |
<front> |
<title>DOSBox</title> |
</front> |
</reference> |
</references> |
</back> |
</rfc> |
/tv80_docs.html
0,0 → 1,413
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1"> |
<tr><td class="header">$Revision: 1.3 $</td><td class="header">G. Hutchison</td></tr> |
<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr> |
<tr><td class="header"> </td><td class="header">October 2004</td></tr> |
</table></td></tr></table> |
<div align="right"><span class="title"><br />tv80 Core Documentation</span></div> |
|
<h3>Abstract</h3> |
|
<p> |
A synthesizable 8-bit microprocessor which is instruction-set compatable |
with the Z80, targetted at embedded and system-on-a-chip designs. |
|
</p><a name="toc"></a><br /><hr /> |
<h3>Table of Contents</h3> |
<p class="toc"> |
<a href="#anchor1">1.</a> |
Background<br /> |
<a href="#anchor2">2.</a> |
Core Area and Technology Mapping<br /> |
<a href="#anchor3">3.</a> |
TV80 Peripherals<br /> |
<a href="#anchor4">3.1</a> |
Simple GMII Interface<br /> |
<a href="#anchor5">3.1.1</a> |
Register Interface<br /> |
<a href="#anchor12">4.</a> |
Verification Environment<br /> |
<a href="#anchor13">4.1</a> |
Memory Map<br /> |
<a href="#anchor14">4.2</a> |
Control Registers<br /> |
<a href="#anchor15">4.2.1</a> |
Simulation control (0x80)<br /> |
<a href="#anchor16">4.2.2</a> |
Message output (0x81)<br /> |
<a href="#anchor17">4.2.3</a> |
Timeout control (0x82)<br /> |
<a href="#anchor18">4.2.4</a> |
Max timeout (0x84, 0x83)<br /> |
<a href="#anchor19">4.2.5</a> |
Interrupt countdown (0x90)<br /> |
<a href="#anchor20">4.2.6</a> |
Checksum value (0x91)<br /> |
<a href="#anchor21">4.2.7</a> |
Checksum accumulate (0x92)<br /> |
<a href="#anchor22">4.2.8</a> |
Increment on read (0x93)<br /> |
<a href="#anchor23">4.3</a> |
Tool Chain<br /> |
<a href="#anchor24">4.4</a> |
Tests<br /> |
<a href="#tvs80">4.4.1</a> |
tvs80 test<br /> |
<a href="#rfc.references1">5.</a> |
References<br /> |
<a href="#rfc.authors">§</a> |
Author's Address<br /> |
</p> |
<br clear="all" /> |
|
<a name="anchor1"></a><br /><hr /> |
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<a name="rfc.section.1"></a><h3>1. Background</h3> |
|
<p>The tv80 core was created as a Verilog port of the <a class="info" href="#t80">VHDL T80 core<span>Wallner, D., VHDL T80 Core, .</span></a>[1], for use as a maintenence processor inside an ASIC. |
The tv80 has been modified since then for better synthesis |
timing/area results, and to incorporate several bug-fixes. |
</p> |
<p>The T80, and the tv80 derived from it, attempt to maintain the |
original cycle timings of the Z80, but have radically different |
internal designs and timings. With its target being ASIC and |
embedded applications, the tv80 does not attempt to maintain |
the original pinout of the Z80. |
</p> |
<a name="anchor2"></a><br /><hr /> |
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<a name="rfc.section.2"></a><h3>2. Core Area and Technology Mapping</h3> |
|
<p> This section tracks synthesis results in various technologies. LSI 10K technology is |
used as a baseline because the library ships with Design Compiler. |
</p><pre> |
Component Clock Speed Area Technology (units) |
================ =========== ======== ===================== |
tv80 33 Mhz 10733 lsi_10k (gates) |
simple_gmii 33 Mhz 1247 lsi_10k (gates) |
</pre> |
|
<a name="anchor3"></a><br /><hr /> |
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<a name="rfc.section.3"></a><h3>3. TV80 Peripherals</h3> |
|
<p>The TV80 design includes a number (one, at this point) of peripherals. These peripherals |
are hardware-synthesizable, but may not be fully tested or functional. |
</p> |
<a name="rfc.section.3.1"></a><h4><a name="anchor4">3.1</a> Simple GMII Interface</h4> |
|
<p>This block presents a GMII interface on one side and a TV80 processor interface on |
the other. The processor-side controls are all mapped into I/O-space. The block |
can only process a single packet in each direction at one time. This is only really |
a limitation on the RX side, where any incoming packets will be dropped until the |
processor removes the first packet from the RX buffer. |
</p> |
<p>The GMII interface is signalling only, and does not support 10/100 operation, half duplex |
mode, flow control, or any other aspects of 802.3. |
</p> |
<a name="rfc.section.3.1.1"></a><h4><a name="anchor5">3.1.1</a> Register Interface</h4> |
|
<p>This block consumes 3 bits of I/O address space. The register addresses below are |
relative to the configurable base address of the block, which must be aligned to an |
8-byte boundary. Registers 0x6 and 0x7 are reserved. |
</p> |
<a name="rfc.section.3.1.1.1"></a><h4><a name="anchor6">3.1.1.1</a> Status Register (0x0)</h4> |
|
<p>Bit 0 of the status register indicates that a packet is available in the RX buffer. |
This bit will be cleared when the last byte of data is read out of the RX buffer. |
</p> |
<p>Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit |
will be cleared when the first byte of data of the next packet is written into the |
TX buffer. |
</p> |
<p>This register is read-only. |
</p> |
<a name="rfc.section.3.1.1.2"></a><h4><a name="anchor7">3.1.1.2</a> Control Register (0x1)</h4> |
|
<p>Bit 0 controls sending packets. When a 1 is written to this bit, the data in |
the TX buffer will be sent as a single packet. |
</p> |
<p>This register is write-only. |
</p> |
<a name="rfc.section.3.1.1.3"></a><h4><a name="anchor8">3.1.1.3</a> RX Length Register (Low, 0x2)</h4> |
|
<p>This register contains the low 8 bits of the length of the packet currently |
residing in the RX buffer. |
</p> |
<p>This register is read-only. |
</p> |
<a name="rfc.section.3.1.1.4"></a><h4><a name="anchor9">3.1.1.4</a> RX Length Register (High, 0x3)</h4> |
|
<p>This register contains the high 8 bits of the length of the packet currently |
residing in the RX buffer. |
</p> |
<p>This register is read-only. |
</p> |
<a name="rfc.section.3.1.1.5"></a><h4><a name="anchor10">3.1.1.5</a> RX Data Register (0x4)</h4> |
|
<p>This register contains the next byte of data in the RX packet buffer. |
</p> |
<p>This register is read-only. |
</p> |
<a name="rfc.section.3.1.1.6"></a><h4><a name="anchor11">3.1.1.6</a> TX Data Register (0x5)</h4> |
|
<p>Writing to this register puts data in the TX packet buffer. This register does |
not perform bounds checking; it is the program's responsibility not to write more |
data than the size of the TX buffer. |
</p> |
<p>This register is write-only. |
</p> |
<a name="anchor12"></a><br /><hr /> |
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<a name="rfc.section.4"></a><h3>4. Verification Environment</h3> |
|
<a name="rfc.section.4.1"></a><h4><a name="anchor13">4.1</a> Memory Map</h4> |
|
<p> |
Environment memory space is divided into a 32k ROM region and a 32k RAM |
region, as follows: |
|
</p> |
<pre> |
0000-7FFF: ROM |
8000-FFFF: RAM |
</pre> |
<p> |
|
<p>Environment I/O space is allocated as follows: |
</p><pre> |
00-0F: Unused |
10-1F: Test devices |
20-7F: Unused |
80-9F: Environment control |
A0-FF: Unused |
</pre> |
|
|
<a name="rfc.section.4.2"></a><h4><a name="anchor14">4.2</a> Control Registers</h4> |
|
<a name="rfc.section.4.2.1"></a><h4><a name="anchor15">4.2.1</a> Simulation control (0x80)</h4> |
|
<ul class="text"> |
<li> Write '01' to end simulation with test passed |
</li> |
<li> Write '02' to end with test failed |
</li> |
<li> Write '03' to turn on dumping |
</li> |
<li> Write '04' to turn off dumping |
</li> |
</ul> |
<a name="rfc.section.4.2.2"></a><h4><a name="anchor16">4.2.2</a> Message output (0x81)</h4> |
|
<p> |
Write characters to this port one at a time. When the |
newline ('\n', ASCII 0x0A) character is written, the |
environment will print out the collected string. |
|
</p> |
<a name="rfc.section.4.2.3"></a><h4><a name="anchor17">4.2.3</a> Timeout control (0x82)</h4> |
|
<p> |
Bit[0] enables the timeout counter, |
Bit[1] resets the counter to 0. |
Timeout counter defaults to enabled at simulation start. |
|
</p> |
<a name="rfc.section.4.2.4"></a><h4><a name="anchor18">4.2.4</a> Max timeout (0x84, 0x83)</h4> |
|
<p> |
Holds 16-bit timeout value (amount of time in clocks before |
timeout error occurs). |
|
</p> |
<a name="rfc.section.4.2.5"></a><h4><a name="anchor19">4.2.5</a> Interrupt countdown (0x90)</h4> |
|
<p> |
When set, starts a countdown (in clocks) until assertion of |
the INT_N signal. |
|
</p> |
<a name="rfc.section.4.2.6"></a><h4><a name="anchor20">4.2.6</a> Checksum value (0x91)</h4> |
|
<p>This register holds the checksum value of all data |
written to the accumulate register. The checksum is a simple |
twos-complement checksum, so it can be compared with a CPU-generated |
checksum. |
</p> |
<p>This register is readable and writeable. Writing the register sets |
the current checksum value. |
</p> |
<a name="rfc.section.4.2.7"></a><h4><a name="anchor21">4.2.7</a> Checksum accumulate (0x92)</h4> |
|
<p>This write-only register adds the written value to the value |
contained in the Checksum Value register. |
</p> |
<a name="rfc.section.4.2.8"></a><h4><a name="anchor22">4.2.8</a> Increment on read (0x93)</h4> |
|
<p>This register increments every time it is read, so reading it |
repeatedly generates an incrementing sequence. It can be reset |
by writing it to a new starting value. |
</p> |
<a name="rfc.section.4.3"></a><h4><a name="anchor23">4.3</a> Tool Chain</h4> |
|
<p>The minimum toolchain required to simulate the tv80 is the |
<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the |
<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In |
addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction |
test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator |
is required. |
|
</p> |
<a name="rfc.section.4.4"></a><h4><a name="anchor24">4.4</a> Tests</h4> |
|
<p>Most of the tests in the tv80 environment are written in C, and should |
be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler. |
|
</p> |
<a name="rfc.section.4.4.1"></a><h4><a name="tvs80">4.4.1</a> tvs80 test</h4> |
|
<p>The tvs80 test is different than the rest of the tests, and is |
written in its own flavor of assembly language. This test provides |
a fairly comprehensive Z80 instruction test. |
</p> |
<p>The assembler for this test only runs under DOS. To assemble |
under Unix/Linux, the <a class="info" href="#dosbox">"dosbox" DOS emulator<span>, DOSBox, .</span></a>[4] is required. A script |
to run the assembler under dosbox, as well as the tvs80.asm source, |
is checked in under the "tests/tvs80" directory. |
</p> |
<a name="rfc.references1"></a><br /><hr /> |
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<h3>5 References</h3> |
<table width="99%" border="0"> |
<tr><td class="author-text" valign="top"><a name="t80">[1]</a></td> |
<td class="author-text">Wallner, D., "<a href="http://www.opencores.org/projects.cgi/web/t80/overview">VHDL T80 Core</a>".</td></tr> |
<tr><td class="author-text" valign="top"><a name="sdcc">[2]</a></td> |
<td class="author-text">"<a href="http://sdcc.sourceforge.net">Small Device C Compiler</a>".</td></tr> |
<tr><td class="author-text" valign="top"><a name="cver">[3]</a></td> |
<td class="author-text">Vanvick, A., "<a href="http://www.pragmatic-c.com/gpl-cver">GPL Cver Simulator</a>".</td></tr> |
<tr><td class="author-text" valign="top"><a name="dosbox">[4]</a></td> |
<td class="author-text">"<a href="http://dosbox.sourceforge.net">DOSBox</a>".</td></tr> |
</table> |
|
<a name="rfc.authors"></a><br /><hr /> |
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table> |
<h3>Author's Address</h3> |
<table width="99%" border="0" cellpadding="0" cellspacing="0"> |
<tr><td class="author-text"> </td> |
<td class="author-text">Guy Hutchison</td></tr> |
<tr><td class="author-text"> </td> |
<td class="author-text">OpenCores.org</td></tr> |
<tr><td class="author" align="right">EMail: </td> |
<td class="author-text"><a href="mailto:ghutchis@opencores.org">ghutchis@opencores.org</a></td></tr> |
</table> |
</body></html> |
/env_io_map.txt
0,0 → 1,52
|
================================================== |
TV80 Microprocessor Core Environment Documentation |
================================================== |
|
Environment Memory Map: |
|
Environment memory space is divided into a 32k ROM region and a 32k RAM |
region, as follows: |
|
0000-7FFF: ROM |
8000-FFFF: RAM |
|
Environment I/O space is allocated as follows: |
|
00-0F: Unused |
10-1F: Test devices |
20-7F: Unused |
80-8F: Environment control |
A0-FF: Unused |
|
The Environment control registers are: |
|
80 : Simulation control |
|
Write '01' to end simulation with test passed |
Write '02' to end with test failed |
Write '03' to turn on dumping |
Write '04' to turn off dumping |
|
81 : Message output |
|
Write characters to this port one at a time. When the |
newline ('\n', ASCII 0x0A) character is written, the |
environment will print out the collected string. |
|
82 : Timeout control |
|
Bit[0] enables the timeout counter |
Bit[1] resets the counter to 0 |
Timeout counter defaults to enabled at simulation start |
|
83 : Max timeout [low] |
84 : Max timeout [high] |
|
Holds 16-bit timeout value (amount of time in clocks before |
timeout error occurs). |
|
90 : Interrupt countdown |
|
When set, starts a countdown (in clocks) until assertion of |
the INT_N signal. |