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URL https://opencores.org/ocsvn/tv80/tv80/trunk

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  • This comparison shows the changes necessary to convert path 
    /tv80/trunk/env
    from Rev 84 to Rev 89
    ↔ Reverse comparison
  •

Rev 84 → Rev 89

/tb.vf
7,6 → 7,7
*
*/
 
env/tb_top.v
rtl/core/tv80_alu.v
rtl/core/tv80_mcode.v
rtl/core/tv80_reg.v
18,7 → 19,6
rtl/simple_gmii/sync2.v
rtl/simple_gmii/ram_1r_1w.v
rtl/uart/T16450.v
env/tb_top.v
env/env_io.v
env/op_decode.v
env/async_mem.v
/env_tasks.v
23,8 → 23,13
begin
if (!dumping)
begin
`ifdef VCS
$vcdpluson;
$vcdplusmemon;
`else
$dumpfile (`DUMPFILE_NAME);
$dumpvars;
`endif
dumping = 1;
end
end
32,7 → 37,12
 
task dumpoff;
begin
`ifdef VCS
$vcdplusoff;
$vcdplusmemoff;
`else
// ???
`endif
end
endtask // dumpoff
 
/env_io.v
1,9 → 1,9
 
module env_io (/*AUTOARG*/
// Outputs
DI,
// Inouts
DI,
// Inputs
clk, iorq_n, rd_n, wr_n, addr, DO
clk, iorq_n, rd_n, wr_n, addr, D_OUT
);
input clk;
11,7 → 11,7
input rd_n;
input wr_n;
input [7:0] addr;
input [7:0] DO;
input [7:0] D_OUT;
inout [7:0] DI;
 
reg [7:0] io_data;
25,8 → 25,10
reg [15:0] max_timeout;
 
reg [7:0] int_countdown;
reg [7:0] nmi_countdown;
reg [7:0] checksum;
reg [7:0] ior_value; // increment-on-read value
reg [7:0] nmi_trigger; // trigger nmi when IR = this value
assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
 
38,6 → 40,8
max_timeout = 10000;
timeout_ctl = 1;
int_countdown = 0;
nmi_countdown = 0;
nmi_trigger = 0;
end
 
always @*
55,6 → 59,8
8'h91 : io_data = checksum;
8'h93 : io_data = ior_value;
8'h94 : io_data = {$random};
8'h95 : io_data = nmi_countdown[7:0];
8'hA0 : io_data = nmi_trigger;
default : io_data = 8'hzz;
endcase // case(addr)
end // if (!iorq_n & !rd_n)
72,10 → 78,18
case (addr)
8'h80 :
begin
case (DO)
1 : tb_top.test_pass;
case (D_OUT)
1 :
begin
$writememh ("test_output2.hex", tb_top.rom.mem);
tb_top.test_pass;
end
 
2 : tb_top.test_fail;
2 :
begin
$writememh ("test_output2.hex", tb_top.rom.mem);
tb_top.test_fail;
end
 
3 : tb_top.dumpon;
 
83,18 → 97,18
 
default :
begin
$display ("%t: ERROR : Unknown I/O command %x", $time, DO);
$display ("%t: ERROR : Unknown I/O command %x", $time, D_OUT);
end
endcase // case(DO)
endcase // case(D_OUT)
end // case: :...
 
8'h81 :
begin
str_buf[buf_ptr] = DO;
str_buf[buf_ptr] = D_OUT;
buf_ptr = buf_ptr + 1;
 
//$display ("%t: DEBUG : Detected write of character %x", $time, DO);
if (DO == 8'h0A)
//$display ("%t: DEBUG : Detected write of character %x", $time, D_OUT);
if (D_OUT == 8'h0A)
begin
$write ("%t: PROGRAM : ", $time);
 
107,16 → 121,18
 
8'h82 :
begin
timeout_ctl = DO;
timeout_ctl = D_OUT;
end
 
8'h83 : max_timeout[7:0] = DO;
8'h84 : max_timeout[15:8] = DO;
8'h83 : max_timeout[7:0] = D_OUT;
8'h84 : max_timeout[15:8] = D_OUT;
 
8'h90 : int_countdown = DO;
8'h91 : checksum = DO;
8'h92 : checksum = checksum + DO;
8'h93 : ior_value = DO;
8'h90 : int_countdown = D_OUT;
8'h91 : checksum = D_OUT;
8'h92 : checksum = checksum + D_OUT;
8'h93 : ior_value = D_OUT;
8'h95 : nmi_countdown[7:0] = D_OUT;
8'hA0 : nmi_trigger = D_OUT;
endcase // case(addr)
end // always @ (posedge clk)
 
136,10 → 152,14
 
always @(posedge clk)
begin
if (int_countdown == 1)
if (int_countdown == 0)
begin
tb_top.int_n <= #1 1'b1;
end
else if (int_countdown == 1)
begin
tb_top.int_n <= #1 1'b0;
int_countdown = 0;
//int_countdown = 0;
end
else if (int_countdown > 1)
begin
146,6 → 166,36
int_countdown = int_countdown - 1;
tb_top.int_n <= #1 1'b1;
end
 
// when nmi countdown reaches 1, an NMI will be issued.
// to clear the interrupt, write nmi_countdown to 0.
if ((nmi_countdown == 0) && (nmi_trigger == 0))
begin
tb_top.nmi_n <= #1 1'b1;
end
else if (nmi_countdown == 1)
begin
tb_top.nmi_n <= #1 1'b0;
end
else if (nmi_countdown > 1)
begin
nmi_countdown = nmi_countdown - 1;
tb_top.nmi_n <= #1 1'b1;
end
 
// when IR equals the target instruction, an NMI will be
// issued. To clear the interrupt, write nmi_trigger to
// zero.
if (nmi_trigger != 0)
begin
if (nmi_trigger === tb_top.tv80s_inst.i_tv80_core.IR[7:0])
begin
tb_top.nmi_n <= #80 0;
tb_top.nmi_n <= #160 1;
end
end
else if (nmi_countdown == 0)
tb_top.nmi_n <= #1 1;
end
endmodule // env_io
/tb_top.v
1,3 → 1,4
`timescale 1ns/100ps
`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core
 
module tb_top;
18,7 → 19,7
wire busak_n;
wire [15:0] A;
wire [7:0] di;
wire [7:0] do;
wire [7:0] d_out;
wire ram_rd_cs, ram_wr_cs, rom_rd_cs;
reg tx_clk;
54,7 → 55,7
.halt_n (halt_n),
.busak_n (busak_n),
.A (A[15:0]),
.do (do[7:0]),
.dout (d_out[7:0]),
// Inputs
.reset_n (reset_n),
.clk (clk),
70,7 → 71,7
.rd_data (di),
// Inputs
.wr_clk (clk),
.wr_data (do),
.wr_data (d_out),
.wr_cs (ram_wr_cs),
.addr (A[14:0]),
.rd_cs (ram_rd_cs));
96,7 → 97,7
.rd_n (rd_n),
.wr_n (wr_n),
.addr (A[7:0]),
.DO (do[7:0]));
.D_OUT (d_out[7:0]));
 
//----------------------------------------------------------------------
// UART
105,7 → 106,7
wire uart_cs_n;
wire [7:0] uart_rd_data;
 
wire sin;
wire ser_in;
wire cts_n;
wire dsr_n;
wire ri_n;
123,7 → 124,7
assign uart_cs_n = ~(!iorq_n & (A[7:3] == 5'h3));
assign di = (!uart_cs_n & !rd_n) ? uart_rd_data : 8'bz;
assign sin = sout;
assign ser_in = sout;
 
T16450 uart0
(.reset_n (reset_n),
133,9 → 134,9
.rd_n (rd_n),
.wr_n (wr_n),
.addr (A[2:0]),
.wr_data (do),
.wr_data (d_out),
.rd_data (uart_rd_data),
.sin (sin),
.sin (ser_in),
.cts_n (cts_n),
.dsr_n (dsr_n),
.ri_n (ri_n),
190,7 → 191,7
.rd_n (rd_n),
.wr_n (wr_n),
.addr (A[15:0]),
.wr_data (do));
.wr_data (d_out));
//----------------------------------------------------------------------
// Global Initialization

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