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URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /tv80/trunk/tests
    from Rev 84 to Rev 89
    ↔ Reverse comparison
  •

Rev 84 → Rev 89

/bintr_crt0.asm
2,6 → 2,7
.module bintr_crt0
.globl _main
.globl _isr
.globl _nmi_isr
 
.area _HEADER (ABS)
;; Reset vector
22,10 → 23,18
reti
.org 0x38
di
push af
call _isr
pop af
ei
reti
.org 0x66
push af
call _nmi_isr
pop af
retn
.org 0x100
init:
;; Stack at the top of memory.
/tv80_env.h
38,6 → 38,8
sfr at 0x92 cksum_accum;
sfr at 0x93 inc_on_read;
sfr at 0x94 randval;
sfr at 0x95 nmi_cntdwn;
sfr at 0xA0 nmi_trig_opcode;
 
#define SC_TEST_PASSED 0x01
#define SC_TEST_FAILED 0x02
/bintr.c
15,17 → 15,78
unsigned char foo;
volatile unsigned char test_pass;
static unsigned char triggers;
int phase;
char done;
char nmi_trig;
 
void nmi_isr (void)
{
nmi_trig++;
 
switch (phase) {
// nmi test
case 1 :
if (nmi_trig > 5) {
phase += 1;
nmi_trig = 0;
//intr_cntdwn = 255;
//intr_cntdwn = 0;
intr_cntdwn = 32;
nmi_cntdwn = 0;
} else
nmi_cntdwn = 32;
break;
 
// just trigger once, and disable interrupt
case 3 :
nmi_cntdwn = 0;
nmi_trig_opcode = 0; // pop AF opcode
break;
}
}
 
void isr (void)
{
int i;
triggers++;
 
if (triggers > 5) {
test_pass = 1;
intr_cntdwn = 255;
switch (phase) {
// int test
case 0 :
if (triggers > 5) {
phase += 1;
triggers = 0;
intr_cntdwn = 0;
nmi_cntdwn = 64;
} else {
intr_cntdwn = 32;
}
break;
 
 
// int / nmi interaction
// in this phase set up interrupt call
// which will be interrupted by an nmi
case 2 :
phase += 1;
triggers = 0;
nmi_trig = 0;
intr_cntdwn = 20;
nmi_trig_opcode = 0xF1; // pop AF opcode
 
break;
 
// wait for a while while servicing interrupt
// nmi should interrupt us and increment nmi_trig
// if test pass is true when we are done then exit
case 3 :
intr_cntdwn = 0;
} else
intr_cntdwn = 32;
if (nmi_trig == 1)
test_pass = 1;
break;
}
}
 
int main ()
35,12 → 96,19
 
test_pass = 0;
triggers = 0;
nmi_trig = 0;
 
phase = 0;
 
// start interrupt countdown
intr_cntdwn = 64;
set_timeout (50000);
 
for (i=0; i<200; i++)
for (i=0; i<1024; i++) {
if (test_pass)
break;
check = sim_ctl_port;
}
 
if (test_pass)
sim_ctl (SC_TEST_PASSED);
/Makefile
15,12 → 15,14
 
%.ihx : %.c
$(CC) $^
rm -f $*.asm
 
%.o : %.asm
$(AS) -o $*.o $^
$(AS) -l -o $*.o $^
 
%.ihx : %.o
$(LD) $(LINK_OPTIONS) $(AS_LINK_OPTIONS) -i $* $^ -e
#$(LD) $(LINK_OPTIONS) $(AS_LINK_OPTIONS) -i $* $^ -e
$(CC) $^ --no-std-crt0 bintr_crt0.o
 
bintr.ihx : bintr.c bintr_crt0.o
$(CC) --no-std-crt0 bintr.c bintr_crt0.o

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