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  • This comparison shows the changes necessary to convert path 
    /tv80/trunk
    from Rev 89 to Rev 90
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  •

Rev 89 → Rev 90

/rtl/core/tv80_alu.v
58,7 → 58,7
input Sub;
input Carry_In;
begin
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
end
endfunction // AddSub4
68,7 → 68,7
input Sub;
input Carry_In;
begin
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
end
endfunction // AddSub4
 
78,7 → 78,7
input Sub;
input Carry_In;
begin
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
end
endfunction // AddSub4
 
/rtl/core/tv80_mcode.v
162,16 → 162,16
// constant aZI : std_logic_vector[2:0] = 3'b110;
 
function is_cc_true;
input [7:0] F;
input [7:0] FF;
input [2:0] cc;
begin
if (Mode == 3 )
begin
case (cc)
3'b000 : is_cc_true = F[7] == 1'b0; // NZ
3'b001 : is_cc_true = F[7] == 1'b1; // Z
3'b010 : is_cc_true = F[4] == 1'b0; // NC
3'b011 : is_cc_true = F[4] == 1'b1; // C
3'b000 : is_cc_true = FF[7] == 1'b0; // NZ
3'b001 : is_cc_true = FF[7] == 1'b1; // Z
3'b010 : is_cc_true = FF[4] == 1'b0; // NC
3'b011 : is_cc_true = FF[4] == 1'b1; // C
3'b100 : is_cc_true = 0;
3'b101 : is_cc_true = 0;
3'b110 : is_cc_true = 0;
181,14 → 181,14
else
begin
case (cc)
3'b000 : is_cc_true = F[6] == 1'b0; // NZ
3'b001 : is_cc_true = F[6] == 1'b1; // Z
3'b010 : is_cc_true = F[0] == 1'b0; // NC
3'b011 : is_cc_true = F[0] == 1'b1; // C
3'b100 : is_cc_true = F[2] == 1'b0; // PO
3'b101 : is_cc_true = F[2] == 1'b1; // PE
3'b110 : is_cc_true = F[7] == 1'b0; // P
3'b111 : is_cc_true = F[7] == 1'b1; // M
3'b000 : is_cc_true = FF[6] == 1'b0; // NZ
3'b001 : is_cc_true = FF[6] == 1'b1; // Z
3'b010 : is_cc_true = FF[0] == 1'b0; // NC
3'b011 : is_cc_true = FF[0] == 1'b1; // C
3'b100 : is_cc_true = FF[2] == 1'b0; // PO
3'b101 : is_cc_true = FF[2] == 1'b1; // PE
3'b110 : is_cc_true = FF[7] == 1'b0; // P
3'b111 : is_cc_true = FF[7] == 1'b1; // M
endcase
end
end
270,9 → 270,9
//
//----------------------------------------------------------------------------
 
casex (IR)
casez (IR)
// 8 BIT LOAD GROUP
8'b01xxxxxx :
8'b01zzzzzz :
begin
if (IR[5:0] == 6'b110110)
Halt = 1'b1;
308,9 → 308,9
Set_BusA_To[2:0] = DDD;
Read_To_Reg = 1'b1;
end // else: !if(IR[5:3] == 3'b110)
end // case: 8'b01xxxxxx
end // case: 8'b01zzzzzz
 
8'b00xxx110 :
8'b00zzz110 :
begin
if (IR[5:3] == 3'b110)
begin
623,7 → 623,7
LDSPHL = 1'b1;
end
8'b11xx0101 :
8'b11zz0101 :
begin
// PUSH qq
MCycles = 3'b011;
668,7 → 668,7
endcase // case(MCycle)
end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
8'b11xx0001 :
8'b11zz0001 :
begin
// POP qq
MCycles = 3'b011;
839,7 → 839,7
 
// 8 BIT ARITHMETIC AND LOGICAL GROUP
8'b10xxxxxx :
8'b10zzzzzz :
begin
if (IR[2:0] == 3'b110)
begin
883,7 → 883,7
end // else: !if(IR[2:0] == 3'b110)
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
8'b11xxx110 :
8'b11zzz110 :
begin
// ADD A,n
// ADC A,n
904,7 → 904,7
end
end
8'b00xxx100 :
8'b00zzz100 :
begin
if (IR[5:3] == 3'b110)
begin
942,7 → 942,7
end
end
8'b00xxx101 :
8'b00zzz101 :
begin
if (IR[5:3] == 3'b110)
begin
1087,7 → 1087,7
SetEI = 1'b1;
 
// 16 BIT ARITHMETIC GROUP
8'b00xx1001 :
8'b00zz1001 :
begin
// ADD HL,ss
MCycles = 3'b011;
1134,7 → 1134,7
endcase // case(MCycle)
end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001
8'b00xx0011 :
8'b00zz0011 :
begin
// INC ss
TStates = 3'b110;
1142,7 → 1142,7
IncDec_16[1:0] = DPAIR;
end
8'b00xx1011 :
8'b00zz1011 :
begin
// DEC ss
TStates = 3'b110;
1186,7 → 1186,7
end // case: 8'b11000011
8'b11xxx010 :
8'b11zzz010 :
begin
if (IR[5] == 1'b1 && Mode == 3 )
begin
1318,7 → 1318,7
end // case: 8'b00011000
 
// Conditional relative jumps (JR [C/NC/Z/NZ], e)
8'b001xx000 :
8'b001zz000 :
begin
if (Mode != 2 )
begin
1425,7 → 1425,7
endcase // case(MCycle)
end // case: 8'b11001101
8'b11xxx100 :
8'b11zzz100 :
begin
if (IR[5] == 1'b0 || Mode != 3 )
begin
1772,7 → 1772,7
Set_BusA_To[2:0] = IR[2:0];
Set_BusB_To[2:0] = IR[2:0];
casex (IR)
casez (IR)
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
1797,7 → 1797,7
end
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
8'b00xxx110 :
8'b00zzz110 :
begin
// RLC (HL)
// RL (HL)
1952,7 → 1952,7
//
//----------------------------------------------------------------------------
 
casex (IR)
casez (IR)
/*
* Undocumented NOP instructions commented out to reduce size of mcode
*
2574,6 → 2574,8
default :;
endcase // case(MCycle)
end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
 
default : ;
endcase // case(IR)
end // block: default_ed_block
/rtl/core/tv80_core.v
307,12 → 307,12
begin
casez (mcyc)
7'b1zzzzzz : mcyc_to_number = 3'h7;
7'bz1zzzzz : mcyc_to_number = 3'h6;
7'bzz1zzzz : mcyc_to_number = 3'h5;
7'bzzz1zzz : mcyc_to_number = 3'h4;
7'bzzzz1zz : mcyc_to_number = 3'h3;
7'bzzzzz1z : mcyc_to_number = 3'h2;
7'bzzzzzz1 : mcyc_to_number = 3'h1;
7'b01zzzzz : mcyc_to_number = 3'h6;
7'b001zzzz : mcyc_to_number = 3'h5;
7'b0001zzz : mcyc_to_number = 3'h4;
7'b00001zz : mcyc_to_number = 3'h3;
7'b000001z : mcyc_to_number = 3'h2;
7'b0000001 : mcyc_to_number = 3'h1;
default : mcyc_to_number = 3'h1;
endcase
end
855,6 → 855,7
SP[15:8] <= #1 Save_Mux;
5'b11011 :
F <= #1 Save_Mux;
default : ;
endcase
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
end // if (ClkEn == 1'b1 )
954,7 → 955,8
begin
RegWEH = ~ Read_To_Reg_r[0];
RegWEL = Read_To_Reg_r[0];
end
end // UNMATCHED !!
default : ;
endcase // case(Read_To_Reg_r)
end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
966,7 → 968,7
RegWEL = 1'b1;
end
 
if (IncDec_16[2] == 1'b1 && ((tstate[2] && wait_n == 1'b1 && mcycle != 3'b001) || (tstate[3] && mcycle[0])) )
if (IncDec_16[2] && ((tstate[2] && ~wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
case (IncDec_16[1:0])
2'b00 , 2'b01 , 2'b10 :
973,7 → 975,8
begin
RegWEH = 1'b1;
RegWEL = 1'b1;
end
end // UNMATCHED !!
default : ;
endcase
end
end // always @ *
995,7 → 998,7
RegDIH = RegBusA_r[15:8];
RegDIL = RegBusA_r[7:0];
end
else if (IncDec_16[2] == 1'b1 && ((tstate[2] && mcycle != 3'b001) || (tstate[3] && mcycle[0])) )
else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
begin
RegDIH = ID16[15:8];
RegDIL = ID16[7:0];
/rtl/uart/T16450.v
190,17 → 190,17
 
always @*
begin
IIR[7:3] <= #1 5'b00000;
IIR[7:3] = #1 5'b00000;
if (IER[2] && (LSR[4:1] != 4'b0000))
IIR[2:0] <= #1 3'b110;
IIR[2:0] = #1 3'b110;
else if (IER[0] && LSR[0])
IIR[2:0] <= #1 3'b100;
IIR[2:0] = #1 3'b100;
else if (IER[1] && LSR[5])
IIR[2:0] <= #1 3'b010;
IIR[2:0] = #1 3'b010;
else if (IER[3] && ((!MCR[4] && (MSR[3:0] != 0)) || (MCR[4] && (MCR[3:0] != 0))))
IIR[2:0] <= #1 3'b000;
IIR[2:0] = #1 3'b000;
else
IIR[2:0] <= #1 3'b001;
IIR[2:0] = #1 3'b001;
end
 
// Baud x 16 clock generator
284,7 → 284,7
end
if (rclk)
begin
if (!RX_Bit_Cnt && (RX_Filtered || (Bit_Phase == 4'b0111)))
if ((RX_Bit_Cnt == 0) && (RX_Filtered || (Bit_Phase == 4'b0111)))
begin
Bit_Phase <= #1 4'b0000;
end
307,7 → 307,7
LSR[4] <= #1 1'b1; // BI
end
end
if (!RX_Bit_Cnt )
if (RX_Bit_Cnt == 0)
begin
if (Bit_Phase == 4'b0111)
begin
/rtl/simple_gmii/simple_gmii_regs.v
1,5 → 1,5
module simple_gmii_regs (
clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,config,int_n);
clk,reset,addr,wr_data,rd_data,doe,rd_n,wr_n,iorq_n,status_set,status_msk,control,control_clr,rx_len0,rx_len1,rx_data,rx_data_stb,tx_data,tx_data_stb,cfg,int_n);
input clk;
input reset;
input [15:0] addr;
19,7 → 19,7
output rx_data_stb;
output [7:0] tx_data;
output tx_data_stb;
output config;
output cfg;
output int_n;
reg [7:0] rd_data;
reg block_select;
42,9 → 42,9
reg tx_data_rd_sel;
reg tx_data_wr_sel;
reg tx_data_stb;
reg config;
reg config_rd_sel;
reg config_wr_sel;
reg cfg;
reg cfg_rd_sel;
reg cfg_wr_sel;
reg int_n;
reg [7:0] int_vec;
always @*
61,8 → 61,8
rx_data_rd_sel = block_select & (addr[2:0] == 5) & !rd_n;
tx_data_rd_sel = block_select & (addr[2:0] == 6) & !rd_n;
tx_data_wr_sel = block_select & (addr[2:0] == 6) & !wr_n;
config_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
config_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
cfg_rd_sel = block_select & (addr[2:0] == 7) & !rd_n;
cfg_wr_sel = block_select & (addr[2:0] == 7) & !wr_n;
end
always @*
begin
78,10 → 78,10
rx_len1_rd_sel : rd_data = rx_len1;
rx_data_rd_sel : rd_data = rx_data;
tx_data_rd_sel : rd_data = tx_data;
config_rd_sel : rd_data = config;
cfg_rd_sel : rd_data = cfg;
default : rd_data = int_vec;
endcase
doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | config_rd_sel;
doe = status_rd_sel | status_msk_rd_sel | control_rd_sel | rx_len0_rd_sel | rx_len1_rd_sel | rx_data_rd_sel | tx_data_rd_sel | cfg_rd_sel;
end
always @*
begin
122,10 → 122,10
else if (tx_data_wr_sel) tx_data_stb <= 1;
else tx_data_stb <= 0;
end
// register: config
// register: cfg
always @(posedge clk)
begin
if (reset) config <= 0;
else if (config_wr_sel) config <= wr_data;
if (reset) cfg <= 0;
else if (cfg_wr_sel) cfg <= wr_data;
end
endmodule
/rtl/simple_gmii/simple_gmii_top.v
30,7 → 30,7
);
 
parameter txbuf_sz = 512, rxbuf_sz = 512;
parameter wr_ptr_sz = 10;
parameter wr_ptr_sz = 9;
 
input clk; // To core0 of simple_gmii_core.v, ...
input reset; // To core0 of simple_gmii_core.v, ...
148,7 → 148,7
.rx_data_stb (rx_rd_stb),
.tx_data (tx_wr_data),
.tx_data_stb (tx_wr_stb),
.config (en_preamble),
.cfg (en_preamble),
.int_n (int_n),
// Inputs
.clk (clk),
/scripts/reglib.py
226,6 → 226,8
self.add (read_stb_reg (params['name'],params['width']))
elif (type == 'write_stb'):
self.add (write_stb_reg (params['name'],params['width'],params['default']))
elif (type == 'hw_load'):
self.add (hw_load_reg (params['name'],params['width']))
else:
print "Unknown register type",type
 
296,6 → 298,32
def write_cap (self):
return 1
 
class hw_load_reg (config_reg):
def __init__ (self, name='', width=0, default=0):
basic_register.__init__(self, name, width)
self.default = default
def verilog_body (self):
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
"else if (%s_wr_sel) %s <= %s;" % (self.name, self.name, 'wr_data'),
"else if (%s_load) %s <= %s_wrdata;" % (self.name,self.name,self.name)
]
return self.id_comment() + seq_block ('clk', statements)
 
def io (self):
return [ port('input', self.name+'_wrdata', self.width),
port('input', self.name+'_load', 1),
port('output',self.name, self.width) ]
 
def nets (self):
return [ net('reg', self.name, self.width),
net('reg', self.name + '_rd_sel'),
net('reg', self.name + '_wr_sel')]
 
def write_cap (self):
return 1
 
 
class int_fixed_reg (basic_register):
def __init__ (self, name, mask_reg, int_value, width=0):
basic_register.__init__(self, name, width)
/env/tb.vf
1,12 → 1,4
/*
* Copyright (c) 2003-2004 by Cisco Systems Inc.
* $Id: tb.vf,v 1.5 2005-03-10 23:07:19 ghutchis Exp $
* All rights reserved.
*
* Author: Guy Hutchison
*
*/
 
+incdir+env
env/tb_top.v
rtl/core/tv80_alu.v
rtl/core/tv80_mcode.v

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