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URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /tv80/trunk
    from Rev 94 to Rev 95
    Reverse comparison

Rev 94 → Rev 95

/tests/hello.c
3,6 → 3,9
sfr at 0x81 msg_port;
sfr at 0x82 timeout_port;
 
void nmi_isr() {}
void isr() {}
 
void print (char *string)
{
char *iter;
/tests/Makefile
20,9 → 20,14
%.o : %.asm
$(AS) -l -o $*.o $^
 
#hello.ihx : hello.c bintr_crt0.o
# $(CC) $^ --no-std-crt0 bintr_crt0.o
otir.ihx : otir.o
$(CC) --no-std-crt0 $^
 
%.ihx : %.o
#$(LD) $(LINK_OPTIONS) $(AS_LINK_OPTIONS) -i $* $^ -e
$(CC) $^ --no-std-crt0 bintr_crt0.o
$(CC) $^
 
bintr.ihx : bintr.c bintr_crt0.o
$(CC) --no-std-crt0 bintr.c bintr_crt0.o
/scripts/regression
27,7 → 27,9
 
def run_tests (test_list):
for test_name in test_list:
os.system ("scripts/run %s" % test_name)
#os.system ("scripts/run %s" % test_name)
os.system ("(cd tests; make %s.ihx)" % test_name)
os.system ("sc_env/sc_env_top -i tests/%s.ihx | tee logs/%s.log" % (test_name, test_name))
 
def check_results (test_list):
print "%-20s %s" % ("Test", "Status")
38,9 → 40,9
testl = testh.readline()
while (testl != ''):
if (testl.find ("TEST PASSED")):
if (testl.find ("TEST PASSED") != -1):
status[test_name] = "passed"
elif (testl.find ("TEST FAILED")):
elif (testl.find ("TEST FAILED") != -1):
status[test_name] = "failed"
testl = testh.readline()
/scripts/sc_gen
1,6 → 1,6
#!/bin/bash
 
verilator --sc rtl/core/tv80s.v rtl/core/tv80_alu.v \
verilator --sc --trace -O3 rtl/core/tv80s.v rtl/core/tv80_alu.v \
rtl/core/tv80_mcode.v rtl/core/tv80_reg.v rtl/core/tv80_core.v
 
 
/sc_env/sc_env_top.cpp
4,10 → 4,34
#include "tv_responder.h"
#include "Vtv80s.h"
#include "SpTraceVcd.h"
#include <unistd.h>
 
extern char *optarg;
extern int optind, opterr, optopt;
 
int sc_main(int argc, char *argv[])
{
sc_clock clk("clk125", 8, SC_NS, 0.5, 0.0, SC_NS);
bool dumping = false;
bool memfile = false;
int index;
char *dumpfile_name;
char *mem_src_name;
SpTraceFile *tfp;
while ( (index = getopt(argc, argv, "d:i:")) != -1) {
printf ("DEBUG: getopt optind=%d index=%d char=%c\n", optind, index, (char) index);
if (index == 'd') {
dumpfile_name = new char(strlen(optarg)+1);
strcpy (dumpfile_name, optarg);
dumping = true;
printf ("VCD dump enabled to %s\n", dumpfile_name);
} else if (index == 'i') {
mem_src_name = new char(strlen(optarg)+1);
strcpy (mem_src_name, optarg);
memfile = true;
}
}
sc_clock clk("clk125", 8, SC_NS, 0.5);
 
sc_signal<bool> reset_n;
sc_signal<bool> wait_n;
95,17 → 119,20
sc_trace (trace_file, di, "di");
sc_trace (trace_file, dout, "dout");
sc_trace (trace_file, addr, "addr");
*/
// Start Verilator traces
Verilated::traceEverOn(true);
SpTraceFile *tfp = new SpTraceFile;
tv80s.trace (tfp, 99);
tfp->open ("tv80.vcd");
*/
if (dumping) {
Verilated::traceEverOn(true);
tfp = new SpTraceFile;
tv80s.trace (tfp, 99);
tfp->open (dumpfile_name);
}
 
// check for command line argument
if (argc > 1) {
env_memory0.load_ihex (argv[1]);
if (memfile) {
printf ("Loading IHEX file %s\n", mem_src_name);
env_memory0.load_ihex (mem_src_name);
}
// set reset to 0 before sim start
114,9 → 141,9
sc_start();
/*
sc_close_vcd_trace_file (trace_file);
tfp->close();
*/
if (dumping)
tfp->close();
return 0;
}

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