URL
https://opencores.org/ocsvn/uart2bus/uart2bus/trunk
Subversion Repositories uart2bus
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart2bus/trunk/vhdl/bench
- from Rev 11 to Rev 13
- ↔ Reverse comparison
Rev 11 → Rev 13
/helpers/helpers_pkg.vhd
1,8 → 1,12
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
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package helpers_pkg is |
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procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic); |
procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)); |
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component regFileModel |
port |
( |
16,3 → 20,41
end component; |
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end helpers_pkg; |
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package body helpers_pkg is |
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procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is |
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variable shiftreg : std_logic_vector(7 downto 0); |
variable bitTime : time; |
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begin |
bitTime := 1000 ms / (baud + baud * baudError / 100.0); |
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length)); |
txd <= '0'; |
wait for bitTime; |
for index in 0 to bitnumber loop |
txd <= shiftreg(index); |
wait for bitTime; |
end loop; |
txd <= '1'; |
wait for stopbit * bitTime; |
end procedure; |
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procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is |
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variable bitTime : time; |
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begin |
bitTime := 1000 ms / (baud + baud * baudError / 100.0); |
wait until (rxd = '0'); |
wait for bitTime / 2; |
wait for bitTime; |
for index in 0 to bitnumber loop |
data <= rxd & data(7 downto 1); |
wait for bitTime; |
end loop; |
wait for stopbit * bitTime; |
end procedure; |
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end; |
/helpers/regFileModel.vhd
4,7 → 4,7
----------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.ALL; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
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entity regFileModel is |
port ( -- global signals |
33,7 → 33,7
end loop; |
elsif (rising_edge(clk)) then |
if (intWrite = '1') then |
regFile(conv_integer(intAddress)) <= intWrData; |
regFile(to_integer(unsigned(intAddress))) <= intWrData; |
end if; |
end if; |
end process; |
44,7 → 44,7
intRdData <= (others => '0'); |
elsif (rising_edge(clk)) then |
if (intRead = '1') then |
intRdData <= regFile(conv_integer(intAddress)); |
intRdData <= regFile(to_integer(unsigned(intAddress))); |
end if; |
end if; |
end process; |
/uart2BusTop_bin_tb.vhd
6,9 → 6,7
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_textio.all; |
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library work; |
use work.uart2BusTop_pkg.all; |
/uart2BusTop_txt_tb.vhd
6,9 → 6,6
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_textio.all; |
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library work; |
use work.uart2BusTop_pkg.all; |
21,40 → 18,6
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architecture behavior of uart2BusTop_txt_tb is |
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procedure sendSerial(data : integer; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal txd : inout std_logic) is |
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variable shiftreg : std_logic_vector(7 downto 0); |
variable bitTime : time; |
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begin |
bitTime := 1000 ms / (baud + baud * baudError / 100.0); |
shiftreg := std_logic_vector(to_unsigned(data, shiftreg'length)); |
txd <= '0'; |
wait for bitTime; |
for index in 0 to bitnumber loop |
txd <= shiftreg(index); |
wait for bitTime; |
end loop; |
txd <= '1'; |
wait for stopbit * bitTime; |
end procedure; |
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procedure recvSerial( signal rxd : in std_logic; baud : in real; parity : in integer; stopbit : in real; bitnumber : in integer; baudError : in real; signal data : inout std_logic_vector(7 downto 0)) is |
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variable bitTime : time; |
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begin |
bitTime := 1000 ms / (baud + baud * baudError / 100.0); |
wait until (rxd = '0'); |
wait for bitTime / 2; |
wait for bitTime; |
for index in 0 to bitnumber loop |
data <= rxd & data(7 downto 1); |
wait for bitTime; |
end loop; |
wait for stopbit * bitTime; |
end procedure; |
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-- Inputs |
signal clr : std_logic := '0'; |
signal clk : std_logic := '0'; |