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GNU GENERAL PUBLIC LICENSE |
Version 3, 29 June 2007 |
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Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> |
Everyone is permitted to copy and distribute verbatim copies |
of this license document, but changing it is not allowed. |
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Preamble |
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The GNU General Public License is a free, copyleft license for |
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17. Interpretation of Sections 15 and 16. |
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0,0 → 1,165
GNU LESSER GENERAL PUBLIC LICENSE |
Version 3, 29 June 2007 |
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Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> |
Everyone is permitted to copy and distribute verbatim copies |
of this license document, but changing it is not allowed. |
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This version of the GNU Lesser General Public License incorporates |
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License, supplemented by the additional permissions listed below. |
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0. Additional Definitions. |
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As used herein, "this License" refers to version 3 of the GNU Lesser |
General Public License, and the "GNU GPL" refers to version 3 of the GNU |
General Public License. |
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/trunk/trunk/doc/termout.png
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Index: trunk/trunk/doc/uart6551.txt
===================================================================
--- trunk/trunk/doc/uart6551.txt (nonexistent)
+++ trunk/trunk/doc/uart6551.txt (revision 2)
@@ -0,0 +1,35 @@
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |WISHBONE Datasheet
+ |WISHBONE SoC Architecture Specification, Revision B.3
+ |
+ |Description: Specifications:
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |General Description: UART core
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |Supported Cycles: SLAVE,READ/WRITE
+ | SLAVE,BLOCK READ/WRITE
+ | SLAVE,RMW
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |Data port, size: 32 bit
+ |Data port, granularity: 8 bit
+ |Data port, maximum operand size: 32 bit
+ |Data transfer ordering: Undefined
+ |Data transfer sequencing: Undefined
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |Clock frequency constraints: 100MHz for proper baud lookup
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |Supported signal list and Signal Name WISHBONE equiv.
+ |cross reference to equivalent ack_o ACK_O
+ |WISHBONE signals adr_i[1:0] ADR_I()
+ | clk_i CLK_I
+ | rst_i RST_I()
+ | dat_i(31:0) DAT_I()
+ | dat_o(31:0) DAT_O()
+ | cyc_i CYC_I
+ | stb_i STB_I
+ | we_i WE_I
+ |
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+ |Special requirements:
+ +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
Index: trunk/trunk/rtl/ack_gen.v
===================================================================
--- trunk/trunk/rtl/ack_gen.v (nonexistent)
+++ trunk/trunk/rtl/ack_gen.v (revision 2)
@@ -0,0 +1,61 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ack_gen.v
+// - generates a acknowledge signal after a specified number of clocks.
+// - separate stages for read and write
+//
+// ============================================================================
+//
+module ack_gen(clk_i, ce_i, i, we_i, o);
+input clk_i;
+input ce_i;
+input i;
+input we_i;
+output reg o;
+parameter READ_STAGES = 3;
+parameter WRITE_STAGES = 0;
+parameter ACK_LEVEL = 1'b0;
+parameter REGISTER_OUTPUT = 1'b0;
+
+wire ro, wo;
+generate begin : gRdy
+if (READ_STAGES==0)
+assign ro = 0;
+else begin
+ready_gen #(READ_STAGES) urrdy (clk_i, ce_i, i, ro);
+end
+if (WRITE_STAGES==0)
+assign wo = we_i;
+else begin
+ready_gen #(WRITE_STAGES) uwrdy (clk_i, ce_i, we_i, wo);
+end
+if (REGISTER_OUTPUT) begin
+always @(posedge clk_i)
+ o <= we_i ? wo : (i ? ro : ACK_LEVEL);
+end
+else begin
+always @*
+ o <= we_i ? wo : (i ? ro : ACK_LEVEL);
+end
+end
+endgenerate
+
+endmodule
Index: trunk/trunk/rtl/edge_det.v
===================================================================
--- trunk/trunk/rtl/edge_det.v (nonexistent)
+++ trunk/trunk/rtl/edge_det.v (revision 2)
@@ -0,0 +1,49 @@
+// ============================================================================
+// (C) 2007-2019 Robert Finch
+// All Rights Reserved.
+//
+// edge_det.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// Notes:
+//
+// Edge detector
+// This little core detects an edge (positive, negative, and
+// either) in the input signal.
+//
+// ============================================================================
+//
+module edge_det(rst, clk, ce, i, pe, ne, ee);
+input rst; // reset
+input clk; // clock
+input ce; // clock enable
+input i; // input signal
+output pe; // positive transition detected
+output ne; // negative transition detected
+output ee; // either edge (positive or negative) transition detected
+
+reg ed = 1'b0;
+always @(posedge clk)
+ if (rst)
+ ed <= 1'b0;
+ else if (ce)
+ ed <= i;
+
+assign pe = ~ed & i; // positive: was low and is now high
+assign ne = ed & ~i; // negative: was high and is now low
+assign ee = ed ^ i; // either: signal is now opposite to what it was
+
+endmodule
Index: trunk/trunk/rtl/ready_gen.v
===================================================================
--- trunk/trunk/rtl/ready_gen.v (nonexistent)
+++ trunk/trunk/rtl/ready_gen.v (revision 2)
@@ -0,0 +1,45 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@opencores.org
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ready_gen.v
+// - generates a ready signal after a specified number of clocks.
+// - this is not a simple delay line. Output is set low as soom as the
+// input goes low.
+//
+// ============================================================================
+//
+module ready_gen(clk_i, ce_i, i, o);
+input clk_i;
+input ce_i;
+input i;
+output reg o = 1'd0;
+parameter STAGES = 3;
+
+integer n;
+reg [STAGES-1:0] rdy;
+always @(posedge clk_i)
+if (ce_i) begin
+ rdy[0] <= i;
+ for (n = 1; n < STAGES; n = n + 1)
+ rdy[n] <= rdy[n-1] & i;
+ o <= rdy[STAGES-1] & i;
+end
+
+endmodule
Index: trunk/trunk/rtl/uart6551.sv
===================================================================
--- trunk/trunk/rtl/uart6551.sv (nonexistent)
+++ trunk/trunk/rtl/uart6551.sv (revision 2)
@@ -0,0 +1,595 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ============================================================================
+//
+`define UART_TRB 2'd0 // transmit/receive buffer
+`define UART_STAT 2'd1
+`define UART_CMD 2'd2
+`define UART_CTRL 2'd3
+
+module uart6551(rst_i, clk_i, cs_i, irq_o,
+ cyc_i, stb_i, ack_o, we_i, sel_i, adr_i, dat_i, dat_o,
+ cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni,
+ rxd_i, txd_o, data_present,
+ rxDRQ_o, txDRQ_o,
+ xclk_i, RxC_i
+);
+parameter pCounterBits = 24;
+parameter pFifoSize = 1024;
+parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock
+parameter HIGH = 1'b1;
+parameter LOW = 1'b0;
+input rst_i;
+input clk_i; // eg 50.000MHz
+input cs_i; // circuit select
+// WISHBONE -------------------------------
+input cyc_i; // bus cycle valid
+input stb_i;
+output ack_o;
+input we_i; // 1 = write
+input [3:0] sel_i;
+input [3:2] adr_i; // register address
+input [31:0] dat_i; // data input bus
+output reg [31:0] dat_o; // data output bus
+//------------------------------------------
+output reg irq_o; // interrupt request
+input cts_ni; // clear to send - (flow control) active low
+output reg rts_no; // request to send - (flow control) active low
+input dsr_ni; // data set ready - active low
+input dcd_ni; // data carrier detect - active low
+output reg dtr_no; // data terminal ready - active low
+input ri_ni; // ring indicator
+input rxd_i; // serial data in
+output txd_o; // serial data out
+output data_present;
+output rxDRQ_o; // reciever DMA request
+output txDRQ_o; // transmitter DMA request
+input xclk_i; // external clock source
+input RxC_i; // external receiver clock source
+
+reg accessCD; // clock multiplier access flag
+reg llb; // local loopback mode
+reg dmaEnable;
+// baud rate clock control
+reg [4:0] baudRateSel;
+reg selCD; // Use clock multiplier register
+reg [pCounterBits-1:0] c; // current count
+reg [pCounterBits-1:0] ckdiv; // baud rate clock divider
+reg [pCounterBits-1:0] clkdiv; // clock multiplier register
+reg [1:0] xclks; // synchronized external clock
+reg [1:0] RxCs; // synchronized external receiver clock
+reg baud16; // 16x baud rate clock
+wire baud16rx; // reciever clock
+reg xClkSrc; // uart baud clock is external
+reg rxClkSrc; // receiver clock is external
+
+// frame format registers
+reg [3:0] wordLength;
+reg stopBit;
+reg [2:0] stopBits;
+reg [2:0] parityCtrl;
+wire [7:0] frameSize;
+
+reg txBreak; // transmit a break
+
+wire rxFull;
+wire rxEmpty;
+wire txFull;
+wire txEmpty;
+reg hwfc; // hardware flow control enable
+wire [7:0] lineStatusReg;
+wire [7:0] modemStatusReg;
+wire [7:0] irqStatusReg;
+// interrupt
+reg rxIe;
+reg txIe;
+reg modemStatusChangeIe;
+wire modemStatusChange;
+reg lineStatusChangeIe;
+wire lineStatusChange;
+reg rxToutIe; // receiver timeout interrupt enable
+reg [3:0] rxThres; // receiver threshold for interrupt
+reg [3:0] txThres; // transmitter threshold for interrupt
+reg rxTout; // receiver timeout
+wire [11:0] rxCnt; // reciever counter value
+reg [7:0] rxToutMax;
+reg [2:0] irqenc; // encoded irq cause
+wire rxITrig; // receiver interrupt trigger level
+wire txITrig; // transmitter interrupt trigger level
+// reciever errors
+wire parityErr; // reciever detected a parity error
+wire frameErr; // receiver char framing error
+wire overrun; // receiver over run
+wire rxBreak; // reciever detected a break
+wire rxGErr; // global error: there is at least one error in the reciever fifo
+// modem controls
+reg [1:0] ctsx; // cts_n sampling
+reg [1:0] dcdx;
+reg [1:0] dsrx;
+reg [1:0] rix;
+reg deltaCts;
+reg deltaDcd;
+reg deltaDsr;
+reg deltaRi;
+
+// fifo
+reg rxFifoClear;
+reg txFifoClear;
+reg fifoEnable;
+wire [3:0] rxQued;
+wire [3:0] txQued;
+
+// test
+wire txd1;
+
+assign data_present = ~rxEmpty;
+
+assign rxITrig = rxQued >= rxThres;
+assign txITrig = txQued <= txThres;
+wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty);
+wire txDRQ1 = (fifoEnable ? txITrig : txEmpty);
+assign rxDRQ = dmaEnable & rxDRQ1;
+assign txDRQ = dmaEnable & txDRQ1;
+wire rxIRQ = rxIe & rxDRQ1;
+wire txIRQ = txIe & txDRQ1;
+
+reg [7:0] cmd0, cmd1, cmd2, cmd3;
+reg [7:0] ctrl0, ctrl1, ctrl2, ctrl3;
+
+always @(posedge clk_i)
+ irq_o <=
+ rxIRQ
+ | txIRQ
+ | (rxTout & rxToutIe)
+ | (lineStatusChange & lineStatusChangeIe)
+ | (modemStatusChange & modemStatusChangeIe)
+ ;
+
+// Hold onto address and data an extra cycle.
+// The extra cycle updates or reads the serial transmit / receive.
+reg [31:0] dati;
+always @(posedge clk_i)
+ dati <= dat_i;
+reg [3:2] adr_h;
+always @(posedge clk_i)
+ adr_h <= adr_i;
+reg we;
+always @(posedge clk_i)
+ we <= we_i;
+reg [3:0] sel;
+always @(posedge clk_i)
+ sel <= sel_i;
+
+wire [7:0] rx_do;
+wire rdrx = ack_o && adr_h==`UART_TRB && ~we && !accessCD;
+wire txrx = ack_o && adr_h==`UART_TRB && !accessCD;
+
+wire cs = cs_i & cyc_i & stb_i;
+
+ack_gen #(
+ .READ_STAGES(1),
+ .WRITE_STAGES(0),
+ .REGISTER_OUTPUT(1)
+) uag1
+(
+ .clk_i(clk_i),
+ .ce_i(1'b1),
+ .i(cs),
+ .we_i(cs & we_i),
+ .o(ack_o)
+);
+
+uart6551Rx uart_rx0
+(
+ .rst(rst_i),
+ .clk(clk_i),
+ .cyc(cyc_i),
+ .cs(rdrx),
+ .wr(we),
+ .dout(rx_do),
+ .ack(),
+ .fifoEnable(fifoEnable),
+ .fifoClear(rxFifoClear),
+ .clearGErr(1'b0),
+ .wordLength(wordLength),
+ .parityCtrl(parityCtrl),
+ .frameSize(frameSize),
+ .stop_bits(stopBits),
+ .baud16x_ce(baud16rx),
+ .clear(1'b0),
+ .rxd(llb ? txd1 : rxd_i),
+ .full(),
+ .empty(rxEmpty),
+ .frameErr(frameErr),
+ .overrun(overrun),
+ .parityErr(parityErr),
+ .break_o(rxBreak),
+ .gerr(rxGErr),
+ .qcnt(rxQued),
+ .cnt(rxCnt)
+);
+
+uart6551Tx uart_tx0
+(
+ .rst(rst_i),
+ .clk(clk_i),
+ .cyc(cyc_i),
+ .cs(txrx),
+ .wr(we),
+ .din(dati[7:0]),
+ .ack(),
+ .fifoEnable(fifoEnable),
+ .fifoClear(txFifoClear),
+ .txBreak(txBreak),
+ .frameSize(frameSize), // 16 x 10 bits
+ .wordLength(wordLength),// 8 bits
+ .parityCtrl(parityCtrl),// no parity
+ .baud16x_ce(baud16),
+ .cts(ctsx[1]|~hwfc),
+ .clear(clear),
+ .txd(txd1),
+ .full(txFull),
+ .empty(txEmpty),
+ .qcnt(txQued)
+);
+
+assign txd_o = llb ? 1'b1 : txd1;
+
+assign lineStatusReg = {rxGErr,1'b0,txFull,rxBreak,1'b0,1'b0,1'b0,1'b0};
+assign modemStatusChange = deltaDcd|deltaRi|deltaDsr|deltaCts; // modem status delta
+assign modemStatusReg = {1'b0,~rix[1],1'b0,~ctsx[1],deltaDcd, deltaRi, deltaDsr, deltaCts};
+assign irqStatusReg = {irq_o,2'b00,irqenc,2'b00};
+
+// mux the reg outputs
+always @(posedge clk_i)
+begin
+ case(adr_i)
+ `UART_TRB: dat_o <= accessCD ? {8'h0,clkdiv} : {24'h0,rx_do}; // receiver holding register
+ `UART_STAT: dat_o <= {irqStatusReg,modemStatusReg,lineStatusReg,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr};
+ `UART_CMD: dat_o <= {cmd3,cmd2,cmd1,cmd0};
+ `UART_CTRL: dat_o <= {ctrl3,ctrl2,ctrl1,ctrl0};
+ endcase
+end
+
+
+// register updates
+always @(posedge clk_i)
+if (rst_i) begin
+ rts_no <= HIGH;
+ dtr_no <= HIGH;
+ // interrupts
+ rxIe <= 1'b0;
+ txIe <= 1'b0;
+ modemStatusChangeIe <= 1'b0;
+ lineStatusChangeIe <= 1'b0;
+ hwfc <= 1'b0;
+ modemStatusChangeIe <= 1'b0;
+ lineStatusChangeIe <= 1'b0;
+ dmaEnable <= 1'b0;
+ // clock control
+ baudRateSel <= 5'h0;
+ rxClkSrc <= 1'b0; // ** 6551 defaults to zero (external receiver clock)
+ clkdiv <= pClkDiv;
+ // frame format
+ wordLength <= 4'd8; // 8 bits
+ stopBit <= 1'b0; // 1 stop bit
+ parityCtrl <= 3'd0; // no parity
+
+ txBreak <= 1'b0;
+ // Fifo control
+ txFifoClear <= 1'b1;
+ rxFifoClear <= 1'b1;
+ fifoEnable <= 1'b1;
+ // Test
+ llb <= 1'b0;
+ selCD <= 1'b0;
+ accessCD <= 1'b0;
+end
+else begin
+
+ //llb <= 1'b1;
+ rxFifoClear <= 1'b0;
+ txFifoClear <= 1'b0;
+ ctrl2[1] <= 1'b0;
+ ctrl2[2] <= 1'b0;
+
+ if (ack_o & we) begin
+ case (adr_h) // synopsys full_case parallel_case
+
+ `UART_TRB:
+ if (accessCD) begin
+ clkdiv <= dati;
+ accessCD <= 1'b0;
+ ctrl3[7] <= 1'b0;
+ end
+
+ // Writing to the status register does a software reset of some bits.
+ `UART_STAT:
+ begin
+ dtr_no <= HIGH;
+ rxIe <= 1'b0;
+ rts_no <= HIGH;
+ txIe <= 1'b0;
+ txBreak <= 1'b0;
+ llb <= 1'b0;
+ end
+ `UART_CMD:
+ begin
+ if (sel[0]) begin
+ cmd0 <= dati[7:0];
+ dtr_no <= ~dati[0];
+ rxIe <= ~dati[1];
+ case(dati[3:2])
+ 2'd0: begin rts_no <= 1'b1; txIe <= 1'b0; txBreak <= 1'b0; end
+ 2'd1: begin rts_no <= 1'b0; txIe <= 1'b1; txBreak <= 1'b0; end
+ 2'd2: begin rts_no <= 1'b0; txIe <= 1'b0; txBreak <= 1'b0; end
+ 2'd3: begin rts_no <= 1'b0; txIe <= 1'b0; txBreak <= 1'b1; end
+ endcase
+ llb <= dati[4];
+ parityCtrl <= dati[7:5]; //000=none,001=odd,011=even,101=force 1,111 = force 0
+ end
+ if (sel[1]) begin
+ cmd1 <= dati[15:8];
+ lineStatusChangeIe <= dati[8];
+ modemStatusChangeIe <= dati[9];
+ rxToutIe <= dati[10];
+ end
+ if (sel[2])
+ cmd2 <= dati[23:16];
+ if (sel[3])
+ cmd3 <= dati[31:24];
+ end
+
+ `UART_CTRL:
+ begin
+ if (sel[0]) begin
+ ctrl0 <= dati[7:0];
+ baudRateSel[3:0] <= dati[3:0];
+ rxClkSrc <= dati[4]; // 1 = baud rate generator, 0 = external
+ //11=5,10=6,01=7,00=8
+ case(dati[6:5])
+ 2'd0: wordLength <= 6'd8;
+ 2'd1: wordLength <= 6'd7;
+ 2'd2: wordLength <= 6'd6;
+ 2'd3: wordLength <= 6'd5;
+ endcase
+ stopBit <= dati[7]; //0=1,1=1.5 or 2
+ end
+ // Extended word length, values beyond 11 not supported.
+ if (sel[1]) begin
+ ctrl1 <= dati[15:8];
+ end
+ if (sel[2]) begin
+ ctrl2 <= dati[23:16];
+ fifoEnable <= dati[16];
+ rxFifoClear <= dati[17];
+ txFifoClear <= dati[18];
+ case (dati[21:20])
+ 2'd0: txThres <= 4'd1; // one-byte
+ 2'd1: txThres <= pFifoSize / 4; // one-quarter full
+ 2'd2: txThres <= pFifoSize / 2; // one-half full
+ 2'd3: txThres <= pFifoSize * 3 / 4; // three-quarters full
+ endcase
+ case (dati[23:22])
+ 2'd0: rxThres <= 4'd1; // one-byte
+ 2'd1: rxThres <= pFifoSize / 4; // one-quarter full
+ 2'd2: rxThres <= pFifoSize / 2; // one-half full
+ 2'd3: rxThres <= pFifoSize * 3 / 4; // three quarters full
+ endcase
+ end
+ if (sel[3]) begin
+ ctrl3 <= dati[31:24];
+ hwfc <= dati[24];
+ dmaEnable <= dati[26];
+ baudRateSel[4] <= dati[27];
+ selCD <= dati[30];
+ accessCD <= dati[31];
+ end
+ end
+
+ default:
+ ;
+ endcase
+ end
+end
+
+// ----------------------------------------------------------------------------
+// Baud rate control.
+// ----------------------------------------------------------------------------
+
+always @(posedge clk_i)
+ xClkSrc <= baudRateSel==5'd0;
+
+wire [pCounterBits-1:0] bclkdiv;
+uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv));
+
+reg [pCounterBits-1:0] clkdiv2;
+always @(posedge clk_i)
+ clkdiv2 <= selCD ? clkdiv : bclkdiv;
+
+always @(posedge clk_i)
+if (rst_i)
+ c <= 1'd1;
+else begin
+ c <= c + 2'd1;
+ if (c >= clkdiv2)
+ c <= 2'd1;
+end
+
+// for detecting an edge on the baud clock
+wire ibaud16 = c == 2'd1;
+
+// Detect an edge on the external clock
+wire xclkEdge;
+edge_det ed1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(xclks[1]), .pe(xclkEdge), .ne() );
+
+// Detect an edge on the external clock
+wire rxClkEdge;
+edge_det ed2(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(RxCs[1]), .pe(rxClkEdge), .ne() );
+
+always @(xClkSrc or xclkEdge or ibaud16)
+if (xClkSrc) // 16x external clock (xclk)
+ baud16 <= xclkEdge;
+else
+ baud16 <= ibaud16;
+
+assign baud16rx = rxClkSrc ? baud16 : rxClkEdge;
+
+//------------------------------------------------------------
+// external signal synchronization
+//------------------------------------------------------------
+
+// External receiver clock
+always @(posedge clk_i)
+ RxCs <= {RxCs[1:0],RxC_i};
+
+// External baud clock
+always @(posedge clk_i)
+ xclks <= {xclks[1:0],xclk_i};
+
+
+always @(posedge clk_i)
+ ctsx <= {ctsx[0],llb?~rts_no:~cts_ni};
+
+always @(posedge clk_i)
+ dcdx <= {dcdx[0],~dcd_ni};
+
+always @(posedge clk_i)
+ dsrx <= {dsrx[0],llb?~dtr_no:~dsr_ni};
+
+always @(posedge clk_i)
+ rix <= {rix[0],~ri_ni};
+
+//------------------------------------------------------------
+// state change detectors
+//------------------------------------------------------------
+
+wire ne_stat;
+edge_det ued3 (
+ .rst(rst_i),
+ .clk(clk_i),
+ .ce(1'b1),
+ .i(ack_o && adr_i==`UART_STAT && ~we_i && sel_i[2]),
+ .pe(),
+ .ne(ne_stat),
+ .ee()
+);
+
+// detect a change on the dsr signal
+always @(posedge clk_i)
+if (rst_i)
+ deltaDsr <= 1'b0;
+else begin
+ if (ne_stat)
+ deltaDsr <= 0;
+ else if (~deltaDsr)
+ deltaDsr <= dsrx[1] ^ dsrx[0];
+end
+
+// detect a change on the dcd signal
+always @(posedge clk_i)
+if (rst_i)
+ deltaDcd <= 1'b0;
+else begin
+ if (ne_stat)
+ deltaDcd <= 0;
+ else if (~deltaDcd)
+ deltaDcd <= dcdx[1] ^ dcdx[0];
+end
+
+// detect a change on the cts signal
+always @(posedge clk_i)
+if (rst_i)
+ deltaCts <= 1'b0;
+else begin
+ if (ne_stat)
+ deltaCts <= 0;
+ else if (~deltaCts)
+ deltaCts <= ctsx[1] ^ ctsx[0];
+end
+
+// detect a change on the ri signal
+always @(posedge clk_i)
+if (rst_i)
+ deltaRi <= 1'b0;
+else begin
+ if (ne_stat)
+ deltaRi <= 0;
+ else if (~deltaRi)
+ deltaRi <= rix[1] ^ rix[0];
+end
+
+// detect a change in line status
+reg [7:0] pLineStatusReg;
+always @(posedge clk_i)
+ pLineStatusReg <= lineStatusReg;
+
+assign lineStatusChange = pLineStatusReg != lineStatusReg;
+
+//-----------------------------------------------------
+
+// compute recieve timeout
+always @(wordLength)
+ rxToutMax <= (wordLength << 2) + 6'd12;
+
+always @(posedge clk_i)
+if (rst_i)
+ rxTout <= 1'b0;
+else begin
+ // read of receiver clears timeout counter
+ if (rdrx)
+ rxTout <= 1'b0;
+ // Don't time out if the fifo is empty
+ else if (rxCnt[9:4]==rxToutMax && ~rxEmpty)
+ rxTout <= 1'b1;
+end
+
+
+//-----------------------------------------------------
+// compute the 2x number of stop bits
+always @*
+if (stopBit==1'b0) // one stop bit
+ stopBits <= 3'd2;
+else if (wordLength==6'd8 && parityCtrl != 3'd0)
+ stopBits <= 3'd2;
+else if (wordLength==6'd5 && parityCtrl == 3'd0) // 5 bits - 1 1/2 stop bit
+ stopBits <= 3'd3;
+else
+ stopBits <= 3'd4; // two stop bits
+
+
+// compute frame size
+// frame size is one less
+assign frameSize = {wordLength + 4'd1 + stopBits[2:1] + parityCtrl[0], stopBits[0],3'b0} - 1;
+
+//-----------------------------------------------------
+// encode IRQ mailbox
+always @(rxDRQ or rxTout or txDRQ or lineStatusChange or modemStatusChange)
+ irqenc <=
+ lineStatusChange ? 3'd0 :
+ ~rxDRQ ? 3'd1 :
+ rxTout ? 3'd2 :
+ ~txDRQ ? 3'd3 :
+ modemStatusChange ? 3'd4 :
+ 3'd0;
+
+endmodule
Index: trunk/trunk/rtl/uart6551BaudLUT.sv
===================================================================
--- trunk/trunk/rtl/uart6551BaudLUT.sv (nonexistent)
+++ trunk/trunk/rtl/uart6551BaudLUT.sv (revision 2)
@@ -0,0 +1,61 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ============================================================================
+//
+module uart6551BaudLUT(a, o);
+parameter pCounterBits = 24;
+input [4:0] a;
+output reg [pCounterBits-1:0] o;
+
+// table for a 50.000MHz reference clock
+// value = 50,000,000 / (baud * 16)
+always @(a)
+ case (a) // synopsys full_case parallel_case
+ 5'd0: o <= 0;
+ 5'd1: o <= 24'd62500; // 50 baud
+ 5'd2: o <= 24'd41667; // 75 baud
+ 5'd3: o <= 24'd28617; // 109.92 baud
+ 5'd4: o <= 24'd23220; // 134.58 baud
+ 5'd5: o <= 24'd20833; // 150 baud
+ 5'd6: o <= 24'd10417; // 300 baud
+ 5'd7: o <= 24'd5208; // 600 baud
+ 5'd8: o <= 24'd2604; // 1200 baud
+ 5'd9: o <= 24'd1736; // 1800 baud
+ 5'd10: o <= 24'd1302; // 2400 baud
+ 5'd11: o <= 24'd868; // 3600 baud
+ 5'd12: o <= 24'd651; // 4800 baud
+ 5'd13: o <= 24'd434; // 7200 baud
+ 5'd14: o <= 24'd326; // 9600 baud
+ 5'd15: o <= 24'd163; // 19200 baud
+
+ 5'd16: o <= 24'd81; // 38400 baud
+ 5'd17: o <= 24'd54; // 57600 baud
+ 5'd18: o <= 24'd27; // 115200 baud
+ 5'd19: o <= 24'd14; // 230400 baud
+ 5'd20: o <= 24'd7; // 460800 baud
+ 5'd21: o <= 24'd3; // 921600 baud
+ default: o <= 24'd326; // 9600 baud
+ endcase
+
+endmodule
+
+
Index: trunk/trunk/rtl/uart6551Fifo.sv
===================================================================
--- trunk/trunk/rtl/uart6551Fifo.sv (nonexistent)
+++ trunk/trunk/rtl/uart6551Fifo.sv (revision 2)
@@ -0,0 +1,52 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2003-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ============================================================================
+//
+module uart6551Fifo(clk, rst, wr, rd, din, dout, ctr, full, empty);
+parameter WID=8;
+parameter DEP=16;
+localparam pCtrBits = $clog2(DEP)-1;
+input clk;
+input rst;
+input wr;
+input rd;
+input [WID-1:0] din;
+output [WID-1:0] dout;
+output [pCtrBits:0] ctr;
+reg [pCtrBits:0] ctr;
+output full;
+output empty;
+
+assign full = ctr=={pCtrBits{1'b1}}-1;
+assign empty = ctr=={pCtrBits{1'b1}};
+wire rdok = rd & ~empty;
+wire wrok = wr & ~full;
+
+vtdl #(WID,DEP) u1 (.clk(clk), .ce(1'b1), .a(ctr), .d(din), .q(dout));
+
+always @(posedge clk)
+if (rst)
+ ctr <= {pCtrBits{1'b1}};
+else
+ ctr <= ctr + {rdok&~wrok,rdok&~wrok,rdok&~wrok,rdok^wrok};
+
+endmodule
Index: trunk/trunk/rtl/uart6551Rx.sv
===================================================================
--- trunk/trunk/rtl/uart6551Rx.sv (nonexistent)
+++ trunk/trunk/rtl/uart6551Rx.sv (revision 2)
@@ -0,0 +1,339 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2005-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ============================================================================
+//
+`define IDLE 0
+`define CNT 1
+
+module uart6551Rx(rst, clk,
+ cyc, cs, wr, dout, ack,
+ fifoEnable, fifoClear, clearGErr,
+ parityCtrl, frameSize, stop_bits, wordLength, baud16x_ce, clear, rxd,
+ full, empty, frameErr, overrun, parityErr, break_o, gerr, qcnt, cnt, bitStream);
+input rst;
+input clk;
+input cyc; // valid bus cycle
+input cs; // core select
+input wr; // read reciever
+output [7:0] dout; // fifo data out
+output ack;
+input fifoEnable; // enable the fifo
+input fifoClear;
+input clearGErr; // clear global error
+input [2:0] parityCtrl;
+input [7:0] frameSize; // frame count
+input [2:0] stop_bits;
+input [3:0] wordLength;
+input baud16x_ce; // baud rate clock enable
+input clear; // clear reciever
+input rxd; // external serial input
+output full; // receive fifo full
+output empty; // receiver fifo is empty
+output frameErr; // framing error
+output overrun; // receiver overrun
+output parityErr; // parity error
+output break_o; // break detected
+output gerr; // global error indicator
+output [3:0] qcnt; // count of number of words queued
+output [9:0] cnt; // receiver counter
+output bitStream; // received bit stream
+
+//0 - simple sampling at middle of symbol period
+//>0 - sampling of 3 middle ticks of sumbol perion and results as majority
+parameter SamplerStyle = 0;
+
+
+reg overrun;
+reg [9:0] cnt; // sample bit rate counter / timeout counter
+reg [10:0] rx_data; // working receive data register
+reg [9:0] t2; // data minus stop bit(s)
+reg [7:0] t3,t4; // data minus parity bit and start bit
+reg p1;
+reg gerr; // global error status
+reg perr; // parity error
+reg ferr = 1'b0; // framing error
+wire bz; // break detected
+reg state; // state machine
+reg wf; // fifo write
+wire empty;
+reg didRd;
+
+assign ack = cyc & cs;
+wire pe_rd;
+edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & ~wr), .pe(pe_rd), .ne(), .ee());
+
+assign bitStream = rx_data[10];
+assign bz = t4==8'd0;
+wire rdf = fifoEnable ? pe_rd : wf;
+
+uart6551Fifo #(.WID(11)) uf1
+(
+ .clk(clk),
+ .rst(rst|clear|fifoClear),
+ .wr(wf),
+ .rd(rdf),
+ .din({bz,perr,ferr,t4}),
+ .dout({break_o,parityErr,frameErr,dout}),
+ .ctr(qcnt),
+ .full(full),
+ .empty(empty)
+);
+
+// compute 1/2 the length of the last bit
+// needed for framing error detection
+reg [7:0] halfLastBit;
+always @(stop_bits)
+if (stop_bits==3'd3) // 1.5 stop bits ?
+ halfLastBit <= 8'd4;
+else
+ halfLastBit <= 8'd8;
+
+// record a global error status
+always @(posedge clk)
+if (rst)
+ gerr <= 0;
+else begin
+ if (clearGErr)
+ gerr <= perr | ferr | bz;
+ else
+ gerr <= gerr | perr | ferr | bz;
+end
+
+
+// strip off stop bits
+always @(stop_bits or rx_data)
+if (stop_bits==3'd2)
+ t2 <= rx_data[9:0];
+else
+ t2 <= {rx_data[8:0],1'b0};
+
+// grab the parity bit
+always @(t2)
+ p1 <= t2[33];
+
+// strip off parity and start bit
+always @(parityCtrl or t2)
+if (parityCtrl[0])
+ t3 <= t2[8:1];
+else
+ t3 <= t2[9:2];
+
+// mask receive data for word length
+// depending on the word length, the first few bits in the
+// recieve shift register will be invalid because the shift
+// register shifts from MSB to LSB and shorter frames
+// won't shift as far towards the LSB.
+always @(wordLength or t3)
+ t4 <= t3 >> (4'd8 - wordLength);
+
+// detect a parity err
+always @(parityCtrl or t4 or p1) begin
+ case (parityCtrl)
+ 3'b001: perr <= p1 != ~^t4; // odd parity
+ 3'b011: perr <= p1 != ^t4; // even parity
+ default: perr <= 0;
+ endcase
+end
+
+
+// Three stage synchronizer to synchronize incoming data to
+// the local clock (avoids metastability).
+
+reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops
+reg rxdsmp; // majority samples
+reg rdxstart; // for majority style sample solid 3tik-wide sample
+reg [1:0] rxdsum [0:1];
+always @(posedge clk)
+if (baud16x_ce) begin
+ rxdd <= {rxdd[4:0],rxd};
+ if (SamplerStyle == 0) begin
+ rxdsmp <= rxdd[3];
+ rdxstart <= rxdd[4]&~rxdd[3];
+ end
+ else begin
+ rxdsum[1] <= rxdsum[0];
+ rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]};
+ rxdsmp <= rxdsum[1] > 2'd1;
+ rdxstart <= (rxdsum[0] == 2'b00) & (rxdsum[1] == 2'b11);
+ end
+end
+
+
+always @(posedge clk)
+if (rst)
+ state <= `IDLE;
+else begin
+ if (clear)
+ state <= `IDLE;
+ else if (baud16x_ce) begin
+ case (state)
+ // Sit in the idle state until a start bit is
+ // detected.
+ `IDLE:
+ if (rdxstart)
+ state <= `CNT;
+ `CNT:
+ begin
+ // Switch back to the idle state a little
+ // bit too soon.
+ if (cnt[7:2]==frameSize[7:2])
+ state <= `IDLE;
+ // On start bit check make sure the start
+ // bit is low, otherwise go back to the
+ // idle state because it's a false start.
+ if (cnt[7:0]==8'h07) begin
+ if (rxdsmp)
+ state <= `IDLE;
+ end
+ end
+ default: ;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ cnt <= 8'h00;
+else begin
+ if (clear)
+ cnt <= 8'h00;
+ else if (baud16x_ce) begin
+ cnt <= cnt + 8'h1;
+ case (state)
+ `IDLE:
+ begin
+ // reset counter on read of reciever
+ // (resets timeout count).
+ if (didRd)
+ cnt <= 8'h0;
+ if (rdxstart)
+ cnt <= 8'h0;
+ end
+ default: ;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ wf <= 1'b0;
+else begin
+ // Clear write flag
+ wf <= 1'b0;
+ if (clear)
+ wf <= 1'b0;
+ else if (baud16x_ce) begin
+ case (state)
+ `CNT:
+ // End of the frame ?
+ // - write data to fifo
+ if (cnt[7:0]==frameSize-halfLastBit) begin
+ if (!full)
+ wf <= 1'b1;
+ end
+ default: ;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ didRd <= 1'b0;
+else begin
+ // set a read flag for later reference
+ if (pe_rd)
+ didRd <= 1'b1;
+ if (clear)
+ didRd <= 1'b0;
+ else if (baud16x_ce) begin
+ case (state)
+ `IDLE:
+ begin
+ if (didRd)
+ didRd <= 1'b0;
+ if (rdxstart)
+ didRd <= 1'b0;
+ end
+ default: ;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ rx_data <= 11'h0;
+else begin
+ if (clear)
+ rx_data <= 11'h0;
+ else if (baud16x_ce) begin
+ case (state)
+ `CNT:
+ begin
+ //if (cnt[7:2]==frameSize[7:2])
+ // rx_data <= 11'h0;
+ if (cnt[3:0]==4'h7)
+ rx_data <= {rxdsmp,rx_data[10:1]};
+ end
+ default: ;
+ endcase
+ end
+end
+
+// Overrun: trying to recieve data when recieve buffer is already full.
+always @(posedge clk)
+if (rst)
+ overrun <= 1'b0;
+else begin
+ if (!full)
+ overrun <= 1'b0;
+ if (clear)
+ overrun <= 1'b0;
+ else if (baud16x_ce) begin
+ case (state)
+ `CNT:
+ if (cnt[7:0]==frameSize-halfLastBit) begin
+ if (full)
+ overrun <= 1'b1;
+ end
+ default: ;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ ferr <= 1'b0;
+else begin
+ if (clear)
+ ferr <= 1'b0;
+ else if (baud16x_ce) begin
+ case (state)
+ `CNT:
+ if (cnt[7:0]==frameSize-halfLastBit)
+ ferr <= ~rxdsmp;
+ default: ;
+ endcase
+ end
+end
+
+endmodule
+
Index: trunk/trunk/rtl/uart6551Tx.sv
===================================================================
--- trunk/trunk/rtl/uart6551Tx.sv (nonexistent)
+++ trunk/trunk/rtl/uart6551Tx.sv (revision 2)
@@ -0,0 +1,229 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2004-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ============================================================================
+//
+`define IDLE 0
+`define CNT 1
+
+module uart6551Tx(rst, clk, cyc, cs, wr, din, ack,
+ fifoEnable, fifoClear, txBreak,
+ frameSize, wordLength, parityCtrl, baud16x_ce,
+ cts, clear, txd, full, empty, qcnt);
+
+input rst;
+input clk;
+input cyc; // bus cycle valid
+input cs; // core select
+input wr; // write transmitter
+input [7:0] din; // fifo data in
+output ack;
+
+input fifoEnable;
+input fifoClear;
+input txBreak;
+input [7:0] frameSize;
+input [3:0] wordLength;
+input [2:0] parityCtrl;
+input baud16x_ce; // baud rate clock enable
+input cts; // clear to send
+input clear; // clear transmitter
+output reg txd; // external serial output
+output full; // fifo is full
+output empty; // fifo is empty
+output [3:0] qcnt; // number of characters queued
+
+reg [7:0] t1;
+reg [11:0] t2;
+reg [11:0] tx_data; // transmit data working reg (raw)
+reg state; // state machine state
+reg [7:0] cnt; // baud clock counter
+reg rd;
+reg p1, p2; // parity bit
+
+assign ack = cyc & cs;
+edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee());
+
+`ifdef UART_NO_TX_FIFO
+reg [7:0] fdo;
+reg empty;
+
+always @(posedge clk)
+ if (awr) fdo <= {3'd0,din};
+
+always @(posedge clk)
+ begin
+ if (awr) empty <= 0;
+ else if (rd) empty <= 1;
+ end
+
+assign full = ~empty;
+`else
+// generate an empty signal for when the fifo is disabled
+reg fempty2;
+always @(posedge clk)
+ if (rst)
+ fempty2 <= 1;
+ else begin
+ if (awr) fempty2 <= 0;
+ else if (rd) fempty2 <= 1;
+ end
+
+
+wire [7:0] fdo; // fifo data output
+wire rdf = fifoEnable ? rd : awr;
+wire fempty;
+wire ffull;
+uart6551Fifo #(.WID(8)) fifo0
+(
+ .clk(clk),
+ .rst(rst|clear|fifoClear),
+ .din(din),
+ .wr(awr),
+ .rd(rdf),
+ .dout(fdo),
+ .full(ffull),
+ .empty(fempty),
+ .ctr(qcnt)
+);
+assign empty = fifoEnable ? fempty : fempty2;
+assign full = fifoEnable ? ffull : ~fempty2;
+`endif
+
+
+// mask transmit data for word length
+// this mask is needed for proper parity generation
+integer n;
+reg [7:0] mask;
+always @*
+ for (n = 0; n < 8; n = n + 1)
+ mask[n] = n < wordLength ? 1'b1 : 1'b0;
+
+always @*
+if (txBreak)
+ t1 <= 0;
+else
+ t1 <= fdo & mask;
+
+
+// compute parity bit
+always @*
+begin
+ case (parityCtrl)
+ 3'b001: p1 <= ~^t1;// odd parity
+ 3'b011: p1 <= ^t1; // even parity
+ 3'b101: p1 <= 1; // mark bit
+ 3'b111: p1 <= 0; // space bit
+ default: p1 <= 1; // stop bit when no parity
+ endcase
+end
+
+/*
+Could pipeline this, but then watch out for empty signal control
+always @(posedge clk)
+ if (ce) t2 <= t1;
+
+always @(posedge clk)
+ if (ce) p2 <= p1;
+*/
+// Insert start, parity bit and stop
+always @*
+case(wordLength)
+4'd5: t2 <= {5'b11111,p1,t1[4:0],1'b0};
+4'd6: t2 <= {4'b1111,p1,t1[5:0],1'b0};
+4'd7: t2 <= {3'b111,p1,t1[6:0],1'b0};
+default: t2 <= {2'b11,p1,t1[7:0],1'b0};
+endcase
+
+always @(posedge clk)
+if (rst)
+ state <= `IDLE;
+else begin
+ if (clear)
+ state <= `IDLE;
+ if (baud16x_ce) begin
+ case(state)
+ `IDLE:
+ if ((!empty && cts)||txBreak)
+ state <= `CNT;
+ `CNT:
+ if (cnt==frameSize)
+ state <= `IDLE;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ cnt <= 8'h00;
+else begin
+ if (clear)
+ cnt <= 8'h00;
+ if (baud16x_ce) begin
+ case(state)
+ `IDLE:
+ cnt <= 8'h00;
+ `CNT:
+ cnt <= cnt + 8'd1;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ rd <= 0;
+else begin
+ rd <= 0;
+ if (clear)
+ rd <= 0;
+ if (baud16x_ce) begin
+ case(state)
+ `IDLE:
+ if ((!empty && cts)||txBreak)
+ rd <= 1;
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ tx_data <= 12'hFFF;
+else begin
+ if (baud16x_ce) begin
+ case(state)
+ `IDLE:
+ if ((!empty && cts)||txBreak)
+ tx_data <= t2;
+ `CNT:
+ // Shift the data out. LSB first.
+ if (cnt[3:0]==4'hF)
+ tx_data <= {1'b1,tx_data[11:1]};
+ endcase
+ end
+end
+
+always @(posedge clk)
+if (rst)
+ txd <= 1'b1;
+else
+ txd <= tx_data[0];
+
+endmodule
Index: trunk/trunk/rtl/vtdl.sv
===================================================================
--- trunk/trunk/rtl/vtdl.sv (nonexistent)
+++ trunk/trunk/rtl/vtdl.sv (revision 2)
@@ -0,0 +1,67 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2007-2019 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+// vtdl - variable tap delay line
+// (dynamic shift register)
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see .
+//
+// ============================================================================
+//
+// Notes:
+//
+// This module acts like a clocked delay line with a variable tap.
+// Miscellaneous usage in rate control circuitry such as fifo's.
+// Capable of delaying a signal bus.
+// Signal bus width is specified with the WID parameter.
+//
+// SystemVerilog
+// =============================================================================
+//
+//`define SIM
+
+module vtdl(clk, ce, a, d, q);
+parameter WID = 8;
+parameter DEP = 16;
+localparam AMSB = $clog2(DEP)-1;
+input clk;
+input ce;
+input [AMSB:0] a;
+input [WID-1:0] d;
+output [WID-1:0] q;
+
+reg [WID-1:0] m [DEP-1:0];
+integer n;
+
+`ifdef SIM
+initial begin
+ for (n = 0; n < DEP; n = n + 1)
+ m[n] = {WID{1'b0}};
+end
+`endif
+
+always @(posedge clk)
+ if (ce) begin
+ for (n = 1; n < DEP; n = n + 1)
+ m[n] <= m[n-1];
+ m[0] <= d;
+ end
+
+assign q = m[a];
+
+endmodule
Index: trunk/trunk/software/README.md
===================================================================
--- trunk/trunk/software/README.md (nonexistent)
+++ trunk/trunk/software/README.md (revision 2)
@@ -0,0 +1,5 @@
+# uart6551demo.asm
+
+This program demonstrates the use of the uart6551. It is written for a risc processor.
+
+
Index: trunk/trunk/software/uart6551demo.asm
===================================================================
--- trunk/trunk/software/uart6551demo.asm (nonexistent)
+++ trunk/trunk/software/uart6551demo.asm (revision 2)
@@ -0,0 +1,138 @@
+XON equ $11
+XOFF equ $13
+LEDS equ $FFDC0600
+UART equ $FFDC0A00
+
+ code 18 bits
+ org $FFFC0000
+start:
+ ldi $sp,#$80000-4 ; setup system mode stack pointer
+ ; Switch to user mode
+.0004:
+ eret
+ ; When an ECALL instruction is executed it'll start here.
+ bra .0004
+
+;------------------------------------------------------------------------------
+; User mode code starts here
+;------------------------------------------------------------------------------
+ org $FFFC0100
+
+ ldi $sp,#$80000-1028 ; setup user mode stack pointer
+ add $t0,$x0,#$AB ; turn on the LED
+ stt $t0,LEDS
+ call SerialInit
+ ldi $t2,#16 ; send an XON just in case
+ ldi $a0,#XON
+.0004:
+ call SerialPutChar
+ sub $t2,$t2,#1
+ bne $t2,$x0,.0004
+ ldi $a0,#'A' ; Try sending the letter 'A'
+ call SerialPutChar
+.0002:
+ ldi $a0,#msgStart ; spit out a startup message
+ call SerialPutString
+
+ ; Now a loop to recieve and echo back characters
+.0003:
+ call SerialPeekChar
+ blt $v0,$x0,.0003
+ mov $a0,$v0
+ call SerialPutChar
+ bra .0003
+
+;------------------------------------------------------------------------------
+; SerialPeekChar
+;
+; Check the serial port status to see if there's a char available. If there's
+; a char available then return it.
+;
+; Modifies:
+; $t0
+; Returns:
+; $v0 = character or -1
+;------------------------------------------------------------------------------
+
+SerialPeekChar:
+ ldb $t0,UART+4
+ and $t0,$t0,#8 ; look for Rx not empty
+ beq $t0,$x0,.0001
+ ldb $v0,UART
+ ret
+.0001:
+ ldi $v0,#-1
+ ret
+
+;------------------------------------------------------------------------------
+; SerialPutChar
+; Put a character to the serial transmitter. This routine blocks until the
+; transmitter is empty.
+;
+; Parameters:
+; $a0 = character to put
+; Modifies:
+; $t0
+;------------------------------------------------------------------------------
+
+SerialPutChar:
+.0001:
+ ldb $t0,UART+4 ; wait until the uart indicates tx empty
+ and $t0,$t0,#16 ; bit #4 of the status reg
+ beq $t0,$x0,.0001 ; branch if transmitter is not empty
+ stb $a0,UART ; send the byte
+ ret
+
+;------------------------------------------------------------------------------
+; SerialPutString
+; Put a string of characters to the serial transmitter. Calls the
+; SerialPutChar routine, so this routine also blocks if the transmitter is not
+; empty.
+;
+; Parameters:
+; $a0 = pointer to null terminated string to put
+; Modifies:
+; $t0 and $t1
+; Stack Space:
+; 2 words
+;------------------------------------------------------------------------------
+
+SerialPutString:
+ sub $sp,$sp,#8 ; save link register
+ stt $ra,[$sp]
+ stt $a0,4[$sp] ; and argument
+ mov $t1,$a0 ; t1 = pointer to string
+.0001:
+ ldb $a0,[$t1]
+ add $t1,$t1,#1 ; advance pointer to next byte
+ beq $a0,$x0,.done ; branch if done
+ call SerialPutChar ; output character
+ bra .0001
+.done:
+ ldt $ra,[$sp] ; restore return address
+ ldt $a0,4[$sp] ; and argument
+ add $sp,$sp,#8
+ ret
+
+;------------------------------------------------------------------------------
+; Initialize serial port.
+;
+; Modifies:
+; $t0
+;------------------------------------------------------------------------------
+
+SerialInit:
+ ldi $t0,#$0B ; dtr,rts active, rxint disabled, no parity
+ stt $t0,UART+8
+ ldi $t0,#$08070012 ; reset the fifo's
+ stt $t0,UART+12
+ ldi $t0,#$08010012 ; baud 115200, 1 stop bit, 8 bit, internal baud gen
+ stt $t0,UART+12
+ ret
+
+;------------------------------------------------------------------------------
+; Message strings
+;------------------------------------------------------------------------------
+
+msgStart:
+ db "uart6551 Demo Starting.",13,10,0
Index: trunk/README.md
===================================================================
--- trunk/README.md (nonexistent)
+++ trunk/README.md (revision 2)
@@ -0,0 +1,13 @@
+# uart6551
+
+uart6551 is a 6551 register compatible uart core.
+uart6551 is a 32-bit peripheral device which may also be used as an eight-bit peripheral.
+The uart contains just four 32-bit registers. The low order eight bits of the register set are 6551 compatible.
+The upper 24-bits of registers represent an extension to the 6551 register set.
+An additional baud-rate selector bit is present which allows the selection of a few more higher baud-rates.
+There are also 16 entry transmit and recieve fifos.
+
+## Status
+
+The core has been tried in an FPGA at 9,600 and 115,200 baud and appears to work.
+