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/trunk/trunk/doc/uart6551_x12.docx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
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n +0000059016 00000 n +0000117615 00000 n +0000118030 00000 n +0000118519 00000 n +0000118776 00000 n +0000118805 00000 n +0000121978 00000 n +0000122025 00000 n +trailer +<<967C638921CBF24ABD4798F77140FC2A>] >> +startxref +124685 +%%EOF +xref +0 0 +trailer +<<967C638921CBF24ABD4798F77140FC2A>] /Prev 124685/XRefStm 122025>> +startxref +150927 +%%EOF \ No newline at end of file Index: trunk/trunk/doc/uart6551x12_WBC.txt =================================================================== --- trunk/trunk/doc/uart6551x12_WBC.txt (nonexistent) +++ trunk/trunk/doc/uart6551x12_WBC.txt (revision 5) @@ -0,0 +1,35 @@ + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |WISHBONE Datasheet + |WISHBONE SoC Architecture Specification, Revision B.3 + | + |Description: Specifications: + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |General Description: UART core + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |Supported Cycles: SLAVE,READ/WRITE + | SLAVE,BLOCK READ/WRITE + | SLAVE,RMW + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |Data port, size: 12 bit + |Data port, granularity: 12 bit + |Data port, maximum operand size: 12 bit + |Data transfer ordering: Undefined + |Data transfer sequencing: Undefined + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |Clock frequency constraints: 40MHz for proper baud lookup + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |Supported signal list and Signal Name WISHBONE equiv. + |cross reference to equivalent ack_o ACK_O + |WISHBONE signals adr_i[3:0] ADR_I() + | clk_i CLK_I + | rst_i RST_I() + | dat_i(11:0) DAT_I() + | dat_o(11:0) DAT_O() + | cyc_i CYC_I + | stb_i STB_I + | we_i WE_I + | + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + |Special requirements: + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + Index: trunk/trunk/rtl/uart6551Rx_x12.sv =================================================================== --- trunk/trunk/rtl/uart6551Rx_x12.sv (nonexistent) +++ trunk/trunk/rtl/uart6551Rx_x12.sv (revision 5) @@ -0,0 +1,379 @@ +// ============================================================================ +// __ +// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +`define IDLE 0 +`define CNT 1 + +module uart6551Rx_x12(rst, clk, + cyc, cs, wr, dout, ack, + fifoEnable, fifoClear, clearGErr, + parityCtrl, frameSize, stop_bits, wordLength, baud16x_ce, clear, rxd, + full, empty, frameErr, overrun, parityErr, break_o, gerr, qcnt, cnt, bitStream); +input rst; +input clk; +input cyc; // valid bus cycle +input cs; // core select +input wr; // read reciever +output [11:0] dout; // fifo data out +output ack; +input fifoEnable; // enable the fifo +input fifoClear; +input clearGErr; // clear global error +input [2:0] parityCtrl; +input [8:0] frameSize; // frame count +input [2:0] stop_bits; +input [3:0] wordLength; +input baud16x_ce; // baud rate clock enable +input clear; // clear reciever +input rxd; // external serial input +output full; // receive fifo full +output empty; // receiver fifo is empty +output frameErr; // framing error +output overrun; // receiver overrun +output parityErr; // parity error +output break_o; // break detected +output gerr; // global error indicator +output [3:0] qcnt; // count of number of words queued +output [10:0] cnt; // receiver counter +output bitStream; // received bit stream + +//0 - simple sampling at middle of symbol period +//>0 - sampling of 3 middle ticks of sumbol perion and results as majority +parameter SamplerStyle = 0; + + +reg overrun; +reg [10:0] cnt; // sample bit rate counter / timeout counter +reg [14:0] rx_data; // working receive data register +reg [13:0] t4; // data minus stop bit(s) +reg [11:0] t3; // data minus parity bit and start bit +reg [11:0] t5; +reg [3:0] shft_amt; +reg p1; +reg gerr; // global error status +reg perr; // parity error +reg ferr = 1'b0; // framing error +wire bz; // break detected +reg state; // state machine +reg wf; // fifo write +wire empty; +reg didRd; +wire [11:0] dout1; +reg full1; +wire fifoFull, fifoEmpty; + +assign ack = cyc & cs; +wire pe_rd, pe_wf; +edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & ~wr), .pe(pe_rd), .ne(), .ee()); +edge_det ued2 (.rst(rst), .clk(clk), .ce(1'b1), .i(wf), .pe(pe_wf), .ne(), .ee()); + +assign bitStream = rx_data[14]; +assign bz = t3==12'd0; +wire rdf = fifoEnable ? pe_rd : pe_wf; + +uart6551Fifo #(.WID(15)) uf1 +( + .clk(clk), + .rst(rst|clear|fifoClear), + .wr(wf), + .rd(rdf), + .din({bz,perr,ferr,t3}), + .dout({break_o,parityErr,frameErr,dout1}), + .ctr(qcnt), + .full(fifoFull), + .empty(fifoEmpty) +); + +assign dout = fifoEnable ? dout1 : t5; +assign empty = fifoEnable ? fifoEmpty : ~full1; +assign full = fifoEnable ? fifoFull : full1; + +// compute 1/2 the length of the last bit +// needed for framing error detection +reg [8:0] halfLastBit; +always_ff @(posedge clk) +if (stop_bits==3'd3) // 1.5 stop bits ? + halfLastBit <= 9'd8; +else + halfLastBit <= 9'd16; + +reg [8:0] fhb; +always_ff @(posedge clk) + fhb <= frameSize-halfLastBit; + +// record a global error status +always_ff @(posedge clk) +if (rst) + gerr <= 0; +else begin + if (clearGErr) + gerr <= perr | ferr | bz; + else + gerr <= gerr | perr | ferr | bz; +end + + +// right align data for word length, strip start bit +// depending on the word length, the first few bits in the +// recieve shift register will be invalid because the shift +// register shifts from MSB to LSB and shorter frames +// won't shift as far towards the LSB. +always_ff @(posedge clk) + shft_amt <= (5'd16 - (wordLength + ({stop_bits[3],~stop_bits[3]}) + parityCtrl[0])); +always_comb + t4 <= rx_data >> shft_amt; + +// grab the parity bit +// Note the data is right aligned +always_comb + p1 <= t4[wordLength]; + +// strip off parity, stop +integer n2; +always_comb + for (n2 = 0; n2 < 12; n2 = n2 + 1) + if (n2 < wordLength) + t3[n2] <= t4[n2]; + else + t3[n2] <= 1'b0; + +// detect a parity err +always_comb begin + case (parityCtrl) + 3'b001: perr <= p1 != ~^t3; // odd parity + 3'b011: perr <= p1 != ^t3; // even parity + default: perr <= 0; + endcase +end + + +// Three stage synchronizer to synchronize incoming data to +// the local clock (avoids metastability). + +reg [5:0] rxdd /* synthesis ramstyle = "logic" */; // synchronizer flops +reg rxdsmp; // majority samples +reg rdxstart; // for majority style sample solid 3tik-wide sample +reg [1:0] rxdsum [0:1]; +always_ff @(posedge clk) +if (baud16x_ce) begin + rxdd <= {rxdd[4:0],rxd}; + if (SamplerStyle == 0) begin + rxdsmp <= rxdd[3]; + rdxstart <= rxdd[4]&~rxdd[3]; + end + else begin + rxdsum[1] <= rxdsum[0]; + rxdsum[0] <= {1'b0,rxdd[3]} + {1'b0,rxdd[4]} + {1'b0,rxdd[5]}; + rxdsmp <= rxdsum[1] > 2'd1; + rdxstart <= (rxdsum[0] == 2'b00) & (rxdsum[1] == 2'b11); + end +end + + +always_ff @(posedge clk) +if (rst) + state <= `IDLE; +else begin + if (clear) + state <= `IDLE; + else if (baud16x_ce) begin + case (state) + // Sit in the idle state until a start bit is + // detected. + `IDLE: + if (rdxstart) + state <= `CNT; + `CNT: + begin + // Switch back to the idle state a little + // bit too soon. + if (cnt[8:2]==frameSize[8:2]) + state <= `IDLE; + // On start bit check make sure the start + // bit is low, otherwise go back to the + // idle state because it's a false start. + if (cnt[8:0]==8'h07) begin + if (rxdsmp) + state <= `IDLE; + end + end + endcase + end +end + +always_ff @(posedge clk) +if (rst) + cnt <= 9'h00; +else begin + if (clear) + cnt <= 9'h00; + else if (baud16x_ce) begin + cnt <= cnt + 2'h1; + case (state) + `IDLE: + begin + // reset counter on read of reciever + // (resets timeout count). + if (didRd) + cnt <= 9'h0; + if (rdxstart) + cnt <= 9'h0; + end + default: ; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + wf <= 1'b0; +else begin + // Clear write flag + wf <= 1'b0; + if (baud16x_ce) begin + case (state) + `CNT: + // End of the frame ? + // - write data to fifo + if (cnt[8:0]==fhb) begin + if (!full) + wf <= 1'b1; + end + default: ; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + t5 <= 1'b0; +else begin + if (pe_wf) + t5 <= t3; +end + +always_ff @(posedge clk) +if (rst) + full1 <= 1'b0; +else begin + if (pe_wf) + full1 <= 1'b1; + else if (pe_rd) + full1 <= 1'b0; +end + +always_ff @(posedge clk) +if (rst) + didRd <= 1'b0; +else begin + // set a read flag for later reference + if (pe_rd) + didRd <= 1'b1; + if (clear) + didRd <= 1'b0; + else if (baud16x_ce) begin + case (state) + `IDLE: + begin + if (didRd) + didRd <= 1'b0; + if (rdxstart) + didRd <= 1'b0; + end + default: ; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + rx_data <= 15'h0; +else begin + if (clear) + rx_data <= 15'h0; + else if (baud16x_ce) begin + case (state) + `CNT: + begin + //if (cnt[7:2]==frameSize[7:2]) + // rx_data <= 11'h0; + if (cnt[3:0]==4'h7) + rx_data <= {rxdsmp,rx_data[14:1]}; + end + default: ; + endcase + end +end + +// Overrun: trying to recieve data when recieve buffer is already full. +always_ff @(posedge clk) +if (rst) + overrun <= 1'b0; +else begin + if (!full) + overrun <= 1'b0; + if (clear) + overrun <= 1'b0; + else if (baud16x_ce) begin + case (state) + `CNT: + if (cnt[8:0]==fhb) begin + if (full) + overrun <= 1'b1; + end + default: ; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + ferr <= 1'b0; +else begin + if (clear) + ferr <= 1'b0; + else if (baud16x_ce) begin + case (state) + `CNT: + if (cnt[8:0]==fhb) + ferr <= ~rxdsmp; + default: ; + endcase + end +end + +endmodule + Index: trunk/trunk/rtl/uart6551Tx_x12.sv =================================================================== --- trunk/trunk/rtl/uart6551Tx_x12.sv (nonexistent) +++ trunk/trunk/rtl/uart6551Tx_x12.sv (revision 5) @@ -0,0 +1,254 @@ +// ============================================================================ +// __ +// \\__/ o\ (C) 2004-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +`define IDLE 0 +`define CNT 1 + +//`define UART_NO_TX_FIFO 1'b1 + +module uart6551Tx_x12 (rst, clk, cyc, cs, wr, din, ack, + fifoEnable, fifoClear, txBreak, + frameSize, wordLength, parityCtrl, baud16x_ce, + cts, clear, txd, full, empty, qcnt); + +input rst; +input clk; +input cyc; // bus cycle valid +input cs; // core select +input wr; // write transmitter +input [11:0] din; // fifo data in +output ack; + +input fifoEnable; +input fifoClear; +input txBreak; +input [8:0] frameSize; +input [3:0] wordLength; +input [2:0] parityCtrl; +input baud16x_ce; // baud rate clock enable +input cts; // clear to send +input clear; // clear transmitter +output reg txd; // external serial output +output full; // fifo is full +output empty; // fifo is empty +output [3:0] qcnt; // number of characters queued + +reg [11:0] t1; +reg [15:0] t2; +reg [15:0] tx_data; // transmit data working reg (raw) +reg state; // state machine state +reg [8:0] cnt; // baud clock counter +reg rd; +reg p1, p2; // parity bit + +assign ack = cyc & cs; +edge_det ued1 (.rst(rst), .clk(clk), .ce(1'b1), .i(ack & wr), .pe(awr), .ne(), .ee()); + +`ifdef UART_NO_TX_FIFO +reg [11:0] fdo2; +reg empty; + +always_ff @(posedge clk) + if (awr) fdo2 <= {3'd0,din}; + +always_ff @(posedge clk) + begin + if (awr) empty <= 0; + else if (rd) empty <= 1; + end + +assign full = ~empty; +wire [11:0] fdo = fdo2; +`else +reg [11:0] fdo2; +always_ff @(posedge clk) + if (awr) fdo2 <= {3'd0,din}; +// generate an empty signal for when the fifo is disabled +reg fempty2; +always_ff @(posedge clk) + if (rst) + fempty2 <= 1; + else begin + if (awr) fempty2 <= 0; + else if (rd) fempty2 <= 1; + end + + +wire [11:0] fdo1; // fifo data output +wire rdf = fifoEnable ? rd : awr; +wire fempty; +wire ffull; +uart6551Fifo #(.WID(12)) fifo0 +( + .clk(clk), + .rst(rst|clear|fifoClear), + .din(din), + .wr(awr), + .rd(rdf), + .dout(fdo1), + .full(ffull), + .empty(fempty), + .ctr(qcnt) +); +assign empty = fifoEnable ? fempty : fempty2; +assign full = fifoEnable ? ffull : ~fempty2; +wire [11:0] fdo = fifoEnable ? fdo1 : fdo2; +`endif + +// mask transmit data for word length +// this mask is needed for proper parity generation +integer n; +reg [11:0] mask; +always @* + for (n = 0; n < 12; n = n + 1) + mask[n] = n < wordLength ? 1'b1 : 1'b0; + +always_comb +if (txBreak) + t1 <= 0; +else + t1 <= fdo & mask; + + +// compute parity bit +always_comb +begin + case (parityCtrl) + 3'b001: p1 <= ~^t1;// odd parity + 3'b011: p1 <= ^t1; // even parity + 3'b101: p1 <= 1; // mark bit + 3'b111: p1 <= 0; // space bit + default: p1 <= 1; // stop bit when no parity + endcase +end + +/* +Could pipeline this, but then watch out for empty signal control +always @(posedge clk) + if (ce) t2 <= t1; + +always @(posedge clk) + if (ce) p2 <= p1; +*/ +// Insert start, parity bit and stop +always_comb +case(wordLength) +4'd4: t2 <= {10'h3FF,p1,t1[3:0],1'b0}; +4'd5: t2 <= {9'h1FF,p1,t1[4:0],1'b0}; +4'd6: t2 <= {8'hFF,p1,t1[5:0],1'b0}; +4'd7: t2 <= {7'h7F,p1,t1[6:0],1'b0}; +4'd8: t2 <= {6'h3F,p1,t1[7:0],1'b0}; +4'd9: t2 <= {5'b11111,p1,t1[8:0],1'b0}; +4'd10: t2 <= {4'b1111,p1,t1[9:0],1'b0}; +4'd11: t2 <= {3'b111,p1,t1[10:0],1'b0}; +4'd12: t2 <= {2'b11,p1,t1[11:0],1'b0}; +default: t2 <= {6'h3F,p1,t1[7:0],1'b0}; +endcase + +always_ff @(posedge clk) +if (rst) + state <= `IDLE; +else begin + if (clear) + state <= `IDLE; + if (baud16x_ce) begin + case(state) + `IDLE: + if ((!empty && cts)||txBreak) + state <= `CNT; + `CNT: + if (cnt==frameSize) + state <= `IDLE; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + cnt <= 9'h00; +else begin + if (clear) + cnt <= 9'h00; + if (baud16x_ce) begin + case(state) + `IDLE: + cnt <= 9'h00; + `CNT: + cnt <= cnt + 2'd1; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + rd <= 0; +else begin + rd <= 0; + if (clear) + rd <= 0; + if (baud16x_ce) begin + case(state) + `IDLE: + if ((!empty && cts)||txBreak) + rd <= 1; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + tx_data <= 16'hFFFF; +else begin + if (baud16x_ce) begin + case(state) + `IDLE: + if ((!empty && cts)||txBreak) + tx_data <= t2; + `CNT: + // Shift the data out. LSB first. + if (cnt[3:0]==4'hF) + tx_data <= {1'b1,tx_data[15:1]}; + endcase + end +end + +always_ff @(posedge clk) +if (rst) + txd <= 1'b1; +else + txd <= tx_data[0]; + +endmodule Index: trunk/trunk/rtl/uart6551_x12.sv =================================================================== --- trunk/trunk/rtl/uart6551_x12.sv (nonexistent) +++ trunk/trunk/rtl/uart6551_x12.sv (revision 5) @@ -0,0 +1,633 @@ +// ============================================================================ +// __ +// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo +// \ __ / All rights reserved. +// \/_// robfinch@finitron.ca +// || +// +// +// BSD 3-Clause License +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ============================================================================ +// +`define UART_TRB 4'd0 // transmit/receive buffer +`define UART_STAT 4'd1 +`define UART_CMD 4'd2 +`define UART_CTRL 4'd3 +`define UART_IRQS 4'd4 +`define UART_MS 4'd5 +`define UART_LS 4'd6 +`define UART_CMD1 4'd7 +`define UART_CMD2 4'd8 +`define UART_CMD3 4'd9 +`define UART_CTRL1 4'd10 +`define UART_CTRL2 4'd11 +`define UART_CTRL3 4'd12 +`define UART_CLK1 4'd13 +`define UART_CLK2 4'd14 + +module uart6551_x12 (rst_i, clk_i, cs_i, irq_o, + cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, + cts_ni, rts_no, dsr_ni, dcd_ni, dtr_no, ri_ni, + rxd_i, txd_o, data_present, + rxDRQ_o, txDRQ_o, + xclk_i, RxC_i +); +parameter pCounterBits = 24; +parameter pFifoSize = 1024; +parameter pClkDiv = 24'd1302; // 9.6k baud, 200.000MHz clock +parameter HIGH = 1'b1; +parameter LOW = 1'b0; +input rst_i; +input clk_i; // eg 50.000MHz +input cs_i; // circuit select +// WISHBONE ------------------------------- +input cyc_i; // bus cycle valid +input stb_i; +output ack_o; +input we_i; // 1 = write +input [3:0] adr_i; // register address +input [11:0] dat_i; // data input bus +output reg [11:0] dat_o; // data output bus +//------------------------------------------ +output reg irq_o; // interrupt request +input cts_ni; // clear to send - (flow control) active low +output reg rts_no; // request to send - (flow control) active low +input dsr_ni; // data set ready - active low +input dcd_ni; // data carrier detect - active low +output reg dtr_no; // data terminal ready - active low +input ri_ni; // ring indicator +input rxd_i; // serial data in +output txd_o; // serial data out +output data_present; +output rxDRQ_o; // reciever DMA request +output txDRQ_o; // transmitter DMA request +input xclk_i; // external clock source +input RxC_i; // external receiver clock source + +reg accessCD; // clock multiplier access flag +reg llb; // local loopback mode +reg dmaEnable; +// baud rate clock control +reg [4:0] baudRateSel; +reg selCD; // Use clock multiplier register +reg [pCounterBits-1:0] c; // current count +reg [pCounterBits-1:0] ckdiv; // baud rate clock divider +reg [pCounterBits-1:0] clkdiv; // clock multiplier register +reg [1:0] xclks; // synchronized external clock +reg [1:0] RxCs; // synchronized external receiver clock +reg baud16; // 16x baud rate clock +wire baud16rx; // reciever clock +reg xClkSrc; // uart baud clock is external +reg rxClkSrc; // receiver clock is external + +// frame format registers +reg [3:0] wordLength; +reg stopBit; +reg [2:0] stopBits; +reg [2:0] parityCtrl; +reg [8:0] frameSize; + +reg txBreak; // transmit a break + +wire rxFull; +wire rxEmpty; +wire txFull; +wire txEmpty; +reg hwfc; // hardware flow control enable +wire [11:0] lineStatusReg; +wire [11:0] modemStatusReg; +wire [11:0] irqStatusReg; +// interrupt +reg rxIe; +reg txIe; +reg modemStatusChangeIe; +wire modemStatusChange; +reg lineStatusChangeIe; +wire lineStatusChange; +reg rxToutIe; // receiver timeout interrupt enable +reg [3:0] rxThres; // receiver threshold for interrupt +reg [3:0] txThres; // transmitter threshold for interrupt +reg rxTout; // receiver timeout +wire [9:0] rxCnt; // reciever counter value +reg [7:0] rxToutMax; +reg [2:0] irqenc; // encoded irq cause +wire rxITrig; // receiver interrupt trigger level +wire txITrig; // transmitter interrupt trigger level +// reciever errors +wire parityErr; // reciever detected a parity error +wire frameErr; // receiver char framing error +wire overrun; // receiver over run +wire rxBreak; // reciever detected a break +wire rxGErr; // global error: there is at least one error in the reciever fifo +// modem controls +reg [1:0] ctsx; // cts_n sampling +reg [1:0] dcdx; +reg [1:0] dsrx; +reg [1:0] rix; +reg deltaCts; +reg deltaDcd; +reg deltaDsr; +reg deltaRi; + +// fifo +reg rxFifoClear; +reg txFifoClear; +reg fifoEnable; +wire [3:0] rxQued; +wire [3:0] txQued; + +// test +wire txd1; + +assign data_present = ~rxEmpty; + +assign rxITrig = rxQued >= rxThres; +assign txITrig = txQued <= txThres; +wire rxDRQ1 = (fifoEnable ? rxITrig : ~rxEmpty); +wire txDRQ1 = (fifoEnable ? txITrig : txEmpty); +assign rxDRQ_o = dmaEnable & rxDRQ1; +assign txDRQ_o = dmaEnable & txDRQ1; +wire rxIRQ = rxIe & rxDRQ1; +wire txIRQ = txIe & txDRQ1; + +reg [11:0] cmd0, cmd1, cmd2, cmd3; +reg [11:0] ctrl0, ctrl1, ctrl2, ctrl3; + +always_ff @(posedge clk_i) + irq_o <= + rxIRQ + | txIRQ + | (rxTout & rxToutIe) + | (lineStatusChange & lineStatusChangeIe) + | (modemStatusChange & modemStatusChangeIe) + ; + +// Hold onto address and data an extra cycle. +// The extra cycle updates or reads the serial transmit / receive. +reg [11:0] dati; +always_ff @(posedge clk_i) + dati <= dat_i; +reg [3:0] adr_h; +always_ff @(posedge clk_i) + adr_h <= adr_i; +reg we; +always_ff @(posedge clk_i) + we <= we_i; + +wire [11:0] rx_do; +wire rdrx = ack_o && adr_h==`UART_TRB && ~we; +wire txrx = ack_o && adr_h==`UART_TRB; + +wire cs = cs_i & cyc_i & stb_i; + +ack_gen #( + .READ_STAGES(1), + .WRITE_STAGES(0), + .REGISTER_OUTPUT(1) +) uag1 +( + .rst_i(rst_i), + .clk_i(clk_i), + .ce_i(1'b1), + .i(cs), + .we_i(cs & we), + .o(ack_o), + .rid_i(0), + .wid_i(0), + .rid_o(), + .wid_o() +); + +uart6551Rx_x12 uart_rx0 +( + .rst(rst_i), + .clk(clk_i), + .cyc(cyc_i), + .cs(rdrx), + .wr(we), + .dout(rx_do), + .ack(), + .fifoEnable(fifoEnable), + .fifoClear(rxFifoClear), + .clearGErr(1'b0), + .wordLength(wordLength), + .parityCtrl(parityCtrl), + .frameSize(frameSize), + .stop_bits(stopBits), + .baud16x_ce(baud16rx), + .clear(1'b0), + .rxd(llb ? txd1 : rxd_i), + .full(), + .empty(rxEmpty), + .frameErr(frameErr), + .overrun(overrun), + .parityErr(parityErr), + .break_o(rxBreak), + .gerr(rxGErr), + .qcnt(rxQued), + .cnt(rxCnt) +); + +uart6551Tx_x12 uart_tx0 +( + .rst(rst_i), + .clk(clk_i), + .cyc(cyc_i), + .cs(txrx), + .wr(we), + .din(dati), + .ack(), + .fifoEnable(fifoEnable), + .fifoClear(txFifoClear), + .txBreak(txBreak), + .frameSize(frameSize), // 16 x 10 bits + .wordLength(wordLength),// 8 bits + .parityCtrl(parityCtrl),// no parity + .baud16x_ce(baud16), + .cts(ctsx[1]|~hwfc), + .clear(clear), + .txd(txd1), + .full(txFull), + .empty(txEmpty), + .qcnt(txQued) +); + +assign txd_o = llb ? 1'b1 : txd1; + +assign lineStatusReg = {4'h0,rxGErr,1'b0,txFull,rxBreak,1'b0,1'b0,1'b0,1'b0}; +assign modemStatusChange = deltaDcd|deltaRi|deltaDsr|deltaCts; // modem status delta +assign modemStatusReg = {4'h0,1'b0,~rix[1],1'b0,~ctsx[1],deltaDcd, deltaRi, deltaDsr, deltaCts}; +assign irqStatusReg = {irq_o,3'b0,irq_o,2'b00,irqenc,2'b00}; + +// mux the reg outputs +always_ff @(posedge clk_i) +if (cs) begin + case(adr_h) + `UART_TRB: dat_o <= {4'h0,rx_do}; // receiver holding register + `UART_STAT: dat_o <= {irq_o,3'h0,irq_o,dsrx[1],dcdx[1],fifoEnable ? ~txFull : txEmpty,~rxEmpty,overrun,frameErr,parityErr}; + `UART_CMD: dat_o <= cmd0; + `UART_CTRL: dat_o <= ctrl0; + `UART_IRQS: dat_o <= irqStatusReg; + `UART_MS: dat_o <= modemStatusReg; + `UART_LS: dat_o <= lineStatusReg; + `UART_CMD1: dat_o <= cmd1; + `UART_CMD2: dat_o <= cmd2; + `UART_CMD3: dat_o <= cmd3; + `UART_CTRL1: dat_o <= ctrl1; + `UART_CTRL2: dat_o <= ctrl2; + `UART_CTRL3: dat_o <= ctrl3; + `UART_CLK1: dat_o <= clkdiv[23:12]; + `UART_CLK2: dat_o <= clkdiv[11: 0]; + default: dat_o <= 12'h0; + endcase +end +else + dat_o <= 12'h0; + + +// register updates +always_ff @(posedge clk_i) +if (rst_i) begin + rts_no <= HIGH; + dtr_no <= HIGH; + // interrupts + rxIe <= 1'b0; + txIe <= 1'b0; + modemStatusChangeIe <= 1'b0; + lineStatusChangeIe <= 1'b0; + hwfc <= 1'b0; + modemStatusChangeIe <= 1'b0; + lineStatusChangeIe <= 1'b0; + dmaEnable <= 1'b0; + // clock control + baudRateSel <= 5'h0; + rxClkSrc <= 1'b0; // ** 6551 defaults to zero (external receiver clock) + clkdiv <= pClkDiv; + // frame format + wordLength <= 4'd8; // 8 bits + stopBit <= 1'b0; // 1 stop bit + parityCtrl <= 3'd0; // no parity + + txBreak <= 1'b0; + // Fifo control + txFifoClear <= 1'b1; + rxFifoClear <= 1'b1; + fifoEnable <= 1'b1; + // Test + llb <= 1'b0; + selCD <= 1'b0; + accessCD <= 1'b0; +end +else begin + + //llb <= 1'b1; + rxFifoClear <= 1'b0; + txFifoClear <= 1'b0; + ctrl2[1] <= 1'b0; + ctrl2[2] <= 1'b0; + + if (cs & we) begin + case (adr_h) // synopsys full_case parallel_case + + `UART_TRB: ; + `UART_CLK2: clkdiv[11: 0] <= dati; + `UART_CLK1: clkdiv[23:12] <= dati; + + // Writing to the status register does a software reset of some bits. + `UART_STAT: + begin + dtr_no <= HIGH; + rxIe <= 1'b0; + rts_no <= HIGH; + txIe <= 1'b0; + txBreak <= 1'b0; + llb <= 1'b0; + end + `UART_CMD: + begin + cmd0 <= dati[7:0]; + dtr_no <= ~dati[0]; + rxIe <= ~dati[1]; + case(dati[3:2]) + 2'd0: begin rts_no <= 1'b1; txIe <= 1'b0; txBreak <= 1'b0; end + 2'd1: begin rts_no <= 1'b0; txIe <= 1'b1; txBreak <= 1'b0; end + 2'd2: begin rts_no <= 1'b0; txIe <= 1'b0; txBreak <= 1'b0; end + 2'd3: begin rts_no <= 1'b0; txIe <= 1'b0; txBreak <= 1'b1; end + endcase + llb <= dati[4]; + parityCtrl <= dati[7:5]; //000=none,001=odd,011=even,101=force 1,111 = force 0 + end + `UART_CMD1: + begin + cmd1 <= dati; + lineStatusChangeIe <= dati[0]; + modemStatusChangeIe <= dati[1]; + rxToutIe <= dati[2]; + end + `UART_CMD2: + cmd2 <= dati; + `UART_CMD3: + cmd3 <= dati; + + `UART_CTRL: + begin + ctrl0 <= dati; + baudRateSel[3:0] <= dati[3:0]; + rxClkSrc <= dati[4]; // 1 = baud rate generator, 0 = external + //11=5,10=6,01=7,00=8 + case({dati[8],dati[6:5]}) + 3'd0: wordLength <= 4'd8; + 3'd1: wordLength <= 4'd7; + 3'd2: wordLength <= 4'd6; + 3'd3: wordLength <= 4'd5; + 3'd4: wordLength <= 4'd12; + 3'd5: wordLength <= 4'd11; + 3'd6: wordLength <= 4'd10; + 3'd7: wordLength <= 4'd9; + endcase + stopBit <= dati[7]; //0=1,1=1.5 or 2 + end + `UART_CTRL1: + // Extended word length, values beyond 11 not supported. + ctrl1 <= dati; + `UART_CTRL2: + begin + ctrl2 <= dati; + fifoEnable <= dati[0]; + rxFifoClear <= dati[1]; + txFifoClear <= dati[2]; + case (dati[5:4]) + 2'd0: txThres <= 4'd1; // one-byte + 2'd1: txThres <= pFifoSize / 4; // one-quarter full + 2'd2: txThres <= pFifoSize / 2; // one-half full + 2'd3: txThres <= pFifoSize * 3 / 4; // three-quarters full + endcase + case (dati[7:6]) + 2'd0: rxThres <= 4'd1; // one-byte + 2'd1: rxThres <= pFifoSize / 4; // one-quarter full + 2'd2: rxThres <= pFifoSize / 2; // one-half full + 2'd3: rxThres <= pFifoSize * 3 / 4; // three quarters full + endcase + end + `UART_CTRL3: + begin + ctrl3 <= dati; + hwfc <= dati[0]; + dmaEnable <= dati[2]; + baudRateSel[4] <= dati[3]; + selCD <= dati[6]; + accessCD <= dati[7]; + end + default: + ; + endcase + end +end + +// ---------------------------------------------------------------------------- +// Baud rate control. +// ---------------------------------------------------------------------------- + +always_ff @(posedge clk_i) + xClkSrc <= baudRateSel==5'd0; + +wire [pCounterBits-1:0] bclkdiv; +uart6551BaudLUT #(pCounterBits) ublt1 (.a(baudRateSel), .o(bclkdiv)); + +reg [pCounterBits-1:0] clkdiv2; +always_ff @(posedge clk_i) + clkdiv2 <= selCD ? clkdiv : bclkdiv; + +always_ff @(posedge clk_i) +if (rst_i) + c <= 1'd1; +else begin + c <= c + 2'd1; + if (c >= clkdiv2) + c <= 2'd1; +end + +// for detecting an edge on the baud clock +wire ibaud16 = c == 2'd1; + +// Detect an edge on the external clock +wire xclkEdge; +edge_det ed1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(xclks[1]), .pe(xclkEdge), .ne() ); + +// Detect an edge on the external clock +wire rxClkEdge; +edge_det ed2(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(RxCs[1]), .pe(rxClkEdge), .ne() ); + +always_comb +if (xClkSrc) // 16x external clock (xclk) + baud16 <= xclkEdge; +else + baud16 <= ibaud16; + +assign baud16rx = rxClkSrc ? baud16 : rxClkEdge; + +//------------------------------------------------------------ +// external signal synchronization +//------------------------------------------------------------ + +// External receiver clock +always_ff @(posedge clk_i) + RxCs <= {RxCs[1:0],RxC_i}; + +// External baud clock +always_ff @(posedge clk_i) + xclks <= {xclks[1:0],xclk_i}; + + +always_ff @(posedge clk_i) + ctsx <= {ctsx[0],llb?~rts_no:~cts_ni}; + +always_ff @(posedge clk_i) + dcdx <= {dcdx[0],~dcd_ni}; + +always_ff @(posedge clk_i) + dsrx <= {dsrx[0],llb?~dtr_no:~dsr_ni}; + +always_ff @(posedge clk_i) + rix <= {rix[0],~ri_ni}; + +//------------------------------------------------------------ +// state change detectors +//------------------------------------------------------------ + +wire ne_stat; +edge_det ued3 ( + .rst(rst_i), + .clk(clk_i), + .ce(1'b1), + .i(ack_o && adr_i==`UART_MS && ~we_i), + .pe(), + .ne(ne_stat), + .ee() +); + +// detect a change on the dsr signal +always_ff @(posedge clk_i) +if (rst_i) + deltaDsr <= 1'b0; +else begin + if (ne_stat) + deltaDsr <= 0; + else if (~deltaDsr) + deltaDsr <= dsrx[1] ^ dsrx[0]; +end + +// detect a change on the dcd signal +always_ff @(posedge clk_i) +if (rst_i) + deltaDcd <= 1'b0; +else begin + if (ne_stat) + deltaDcd <= 0; + else if (~deltaDcd) + deltaDcd <= dcdx[1] ^ dcdx[0]; +end + +// detect a change on the cts signal +always_ff @(posedge clk_i) +if (rst_i) + deltaCts <= 1'b0; +else begin + if (ne_stat) + deltaCts <= 0; + else if (~deltaCts) + deltaCts <= ctsx[1] ^ ctsx[0]; +end + +// detect a change on the ri signal +always_ff @(posedge clk_i) +if (rst_i) + deltaRi <= 1'b0; +else begin + if (ne_stat) + deltaRi <= 0; + else if (~deltaRi) + deltaRi <= rix[1] ^ rix[0]; +end + +// detect a change in line status +reg [7:0] pLineStatusReg; +always_ff @(posedge clk_i) + pLineStatusReg <= lineStatusReg; + +assign lineStatusChange = pLineStatusReg != lineStatusReg; + +//----------------------------------------------------- + +// compute recieve timeout +always_comb + rxToutMax <= (wordLength << 2) + 6'd12; + +always_ff @(posedge clk_i) +if (rst_i) + rxTout <= 1'b0; +else begin + // read of receiver clears timeout counter + if (rdrx) + rxTout <= 1'b0; + // Don't time out if the fifo is empty + else if (rxCnt[9:4]==rxToutMax && ~rxEmpty) + rxTout <= 1'b1; +end + + +//----------------------------------------------------- +// compute the 2x number of stop bits +always_comb +if (stopBit==1'b0) // one stop bit + stopBits <= 3'd2; +else if (wordLength==4'd8 && parityCtrl != 3'd0) + stopBits <= 3'd2; +else if (wordLength==4'd5 && parityCtrl == 3'd0) // 5 bits - 1 1/2 stop bit + stopBits <= 3'd3; +else + stopBits <= 3'd4; // two stop bits + + +// compute frame size +// frame size is one less +always_ff @(posedge clk_i) + frameSize <= {wordLength + 4'd1 + stopBits[2:1] + parityCtrl[0], stopBits[0],3'b0} - 2'd1; + +//----------------------------------------------------- +// encode IRQ mailbox +always_comb + irqenc <= + lineStatusChange ? 3'd0 : + ~rxDRQ_o ? 3'd1 : + rxTout ? 3'd2 : + ~txDRQ_o ? 3'd3 : + modemStatusChange ? 3'd4 : + 3'd0; + +endmodule Index: trunk/trunk/software/README.md =================================================================== --- trunk/trunk/software/README.md (revision 4) +++ trunk/trunk/software/README.md (revision 5) @@ -2,4 +2,6 @@ This program demonstrates the use of the uart6551. It is written for a risc processor. +# serial.asm +6809 assembler serial port routines.
/trunk/trunk/software/serial.asm
0,0 → 1,322
; ============================================================================
; __
; \\__/ o\ (C) 2022 Robert Finch, Waterloo
; \ __ / All rights reserved.
; \/_// robfinch<remove>@opencores.org
; ||
;
;
; Serial port routines for a WDC6551 compatible circuit.
;
; This source file is free software: you can redistribute it and/or modify
; it under the terms of the GNU Lesser General Public License as published
; by the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; This source file is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
; ============================================================================
;
;------------------------------------------------------------------------------
; Initialize serial port.
;
; Clear buffer indexes. Two bytes are used for the buffer index even though
; only a single byte is needed. This is for convenience in calculating the
; number of characters in the buffer, done later. The upper byte remains at
; zero.
; The port is initialized for 9600 baud, 1 stop bit and 8 bits data sent.
; The internal baud rate generator is used.
;
; Parameters:
; none
; Modifies:
; d
; Returns:
; none
;------------------------------------------------------------------------------
 
InitSerial:
SerialInit:
clra
clrb
std SerHeadRcv-1
std SerTailRcv-1
std SerHeadXmit-1
std SerTailXmit-1
clr SerRcvXon
clr SerRcvXoff
ldb #$09 ; dtr,rts active, rxint enabled, no parity
stb ACIA+ACIA_CMD
ldb #$1E ; baud 9600, 1 stop bit, 8 bit, internal baud gen
stb ACIA+ACIA_CTRL
ldb #$0A6 ; diable fifos, reset fifos
stb ACIA+ACIA_CTRL2
rts
 
;------------------------------------------------------------------------------
; SerialGetChar
;
; Check the serial port buffer to see if there's a char available. If there's
; a char available then return it. If the buffer is almost empty then send an
; XON.
;
; Stack Space:
; 2 words
; Parameters:
; none
; Modifies:
; none
; Returns:
; d = character or -1
;------------------------------------------------------------------------------
 
SerialGetChar:
pshs x
sei ; disable interrupts
bsr SerialRcvCount ; check number of chars in receive buffer
cmpb #8 ; less than 8?
bhi sgc2
ldb SerRcvXon ; skip sending XON if already sent
bne sgc2 ; XON already sent?
ldb #XON ; if <8 send an XON
clr SerRcvXoff ; clear XOFF status
stb SerRcvXon ; flag so we don't send it multiple times
stb ACIA+ACIA_TX
sgc2:
ldb SerHeadRcv ; check if anything is in buffer
cmpb SerTailRcv
beq sgcNoChars ; no?
ldx #SerRcvBuf
abx
clra
ldb ,x ; get byte from buffer
inc SerHeadRcv ; 4k wrap around
bra sgcXit
sgcNoChars:
ldd #-1
sgcXit:
cli
puls x,pc
 
;------------------------------------------------------------------------------
; SerialPeekChar
;
; Check the serial port buffer to see if there's a char available. If there's
; a char available then return it. But don't update the buffer indexes. No need
; to send an XON here.
;
; Stack Space:
; 0 words
; Parameters:
; none
; Modifies:
; none
; Returns:
; d = character or -1
;------------------------------------------------------------------------------
 
SerialPeekChar:
pshs x
sei
ldb SerHeadRcv ; check if anything is in buffer
cmpb SerTailRcv
beq spcNoChars ; no?
ldx #SerRcvBuf
abx
clra
ldb ,x ; get byte from buffer
bra spcXit
spcNoChars:
ldd #-1
spcXit:
cli
puls x,pc
 
;------------------------------------------------------------------------------
; SerialPeekChar
; Get a character directly from the I/O port. This bypasses the input
; buffer.
;
; Stack Space:
; 0 words
; Parameters:
; none
; Modifies:
; d
; Returns:
; d = character or -1
;------------------------------------------------------------------------------
 
SerialPeekCharDirect:
; Disallow interrupts between status read and rx read.
sei
ldb ACIA+ACIA_STAT
bitb #8 ; look for Rx not empty
beq spcd0001
clra
ldb ACIA+ACIA_RX
cli
rts
spcd0001:
ldd #-1
cli
rts
 
;------------------------------------------------------------------------------
; SerialPutChar
; Put a character to the serial transmitter. This routine blocks until the
; transmitter is empty.
;
; Stack Space
; 0 words
; Parameters:
; b = character to put
; Modifies:
; none
;------------------------------------------------------------------------------
 
SerialPutChar:
pshs a
spc0001:
cli ; provide a window for an interrupt to occur
sei
; Between the status read and the transmit do not allow an
; intervening interrupt.
lda ACIA+ACIA_STAT ; wait until the uart indicates tx empty
bita #16 ; bit #4 of the status reg
beq spc0001 ; branch if transmitter is not empty
stb ACIA+ACIA_TX ; send the byte
cli
puls a
rts
 
;------------------------------------------------------------------------------
; Calculate number of character in input buffer
;
; Returns:
; d = number of bytes in buffer.
;------------------------------------------------------------------------------
 
SerialRcvCount:
clra
ldb SerTailRcv
subb SerHeadRcv
bge srcXit
ldd #$1000
subd SerHeadRcv
addd SerTailRcv
srcXit:
rts
 
;------------------------------------------------------------------------------
; Serial IRQ routine
;
; Keeps looping as long as it finds characters in the ACIA recieve buffer/fifo.
; Received characters are buffered. If the buffer becomes full, new characters
; will be lost.
;
; Parameters:
; none
; Modifies:
; d,x
; Returns:
; none
;------------------------------------------------------------------------------
 
SerialIRQ:
sirqNxtByte:
ldb ACIA+ACIA_STAT ; check the status
bitb #$08 ; bit 3 = rx full
beq notRxInt
ldb ACIA+ACIA_RX ; get data from Rx buffer to clear interrupt
cmpb #CTRLT ; detect special keystroke
bne sirq0001
; bsr DumpTraceQueue
sirq0001:
lda SerTailRcv ; check if recieve buffer full
inca
cmpa SerHeadRcv
beq sirqRxFull
sta SerTailRcv ; update tail pointer
deca ; backup
exg a,b
ldx #SerRcvBuf ; x = buffer address
abx
sta ,x ; store recieved byte in buffer
tst SerRcvXoff ; check if xoff already sent
bne sirqNxtByte
bsr SerialRcvCount ; if more than 4080 chars in buffer
cmpb #4080
blo sirqNxtByte
ldb #XOFF ; send an XOFF
clr SerRcvXon ; clear XON status
stb SerRcvXoff ; set XOFF status
stb ACIA+ACIA_TX
bra sirqNxtByte ; check the status for another byte
sirqRxFull:
notRxInt:
rts
 
nmeSerial:
fcb "Serial",0
 
;------------------------------------------------------------------------------
; Put a string to the serial port.
;
; Parameters:
; d = pointer to string
; Modifies:
; none
; Returns:
; none
;------------------------------------------------------------------------------
 
SerialPutString:
pshs d,x
tfr d,x
sps2:
ldb ,x
beq spsXit
inx
bsr SerialPutChar
bra sps2
spsXit:
puls d,x,pc
 
;------------------------------------------------------------------------------
; A little routine to test serial output.
;
; Parameters:
; none
; Modifies:
; none
; Returns:
; none
;------------------------------------------------------------------------------
 
SerialOutputTest:
pshs d
ldd #msgSerialTest
lbsr DisplayString
bsr SerialInit
sotst1:
ldb #XON
bsr SerialPutChar
bsr SerialPutChar
bsr SerialPutChar
ldd #msgSerialTest
bsr SerialPutString
lbsr INCH
cmpb #CTRLC
bne sotst1
puls d,pc
 
msgSerialTest:
fcb "Serial port test",CR,LF,0
 

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