OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block/trunk/hdl/iseProject
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/isim.log
17,3 → 17,4
In process testUart_control.vhd:stim_proc
INFO: Simulator is stopped.
# exit 0
/serial_receiver.vhd
87,7 → 87,7
end process;
-- Process to handle the serial receive
process (current_s)
process (current_s, serial_in)
variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0);
begin
case current_s is
/testUart_control.vhd
15,20 → 15,21
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_control
Port ( rst : in STD_LOGIC; -- Global reset
clk : in STD_LOGIC; -- Global clock
WE : in STD_LOGIC; -- Write enable
reg_addr : in STD_LOGIC_VECTOR (1 downto 0); -- Register address
Port ( rst : in std_logic; -- Global reset
clk : in std_logic; -- Global clock
WE : in std_logic; -- Write enable
reg_addr : in std_logic_vector (1 downto 0); -- Register address
start : in std_logic; -- Start (Strobe)
done : out std_logic; -- Done (ACK)
DAT_I : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
DAT_O : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
baud_wait : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
tx_data_sent : in STD_LOGIC; -- Signal comming from serial_transmitter
tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
tx_start : out std_logic; -- Signal to start sending serial data...
rst_comm_blocks : out std_logic; -- Reset Communication blocks
rx_data_ready : in STD_LOGIC); -- Signal comming from serial_receiver
rx_data_ready : in std_logic);
END COMPONENT;
 
45,6 → 46,7
 
--Outputs
signal done : std_logic;
signal tx_start : std_logic;
signal rst_comm_blocks : std_logic;
signal DAT_O : std_logic_vector((nBitsLarge-1) downto 0);
signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
70,6 → 72,7
data_byte_rx => data_byte_rx,
tx_data_sent => tx_data_sent,
rst_comm_blocks => rst_comm_blocks,
tx_start => tx_start,
rx_data_ready => rx_data_ready
);
 
119,7 → 122,7
WE <= '1';
start <= '1';
DAT_I <= x"00000055";
wait for clk_period*10;
wait for clk_period*10; -- No point to use wait until because we're not connected to the comm block yet
 
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
/uart_control.vhd
18,6 → 18,7
data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
tx_start : out std_logic; -- Signal to start sending serial data...
rst_comm_blocks : out std_logic; -- Reset Communication blocks
rx_data_ready : in std_logic); -- Signal comming from serial_receiver
end uart_control;
119,7 → 120,8
div_result_baud_wait := (others => '0');
done <= '0';
sigDivRst <= '1';
rst_comm_blocks <= '1';
rst_comm_blocks <= '1';
tx_start <= '0';
elsif rising_edge(clk) then
case controlStates is
when idle =>
179,6 → 181,7
-- Control the serial_receiver or serial_transmitter block
when rx_tx_state =>
rst_comm_blocks <= '0';
tx_start <= '0';
controlStates <= rx_tx_state;
if (WE = '1') and (start = '1') then
if reg_addr = "10" then
197,6 → 200,7
-- Send data and wait to transmit
when tx_state_wait =>
tx_start <= '1';
data_byte_tx <= byte_to_transmitt;
if tx_data_sent = '0' then
controlStates <= tx_state_wait;
/iseProject.gise
98,6 → 98,18
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_control_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_wishbone_slave.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_wishbone_slave.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_wishbone_slave.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_wishbone_slave.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_wishbone_slave.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_wishbone_slave.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_wishbone_slave.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_wishbone_slave_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
108,9 → 120,13
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335800030" xil_pn:in_ck="-4722702178573701357" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335800030">
<transform xil_pn:end_ts="1335802560" xil_pn:in_ck="7038098250406169239" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335802560">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
124,6 → 140,7
<outfile xil_pn:name="testUart_control.vhd"/>
<outfile xil_pn:name="uart_communication_blocks.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1335798073" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8606825911088484082" xil_pn:start_ts="1335798073">
<status xil_pn:value="SuccessfullyRun"/>
133,13 → 150,18
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335787909" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="3805806310047624647" xil_pn:start_ts="1335787909">
<transform xil_pn:end_ts="1335802528" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335802528">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335800030" xil_pn:in_ck="-4722702178573701357" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335800030">
<transform xil_pn:end_ts="1335802560" xil_pn:in_ck="7038098250406169239" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335802560">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
153,11 → 175,15
<outfile xil_pn:name="testUart_control.vhd"/>
<outfile xil_pn:name="uart_communication_blocks.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1335800032" xil_pn:in_ck="-4722702178573701357" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-5081072825835922682" xil_pn:start_ts="1335800030">
<transform xil_pn:end_ts="1335802561" xil_pn:in_ck="7038098250406169239" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-5081072825835922682" xil_pn:start_ts="1335802560">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
166,56 → 192,62
<outfile xil_pn:name="testUart_control_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335800032" xil_pn:in_ck="4271185753694017635" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7937214117275137446" xil_pn:start_ts="1335800032">
<transform xil_pn:end_ts="1335802562" xil_pn:in_ck="4271185753694017635" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7937214117275137446" xil_pn:start_ts="1335802561">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testUart_control_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1334961610" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1334961610">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796982" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-35064074774108767" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1008586360203480345" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796982" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3805806310047624647" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796982" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796982" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1079965127516565983" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7853110446436427671" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796982" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796982" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8612320488941914449" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802690" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2852686481009242409" xil_pn:start_ts="1335802690">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335796992" xil_pn:in_ck="-6248044245201781046" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-2148701269487986748" xil_pn:start_ts="1335796982">
<transform xil_pn:end_ts="1335802840" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8823216100926192740" xil_pn:start_ts="1335802829">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="uart_control.lso"/>
<outfile xil_pn:name="uart_control.ngc"/>
<outfile xil_pn:name="baud_generator.ngr"/>
<outfile xil_pn:name="serial_receiver.ngr"/>
<outfile xil_pn:name="serial_transmitter.ngr"/>
<outfile xil_pn:name="uart_communication_blocks.ngr"/>
<outfile xil_pn:name="uart_control.ngr"/>
<outfile xil_pn:name="uart_control.prj"/>
<outfile xil_pn:name="uart_control.stx"/>
<outfile xil_pn:name="uart_control.syr"/>
<outfile xil_pn:name="uart_control.xst"/>
<outfile xil_pn:name="uart_control_xst.xrpt"/>
<outfile xil_pn:name="uart_wishbone_slave.lso"/>
<outfile xil_pn:name="uart_wishbone_slave.ngc"/>
<outfile xil_pn:name="uart_wishbone_slave.ngr"/>
<outfile xil_pn:name="uart_wishbone_slave.prj"/>
<outfile xil_pn:name="uart_wishbone_slave.stx"/>
<outfile xil_pn:name="uart_wishbone_slave.syr"/>
<outfile xil_pn:name="uart_wishbone_slave.xst"/>
<outfile xil_pn:name="uart_wishbone_slave_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
/divisor.vhd
22,7 → 22,7
begin
-- Division algorithm Q=N/D
process (rst, clk)
process (rst, clk, numerator, divident)
variable Q : unsigned(quotient'length-1 downto 0);
variable R : unsigned(reminder'length-1 downto 0);
variable D : unsigned(reminder'length-1 downto 0);
/fuse.log
10,7 → 10,7
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36628 KB
Fuse CPU Usage: 1070 ms
Fuse CPU Usage: 1090 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
20,9 → 20,8
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling architecture behavior of entity testuart_control
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 10 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe
Fuse Memory Usage: 85688 KB
Fuse CPU Usage: 1160 ms
Fuse CPU Usage: 1180 ms
GCC CPU Usage: 400 ms
/uart_wishbone_slave.vhd
0,0 → 1,95
--! Top wishbone slave for the uart
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity uart_wishbone_slave is
Port ( RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0);
DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0);
DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0);
WE_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC;
serial_in : in std_logic;
serial_out : out std_logic
);
end uart_wishbone_slave;
 
architecture Behavioral of uart_wishbone_slave is
component uart_control is
Port ( rst : in std_logic; -- Global reset
clk : in std_logic; -- Global clock
WE : in std_logic; -- Write enable
reg_addr : in std_logic_vector (1 downto 0); -- Register address
start : in std_logic; -- Start (Strobe)
done : out std_logic; -- Done (ACK)
DAT_I : in std_logic_vector ((nBitsLarge-1) downto 0); -- Data Input (Wishbone)
DAT_O : out std_logic_vector ((nBitsLarge-1) downto 0); -- Data output (Wishbone)
baud_wait : out std_logic_vector ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency
data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter
data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver
tx_data_sent : in std_logic; -- Signal comming from serial_transmitter
tx_start : out std_logic; -- Signal to start sending serial data...
rst_comm_blocks : out std_logic; -- Reset Communication blocks
rx_data_ready : in std_logic);
end component;
 
component uart_communication_blocks is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent_tx : out STD_LOGIC;
data_received_rx : out STD_LOGIC;
serial_out : out std_logic;
serial_in : in std_logic;
start_tx : in STD_LOGIC);
end component;
signal baud_wait : std_logic_vector((nBitsLarge-1) downto 0);
signal tx_data_sent : std_logic;
signal tx_start : std_logic;
signal rst_comm_blocks : std_logic;
signal rx_data_ready : std_logic;
signal data_byte_tx : std_logic_vector(7 downto 0);
signal data_byte_rx : std_logic_vector(7 downto 0);
begin
-- Instantiate uart_control
uUartControl : uart_control port map (
rst => RST_I,
clk => CLK_I,
WE => WE_I,
reg_addr => ADR_I0,
start => STB_I,
done => ACK_O,
DAT_I => DAT_I0,
DAT_O => DAT_O0,
baud_wait => baud_wait,
data_byte_tx => data_byte_tx,
data_byte_rx => data_byte_rx,
tx_data_sent => tx_data_sent,
rst_comm_blocks => rst_comm_blocks,
tx_start => tx_start,
rx_data_ready => rx_data_ready
);
-- Instantiate uart_communication_blocks
uUartCommunicationBlocks : uart_communication_blocks port map (
rst => rst_comm_blocks,
clk => CLK_I,
cycle_wait_baud => baud_wait,
byte_tx => data_byte_tx,
byte_rx => data_byte_rx,
data_sent_tx => tx_data_sent,
data_received_rx => rx_data_ready,
serial_out => serial_out,
serial_in => serial_in,
start_tx => tx_start
);
 
end Behavioral;
 
/webtalk_pn.xml
3,7 → 3,7
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Mon Apr 30 16:43:02 2012">
<application name="pn" timeStamp="Mon Apr 30 18:20:29 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
19,7 → 19,7
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/uart_control" type="process"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_control" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
29,7 → 29,7
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.uart_control" type="process"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_control" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/>
41,7 → 41,7
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="12" type="source"/>
<property name="FILE_VHDL" value="14" type="source"/>
</section>
</application>
</document>
/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd&quot; into library work</arg>
</msg>
 
</messages>
/_xmsgs/xst.xmsgs
5,117 → 5,322
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="819" delta="new" >&quot;<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd</arg>&quot; line <arg fmt="%d" index="2">25</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;divident&gt;, &lt;numerator&gt;</arg>
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">D</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">D</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">N</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">N</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">cycle_wait_oversample</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">sigDivReminder</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">half_cycle</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">half_cycle0</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">byteReceived&lt;7&gt;</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">96</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="646" delta="old" >Signal &lt;<arg fmt="%s" index="1">sigDivReminder</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">30</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">29</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">30</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="new" >Node &lt;<arg fmt="%s" index="1">uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_control</arg>&gt;.
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;cycle_wait_oversample_8&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;cycle_wait_oversample_5&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;cycle_wait_oversample_24&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_28</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;cycle_wait_oversample_29&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;cycle_wait_oversample_0&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;cycle_wait_oversample_14&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;cycle_wait_oversample_19&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;cycle_wait_oversample_9&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;cycle_wait_oversample_6&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;cycle_wait_oversample_25&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_2&gt; &lt;cycle_wait_oversample_1&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;cycle_wait_oversample_15&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;cycle_wait_oversample_20&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;cycle_wait_oversample_10&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;cycle_wait_oversample_7&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;cycle_wait_oversample_26&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;cycle_wait_oversample_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;cycle_wait_oversample_16&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;cycle_wait_oversample_21&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;cycle_wait_oversample_11&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;cycle_wait_oversample_27&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;cycle_wait_oversample_3&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;cycle_wait_oversample_17&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;cycle_wait_oversample_22&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;cycle_wait_oversample_12&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;cycle_wait_oversample_4&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;cycle_wait_oversample_23&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;cycle_wait_oversample_28&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;cycle_wait_oversample_13&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;cycle_wait_oversample_18&gt; </arg>
</msg>
 
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">serial_receiver</arg>: <arg fmt="%d" index="2">7</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/R_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_0</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_1</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_2</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_3</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_4</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_5</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_6</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_7</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_8</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_9</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_10</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_11</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_12</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_13</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_14</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_15</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_16</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_17</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_18</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_19</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_20</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_21</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_22</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_23</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_24</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_25</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_26</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_27</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_28</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_29</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_30</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="warning" file="Xst" num="2677" delta="old" >Node &lt;<arg fmt="%s" index="1">uUartControl/uDiv/reminder_31</arg>&gt; of sequential type is unconnected in block &lt;<arg fmt="%s" index="2">uart_wishbone_slave</arg>&gt;.
</msg>
 
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
</messages>
 
/baud_generator.vhd
20,7 → 20,7
signal genTick : std_logic;
signal genTickOverSample : std_logic;
begin
process (rst, clk)
process (rst, clk, cycle_wait)
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
begin
48,7 → 48,7
baud_oversample <= genTickOverSample;
-- Process to generate the overclocked (8x) sample
process (rst, clk)
process (rst, clk, cycle_wait)
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
/iseProject.xise
17,7 → 17,7
<files>
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
31,7 → 31,7
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
41,7 → 41,7
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
51,7 → 51,7
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
61,7 → 61,7
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
71,7 → 71,7
</file>
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
79,6 → 79,10
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
</files>
 
<properties>
184,9 → 188,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_control|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_control.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_control" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_wishbone_slave|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_wishbone_slave.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
244,7 → 248,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
256,10 → 260,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_control_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_control_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_control_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_control_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_wishbone_slave_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_wishbone_slave_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_wishbone_slave_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_wishbone_slave_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
279,7 → 283,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_control" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
/xst/work/hdpdeps.ref
1,56 → 1,64
V3 29
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/04/30.15:47:40 O.87xd
EN work/baud_generator 1335796914 \
V3 34
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/04/30.18:19:47 O.87xd
EN work/baud_generator 1335802835 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335796987
AR work/baud_generator/Behavioral 1335796915 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335802834
AR work/baud_generator/Behavioral 1335802836 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
EN work/baud_generator 1335796914
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/04/30.07:41:35 O.87xd
EN work/divisor 1335796988 \
EN work/baud_generator 1335802835
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/04/30.18:18:59 O.87xd
EN work/divisor 1335802841 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1335796987
AR work/divisor/Behavioral 1335796989 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335796988
PB work/pkgDefinitions 1335802834
AR work/divisor/Behavioral 1335802842 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335802841
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/30.08:38:25 O.87xd
PH work/pkgDefinitions 1335796986 \
PH work/pkgDefinitions 1335802833 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335796987 \
PB work/pkgDefinitions 1335802834 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PH work/pkgDefinitions 1335796986
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/30.15:53:30 O.87xd
EN work/serial_receiver 1335796918 \
PH work/pkgDefinitions 1335802833
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/30.18:20:26 O.87xd
EN work/serial_receiver 1335802839 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335796987
AR work/serial_receiver/Behavioral 1335796919 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335802834
AR work/serial_receiver/Behavioral 1335802840 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \
EN work/serial_receiver 1335796918
EN work/serial_receiver 1335802839
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd
EN work/serial_transmitter 1335796916 \
EN work/serial_transmitter 1335802837 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335796987
AR work/serial_transmitter/Behavioral 1335796917 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335802834
AR work/serial_transmitter/Behavioral 1335802838 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335796916
EN work/serial_transmitter 1335802837
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd
EN work/uart_communication_blocks 1335796920 \
EN work/uart_communication_blocks 1335802845 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335796987
AR work/uart_communication_blocks/Behavioral 1335796921 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335802834
AR work/uart_communication_blocks/Behavioral 1335802846 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \
EN work/uart_communication_blocks 1335796920 CP baud_generator \
EN work/uart_communication_blocks 1335802845 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/04/30.10:14:50 O.87xd
EN work/uart_control 1335796990 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/04/30.18:12:57 O.87xd
EN work/uart_control 1335802843 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335796987
AR work/uart_control/Behavioral 1335796991 \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335802834
AR work/uart_control/Behavioral 1335802844 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \
EN work/uart_control 1335796990 CP divisor
EN work/uart_control 1335802843 CP divisor
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd
EN work/uart_wishbone_slave 1335802847 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335802834
AR work/uart_wishbone_slave/Behavioral 1335802848 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \
EN work/uart_wishbone_slave 1335802847 CP uart_control \
CP uart_communication_blocks
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
/xst/work/hdllib.ref
1,14 → 1,16
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335796990
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335796917
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335796915
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335796918
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335796988
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335796989
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335796916
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335796921
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335796919
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335796920
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335796987
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335796991
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335796914
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335796986
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335802843
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335802838
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335802847
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335802836
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335802839
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335802841
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335802842
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335802837
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335802846
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335802848
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335802840
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335802845
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335802834
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335802844
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335802835
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335802833
/xst/work/sub00/vhpl04.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/xst/work/sub00/vhpl05.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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