URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
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/uart_block/trunk/hdl/iseProject
- from Rev 18 to Rev 19
- ↔ Reverse comparison
Rev 18 → Rev 19
/isim.log
1,132 → 1,363
ISim log file |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 30 |
# run all |
Stopped at time : 24706500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
Stopped at time : 25249500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
Stopped at time : 25792500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
Stopped at time : 1821 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 46 |
# run all |
Stopped at time : 8765 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 87 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 870 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 9627710 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" Line 60 |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 87690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 125 |
# run all |
Stopped at time : 96330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 91 |
# run all |
Stopped at time : 105010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 96 |
# run all |
Stopped at time : 113690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 101 |
# run all |
Stopped at time : 122370 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 106 |
# run all |
Stopped at time : 131050 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 111 |
# run all |
Stopped at time : 139730 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 116 |
# run all |
Stopped at time : 148410 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 121 |
# run all |
Stopped at time : 157090 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 126 |
# run all |
Stopped at time : 165770 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 132 |
# run all |
Stopped at time : 9633330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 71 |
# exit 0 |
ISim log file |
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 174470 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 220 |
# run all |
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183170 ns : File "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 151 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
# show driver /testuart_wishbone_slave/dat_o0 |
Driver for /testuart_wishbone_slave/dat_o0[0] |
'1' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[10] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[11] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[12] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[13] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[14] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[15] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[16] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[17] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[18] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[19] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[1] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[20] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[21] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[22] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[23] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[24] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[25] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[26] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[27] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[28] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[29] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[2] |
'1' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[30] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[31] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[3] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[4] |
'1' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[5] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[6] |
'1' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[7] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[8] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
Driver for /testuart_wishbone_slave/dat_o0[9] |
'0' : /testuart_wishbone_slave/uut/uUartControl/:64 |
in File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 64 |
|
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
# run all |
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
# run all |
Stopped at time : 183150 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 183130 ns : File "E:/uart_block/hdl/iseProject/uart_control.vhd" Line 81 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 26193350 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 36542110 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 39 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 23647410 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 82 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 16400510 ns : File "E:/uart_block/hdl/iseProject/baud_generator.vhd" Line 89 |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
/fuseRelaunch.cmd
1,132 → 1,363
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
/uart_control.vhd
26,7 → 26,7
architecture Behavioral of uart_control is |
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0); |
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0); |
signal byte_to_receive : std_logic_vector((nBits-1) downto 0); |
--signal byte_to_receive : std_logic_vector((nBits-1) downto 0); |
signal byte_to_transmitt : std_logic_vector((nBits-1) downto 0); |
signal controlStates : uartControl; |
|
61,9 → 61,11
); |
|
-- Process that read uart control registers |
process (rst, clk, reg_addr,WE) |
process (rst, reg_addr, WE, start, byte_to_transmitt, data_byte_rx, rx_data_ready, config_clk, config_baud) |
begin |
if rising_edge(clk) then |
if rst = '1' then |
DAT_O <= (others => 'Z'); |
else |
if (WE = '0') and (start = '1') then |
case reg_addr is |
when "00" => |
74,13 → 76,20
-- Byte that will be transmitted |
DAT_O <= "000000000000000000000000" & byte_to_transmitt; |
when "11" => |
-- Byte that will be received |
DAT_O <= "000000000000000000000000" & byte_to_receive; |
-- Byte that will be received |
if rx_data_ready = '1' then |
DAT_O <= "000000000000000000000000" & data_byte_rx; |
--DAT_O <= "000000000000000000000000" & byte_to_receive; |
else |
DAT_O <= (others => 'Z'); |
end if; |
when others => |
null; |
end case; |
end if; |
end if; |
DAT_O <= (others => 'Z'); |
end case; |
else |
DAT_O <= (others => 'Z'); |
end if; |
end if; |
end process; |
|
-- Process that populate the uart control registers |
108,7 → 117,7
end process; |
|
-- Process to handle the next state logic |
process (rst, clk, reg_addr, WE) |
process (rst, clk, reg_addr, WE, start) |
variable baud_configured : std_logic; |
variable clk_configured : std_logic; |
variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0); |
122,6 → 131,7
sigDivRst <= '1'; |
rst_comm_blocks <= '1'; |
tx_start <= '0'; |
--byte_to_receive <= (others => 'Z'); |
elsif rising_edge(clk) then |
case controlStates is |
when idle => |
192,8 → 202,7
|
if (WE = '0') and (start = '1') then |
if reg_addr = "11" then |
controlStates <= rx_state_wait; |
done <= '0'; |
controlStates <= rx_state_wait; |
end if; |
end if; |
|
211,13 → 220,18
|
-- Receive data and wait to receive |
when rx_state_wait => |
if rx_data_ready = '1' then |
byte_to_receive <= data_byte_rx; |
done <= '1'; |
controlStates <= rx_tx_state; |
if rx_data_ready = '1' then |
-- Put an ack on the next cycle |
controlStates <= rx_state_ack; |
else |
controlStates <= rx_state_wait; |
end if; |
controlStates <= rx_state_wait; |
done <= '0'; |
end if; |
|
-- Ack that we got a value |
when rx_state_ack => |
done <= '1'; |
controlStates <= rx_tx_state; |
end case; |
end if; |
end process; |
/pkgDefinitions.vhd
26,7 → 26,7
type rxFilterStates is (s0, s1, s2, s3); |
|
type uartControl is (idle, config_state_clk, config_state_baud, start_division, wait_division, config_state_baud_generator, |
rx_tx_state, tx_state_wait, rx_state_wait); |
rx_tx_state, tx_state_wait, rx_state_wait, rx_state_ack); |
|
end pkgDefinitions; |
|
/iseProject.gise
81,6 → 81,7
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_communication_block_isim_beh.wdb"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_wishbone_slave_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/> |
131,9 → 132,13
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335879371" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335879371"> |
<transform xil_pn:end_ts="1335908295" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335908295"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
<outfile xil_pn:name="divisor.vhd"/> |
<outfile xil_pn:name="pkgDefinitions.vhd"/> |
150,11 → 155,11
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335878937" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335878937"> |
<transform xil_pn:end_ts="1335899449" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335899449"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335878937" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335878937"> |
<transform xil_pn:end_ts="1335899449" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335899449"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
161,10 → 166,16
<transform xil_pn:end_ts="1335876275" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335876275"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForProperties"/> |
</transform> |
<transform xil_pn:end_ts="1335879371" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335879371"> |
<transform xil_pn:end_ts="1335908295" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335908295"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
<outfile xil_pn:name="divisor.vhd"/> |
<outfile xil_pn:name="pkgDefinitions.vhd"/> |
181,10 → 192,13
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335879373" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335879371"> |
<transform xil_pn:end_ts="1335908298" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335908295"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
193,60 → 207,58
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1335879373" xil_pn:in_ck="-5691276081812346650" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335879373"> |
<transform xil_pn:end_ts="1335908312" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335908312"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1335863867" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335863867"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1008586360203480345" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-35064074774108767" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3805806310047624647" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7853110446436427671" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1079965127516565983" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2852686481009242409" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909764" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8612320488941914449" xil_pn:start_ts="1335909764"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335875605" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8823216100926192740" xil_pn:start_ts="1335875592"> |
<transform xil_pn:end_ts="1335909825" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-2148701269487986748" xil_pn:start_ts="1335909819"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="baud_generator.ngr"/> |
<outfile xil_pn:name="divisor.ngr"/> |
<outfile xil_pn:name="serial_receiver.ngr"/> |
<outfile xil_pn:name="serial_transmitter.ngr"/> |
<outfile xil_pn:name="uart_communication_blocks.ngr"/> |
<outfile xil_pn:name="uart_control.lso"/> |
<outfile xil_pn:name="uart_control.ngc"/> |
<outfile xil_pn:name="uart_control.ngr"/> |
<outfile xil_pn:name="uart_wishbone_slave.lso"/> |
<outfile xil_pn:name="uart_wishbone_slave.ngc"/> |
<outfile xil_pn:name="uart_wishbone_slave.ngr"/> |
<outfile xil_pn:name="uart_wishbone_slave.prj"/> |
<outfile xil_pn:name="uart_wishbone_slave.stx"/> |
<outfile xil_pn:name="uart_wishbone_slave.syr"/> |
<outfile xil_pn:name="uart_wishbone_slave.xst"/> |
<outfile xil_pn:name="uart_wishbone_slave_xst.xrpt"/> |
<outfile xil_pn:name="uart_control.prj"/> |
<outfile xil_pn:name="uart_control.stx"/> |
<outfile xil_pn:name="uart_control.syr"/> |
<outfile xil_pn:name="uart_control.xst"/> |
<outfile xil_pn:name="uart_control_vhdl.prj"/> |
<outfile xil_pn:name="uart_control_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
/fuse.log
1,40 → 1,36
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -relaunch -intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
Determining compilation order of HDL files |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work |
WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 37476 KB |
Fuse CPU Usage: 1110 ms |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package std_logic_unsigned |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity divisor [divisor_default] |
Compiling architecture behavioral of entity uart_control [uart_control_default] |
Compiling package numeric_std |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default] |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default] |
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...] |
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Time Resolution for simulation is 1ps. |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 21 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 89256 KB |
Fuse CPU Usage: 1270 ms |
GCC CPU Usage: 150 ms |
Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
ISim O.87xd (signature 0xc3576ebc) |
Number of CPUs detected in this system: 8 |
Turning on mult-threading, number of parallel sub-compilation jobs: 16 |
Determining compilation order of HDL files |
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work |
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression |
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package std_logic_unsigned |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity divisor [divisor_default] |
Compiling architecture behavioral of entity uart_control [uart_control_default] |
Compiling package numeric_std |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default] |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default] |
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...] |
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Time Resolution for simulation is 1ps. |
Compiled 21 VHDL Units |
Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 37732 KB |
Fuse CPU Usage: 405 ms |
/testUart_wishbone_slave.vhd
77,7 → 77,8
stim_proc: process |
begin |
-- Reset the slave |
RST_I <= '1'; |
RST_I <= '1'; |
serial_in <= '1'; |
wait for CLK_I_period; |
RST_I <= '0'; |
wait for CLK_I_period; |
113,12 → 114,13
WE_I <= '0'; |
STB_I <= '0'; |
ADR_I0 <= (others => 'U'); |
wait for CLK_I_period; |
wait for CLK_I_period*500; |
|
-- Ask to send some data...(0xC4) |
-- Receive data |
ADR_I0 <= "11"; |
WE_I <= '1'; |
STB_I <= '1'; |
WE_I <= '0'; |
STB_I <= '1'; |
wait for CLK_I_period*100; -- Error !!!!! (Should not need this!!) |
|
-- Receive data... |
-- Receive 0x55 value (01010101) |
143,13 → 145,10
wait for 8.68 us; |
|
-- Stop bit here |
serial_in <= '1'; |
wait for CLK_I_period*20; |
serial_in <= '1'; |
|
wait until ACK_O = '1'; |
WE_I <= '0'; |
STB_I <= '0'; |
wait for CLK_I_period; |
wait until ACK_O = '1'; |
wait for CLK_I_period*100; |
|
-- Stop Simulation |
assert false report "NONE. End of simulation." severity failure; |
/webtalk_pn.xml
1,47 → 1,46
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Tue May 1 14:33:13 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="0" type="project"/> |
<property name="ProjectFile" value="/home/laraujo/work/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
<section name="Project Statistics" visible="true"> |
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> |
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/> |
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
<property name="PROP_FitterReportFormat" value="HTML" type="process"/> |
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testSerial_receiver" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
<property name="PROP_UseSmartGuide" value="false" type="design"/> |
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testSerial_receiver" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/> |
<property name="PROP_DevFamily" value="Spartan3E" type="design"/> |
<property name="PROP_DevDevice" value="xc3s500e" type="design"/> |
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> |
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 us" type="process"/> |
<property name="PROP_DevPackage" value="fg320" type="design"/> |
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_VHDL" value="14" type="source"/> |
</section> |
</application> |
</document> |
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Wed May 02 00:03:39 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="0" type="project"/> |
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
<section name="Project Statistics" visible="true"> |
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> |
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/> |
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
<property name="PROP_FitterReportFormat" value="HTML" type="process"/> |
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
<property name="PROP_UseSmartGuide" value="false" type="design"/> |
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_DevFamily" value="Spartan3E" type="design"/> |
<property name="PROP_DevDevice" value="xc3s500e" type="design"/> |
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> |
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/> |
<property name="PROP_DevPackage" value="fg320" type="design"/> |
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_VHDL" value="15" type="source"/> |
</section> |
</application> |
</document> |
/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/_xmsgs/xst.xmsgs
1,321 → 1,116
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">53</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">53</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
<msg type="info" file="Xst" num="1561" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">83</arg>: Mux is complete : default of case is discarded |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">uart_control</arg>: <arg fmt="%d" index="2">8</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uBaudGen</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>> in Unit <<arg fmt="%s" index="2">serial_receiver</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><data_ready> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. |
</msg> |
|
</messages> |
|
|
/fuse.xmsgs
1,12 → 1,12
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression |
</msg> |
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression |
</msg> |
|
</messages> |
|
|
/xilinxsim.ini
1,12 → 1,12
work=isim/work |
work=isim/work |
/isim.cmd
1,3 → 1,3
onerror {resume} |
wave add / |
run 1000 ms; |
onerror {resume} |
wave add / |
run 1000 ms; |
/iseProject.xise
17,7 → 17,7
<files> |
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
31,7 → 31,7
</file> |
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
41,7 → 41,7
</file> |
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
51,7 → 51,7
</file> |
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
61,7 → 61,7
</file> |
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
71,7 → 71,7
</file> |
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
81,7 → 81,7
</file> |
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
115,7 → 115,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
194,9 → 194,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_wishbone_slave|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_wishbone_slave.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_control|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_control.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave/uUartControl" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
254,7 → 254,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="uart_control" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
266,10 → 266,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_wishbone_slave_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="uart_wishbone_slave_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_wishbone_slave_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_wishbone_slave_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_control_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="uart_control_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_control_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_control_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
289,7 → 289,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_control" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
/xst/work/hdpdeps.ref
1,65 → 1,63
V3 34 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
EN work/baud_generator 1335875598 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \ |
PB work/pkgDefinitions 1335875597 |
AR work/baud_generator/Behavioral 1335875599 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
EN work/baud_generator 1335875598 |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
EN work/divisor 1335875604 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1335875597 |
AR work/divisor/Behavioral 1335875605 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335875604 |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.13:49:58 O.87xd |
PH work/pkgDefinitions 1335875596 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1335875597 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PH work/pkgDefinitions 1335875596 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
EN work/serial_receiver 1335875602 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/serial_receiver/Behavioral 1335875603 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
EN work/serial_receiver 1335875602 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
EN work/serial_transmitter 1335875600 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/serial_transmitter/Behavioral 1335875601 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1335875600 |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
EN work/uart_communication_blocks 1335875608 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/uart_communication_blocks/Behavioral 1335875609 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1335875608 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/01.14:32:36 O.87xd |
EN work/uart_control 1335875606 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/uart_control/Behavioral 1335875607 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1335875606 CP divisor |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
EN work/uart_wishbone_slave 1335875610 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/uart_wishbone_slave/Behavioral 1335875611 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1335875610 CP uart_control \ |
CP uart_communication_blocks |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
V3 36 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
EN work/baud_generator 1335875598 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \ |
PB work/pkgDefinitions 1335909821 |
AR work/baud_generator/Behavioral 1335875599 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
EN work/baud_generator 1335875598 |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.13:49:58 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
EN work/serial_receiver 1335875602 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335909821 |
AR work/serial_receiver/Behavioral 1335875603 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
EN work/serial_receiver 1335875602 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
EN work/serial_transmitter 1335875600 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335909821 |
AR work/serial_transmitter/Behavioral 1335875601 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1335875600 |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
EN work/uart_communication_blocks 1335875608 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335909821 |
AR work/uart_communication_blocks/Behavioral 1335875609 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1335875608 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/01.14:32:36 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
EN work/uart_wishbone_slave 1335875610 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335909821 |
AR work/uart_wishbone_slave/Behavioral 1335875611 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1335875610 CP uart_control \ |
CP uart_communication_blocks |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
EN work/divisor 1335909822 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1335909821 |
AR work/divisor/Behavioral 1335909823 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335909822 |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.23:44:07 O.87xd |
PH work/pkgDefinitions 1335909820 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1335909821 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1335909820 |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.00:03:37 O.87xd |
EN work/uart_control 1335909824 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335909821 |
AR work/uart_control/Behavioral 1335909825 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1335909824 \ |
CP divisor |
/xst/work/hdllib.ref
1,16 → 1,16
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335875606 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335875601 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335875610 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335875599 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335875602 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335875604 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335875605 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335875600 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335875609 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335875611 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335875603 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335875608 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335875597 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335875607 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335875598 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335875596 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335875609 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335909825 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335909821 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335875602 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335875611 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335875601 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335875608 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335909822 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335909823 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335875599 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335909824 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335875600 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335909820 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335875610 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335875598 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335875603 |
/xst/work/sub00/vhpl00.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/xst/work/sub00/vhpl01.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream