URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block/trunk/hdl/iseProject
- from Rev 27 to Rev 28
- ↔ Reverse comparison
Rev 27 → Rev 28
/iseProject.gise
312,7 → 312,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336085196" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336085185"> |
<transform xil_pn:end_ts="1336086318" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336086306"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
341,7 → 341,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336085201" xil_pn:in_ck="-1408796339596843907" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336085196"> |
<transform xil_pn:end_ts="1336086322" xil_pn:in_ck="-1408796339596843907" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336086318"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.bld"/> |
350,7 → 350,7
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336085204" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336085201"> |
<transform xil_pn:end_ts="1336086325" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336086322"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.pcf"/> |
363,7 → 363,7
<outfile xil_pn:name="INTERCON_P2P_usage.xml"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336085222" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336085204"> |
<transform xil_pn:end_ts="1336086342" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336086325"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
378,7 → 378,7
<outfile xil_pn:name="INTERCON_P2P_par.xrpt"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336085230" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336085222"> |
<transform xil_pn:end_ts="1336086350" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336086342"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.ut"/> |
398,7 → 398,7
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="InputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1336085222" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336085220"> |
<transform xil_pn:end_ts="1336086342" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336086340"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.twr"/> |
/SERIALMASTER.vhd
34,6 → 34,7
|
process (CLK_I) |
variable contWait : integer range 0 to 50000000; |
variable cycles2Wait : integer range 0 to 50000000; |
variable nextState: testMaster; |
begin |
if rising_edge(CLK_I) then |
41,7 → 42,8
masterSerialStates <= idle; |
nextState := idle; |
contWait := 0; |
byteIncome <= (others => '0'); |
cycles2Wait := 25000000; |
byteIncome <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'; |
else |
case masterSerialStates is |
when idle => |
81,8 → 83,8
DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@' |
if ACK_I = '1' then |
-- Byte received wait some cycles to continue |
masterSerialStates <= wait_cycles; |
byte_rec <= "00000100"; |
masterSerialStates <= wait_cycles; |
cycles2Wait := 7000000; |
end if; |
|
when receive_byte => |
95,12 → 97,12
masterSerialStates <= wait_cycles; |
byte_rec <= DAT_I(7 downto 0); |
byteIncome <= DAT_I(7 downto 0); |
--byte_rec <= "00001000"; |
cycles2Wait := 7000000; |
end if; |
|
when wait_cycles => |
-- wait some cycles (90) |
if contWait < 25000000 then |
if contWait < cycles2Wait then |
contWait := contWait + 1; |
STB_O <= '0'; |
else |
/webtalk_pn.xml
3,10 → 3,10
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Fri May 04 00:46:44 2012"> |
<application name="pn" timeStamp="Fri May 04 01:05:25 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="13" type="project"/> |
<property name="ProjectIteration" value="20" type="project"/> |
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
27,7 → 27,7
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWbtProjectIteration" value="13" type="process"/> |
<property name="PROP_intWbtProjectIteration" value="20" type="process"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> |
/_xmsgs/xst.xmsgs
14,6 → 14,9
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">95</arg>: Unconnected output port '<arg fmt="%s" index="3">data_Avaible</arg>' of component '<arg fmt="%s" index="4">uart_wishbone_slave</arg>'. |
</msg> |
|
<msg type="warning" file="Xst" num="1610" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/SERIALMASTER.vhd</arg>" line <arg fmt="%d" index="2">46</arg>: Width mismatch. <<arg fmt="%s" index="3">byteIncome</arg>> has a width of <arg fmt="%d" index="4">8</arg> bits but assigned expression is <arg fmt="%d" index="5">32</arg>-bit wide. |
</msg> |
|
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">62</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
|
356,7 → 359,7
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
386,7 → 389,7
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
497,9 → 500,30
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">nextState_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycles2Wait_0</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_2</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_3</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_4</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_23</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
/xst/work/hdpdeps.ref
9,73 → 9,73
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd |
EN work/baud_generator 1336085188 \ |
EN work/baud_generator 1336086310 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \ |
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \ |
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336085187 |
AR work/baud_generator/Behavioral 1336085189 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336085188 |
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336086309 |
AR work/baud_generator/Behavioral 1336086311 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336086310 |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
EN work/divisor 1336085194 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
EN work/divisor 1336086316 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1336085187 |
AR work/divisor/Behavioral 1336085195 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336085194 |
PB work/pkgDefinitions 1336086309 |
AR work/divisor/Behavioral 1336086317 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336086316 |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd |
EN work/INTERCON_P2P 1336085206 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
EN work/INTERCON_P2P 1336086328 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/INTERCON_P2P/Behavioral 1336085207 \ |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336085206 \ |
AR work/INTERCON_P2P/Behavioral 1336086329 \ |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336086328 \ |
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/03.23:01:52 O.87xd |
PH work/pkgDefinitions 1336085186 \ |
PH work/pkgDefinitions 1336086308 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1336085187 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336085186 |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.00:46:23 O.87xd |
EN work/SERIALMASTER 1336085202 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
PB work/pkgDefinitions 1336086309 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336086308 |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.01:05:05 O.87xd |
EN work/SERIALMASTER 1336086324 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336085187 |
AR work/SERIALMASTER/Behavioral 1336085203 \ |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336085202 |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336086309 |
AR work/SERIALMASTER/Behavioral 1336086325 \ |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336086324 |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd |
EN work/serial_receiver 1336085192 \ |
EN work/serial_receiver 1336086314 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \ |
PB work/pkgDefinitions 1336085187 |
AR work/serial_receiver/Behavioral 1336085193 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336085192 |
PB work/pkgDefinitions 1336086309 |
AR work/serial_receiver/Behavioral 1336086315 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336086314 |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
EN work/serial_transmitter 1336085190 \ |
EN work/serial_transmitter 1336086312 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336085187 |
AR work/serial_transmitter/Behavioral 1336085191 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336086309 |
AR work/serial_transmitter/Behavioral 1336086313 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1336085190 |
EN work/serial_transmitter 1336086312 |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd |
EN work/SYC0001a 1336085200 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \ |
EN work/SYC0001a 1336086322 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/SYC0001a/SYC0001a1 1336085201 \ |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336085200 |
AR work/SYC0001a/SYC0001a1 1336086323 \ |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336086322 |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd |
EN work/uart_communication_blocks 1336085198 \ |
EN work/uart_communication_blocks 1336086320 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336085187 |
AR work/uart_communication_blocks/Behavioral 1336085199 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336086309 |
AR work/uart_communication_blocks/Behavioral 1336086321 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1336085198 CP baud_generator \ |
EN work/uart_communication_blocks 1336086320 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_control 1336085196 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1336086318 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336085187 |
AR work/uart_control/Behavioral 1336085197 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336085196 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336086309 |
AR work/uart_control/Behavioral 1336086319 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336086318 \ |
CP divisor |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_wishbone_slave 1336085204 \ |
EN work/uart_wishbone_slave 1336086326 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336085187 |
AR work/uart_wishbone_slave/Behavioral 1336085205 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336086309 |
AR work/uart_wishbone_slave/Behavioral 1336086327 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1336085204 CP uart_control \ |
EN work/uart_wishbone_slave 1336086326 CP uart_control \ |
CP uart_communication_blocks |
/xst/work/hdllib.ref
1,22 → 1,22
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336085199 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336085197 |
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336085201 |
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336085206 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336085187 |
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336085192 |
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336085205 |
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336085191 |
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336085198 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336085194 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336085195 |
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336085189 |
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336085200 |
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336085202 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336085196 |
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336085207 |
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336085190 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336085186 |
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336085203 |
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336085204 |
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336085188 |
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336085193 |
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336086321 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336086319 |
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336086323 |
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336086328 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336086309 |
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336086314 |
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336086327 |
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336086313 |
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336086320 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336086316 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336086317 |
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336086311 |
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336086322 |
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336086324 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336086318 |
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336086329 |
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336086312 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336086308 |
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336086325 |
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336086326 |
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336086310 |
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336086315 |