URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block/trunk/hdl
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/iseProject/isim.log
1,19 → 1,19
ISim log file |
Running: E:\uart_block\hdl\iseProject\testDivisor_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testDivisor_isim_beh.wdb |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 us |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testDivisor.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim log file |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 us |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testSerial_receiver.vhd:stim_proc |
|
INFO: Simulator is stopped. |
/iseProject/serial_receiver.vhd
129,12 → 129,12
|
when bit7 => |
data_ready <= '0'; |
byteReceived(7) := serial_in; |
byteReceived(7) := serial_in; |
data_byte <= byteReceived; |
next_s <= rx_stop; |
|
when rx_stop => |
data_ready <= '1'; |
data_byte <= byteReceived; |
data_ready <= '1'; |
next_s <= rx_stop; |
end case; |
|
/iseProject/fuseRelaunch.cmd
1,12 → 129,12
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testDivisor_beh.prj" "testDivisor" |
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver" |
/iseProject/uart_control.vhd
6,21 → 6,26
use work.pkgDefinitions.all; |
|
entity uart_control is |
Port ( rst : in STD_LOGIC; |
clk : in STD_LOGIC; |
WE : in STD_LOGIC; |
reg_addr : in STD_LOGIC_VECTOR (1 downto 0); |
DAT_I : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); |
DAT_O : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); |
tx_busy : in STD_LOGIC; |
rx_ready : in STD_LOGIC); |
Port ( rst : in STD_LOGIC; -- Global reset |
clk : in STD_LOGIC; -- Global clock |
WE : in STD_LOGIC; -- Write enable |
reg_addr : in STD_LOGIC_VECTOR (1 downto 0); -- Register address |
start : in std_logic; -- Start (Strobe) |
done : out std_logic; -- Done (ACK) |
DAT_I : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Data Input (Wishbone) |
DAT_O : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Data output (Wishbone) |
baud_wait : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0); -- Signal to control the baud rate frequency |
data_byte_tx : out std_logic_vector((nBits-1) downto 0); -- 1 Byte to be send to serial_transmitter |
data_byte_rx : in std_logic_vector((nBits-1) downto 0); -- 1 Byte to be received by serial_receiver |
tx_data_sent : in STD_LOGIC; -- Signal comming from serial_transmitter |
rx_data_ready : in STD_LOGIC); -- Signal comming from serial_receiver |
end uart_control; |
|
architecture Behavioral of uart_control is |
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0); |
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0); |
signal byte_out : std_logic_vector((nBitsLarge-1) downto 0); |
signal byte_in : std_logic_vector((nBitsLarge-1) downto 0); |
signal byte_to_receive : std_logic_vector((nBitsLarge-1) downto 0); |
signal byte_to_transmitt : std_logic_vector((nBitsLarge-1) downto 0); |
signal controlStates : uartControl; |
|
signal sigDivRst : std_logic; |
53,16 → 58,39
done => sigDivDone |
); |
|
-- Process that populate/read the uart control registers |
-- Process that read uart control registers |
process (rst, clk, reg_addr,WE) |
begin |
if rising_edge(clk) then |
if (WE = '0') and (start = '1') then |
case reg_addr is |
when "00" => |
DAT_O <= config_clk; |
when "01" => |
DAT_O <= config_baud; |
when "10" => |
-- Byte that will be transmitted |
DAT_O <= "0000000000000000000000000" & byte_to_transmitt; |
when "11" => |
-- Byte that will be received |
DAT_O <= "0000000000000000000000000" & byte_to_receive; |
when others => |
null; |
end case; |
end if; |
end if; |
end process; |
|
-- Process that populate the uart control registers |
process (rst, clk, reg_addr,WE) |
begin |
if rst = '1' then |
config_clk <= (others => '0'); |
config_baud <= (others => '0'); |
byte_out <= (others => '0'); |
byte_in <= (others => '0'); |
byte_to_transmitt <= (others => '0'); |
byte_to_receive <= (others => '0'); |
elsif rising_edge(clk) then |
if WE = '1' then |
if (WE = '1') and (start = '1') then |
case reg_addr is |
when "00" => |
config_clk <= DAT_I; |
69,7 → 97,8
when "01" => |
config_baud <= DAT_I; |
when "10" => |
byte_out <= DAT_I((nBits-1) downto 0); |
-- Byte that will be transmitted |
byte_to_transmitt <= DAT_I((nBits-1) downto 0); |
when others => |
null; |
end case; |
80,15 → 109,19
-- Process to handle the next state logic |
process (rst, clk, reg_addr, WE) |
variable baud_configured : std_logic; |
variable clk_configured : std_logic; |
variable clk_configured : std_logic; |
variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0); |
begin |
if rst = '1' then |
controlStates <= idle; |
baud_configured <= '0'; |
clk_configured <= '0'; |
clk_configured <= '0'; |
div_result_baud_wait <= (others => '0'); |
done <= '0'; |
elsif rising_edge(clk) then |
case controlStates is |
when idle => |
done <= '0'; |
-- Go to config state |
if (reg_addr = "00") and (WE = '1') then |
controlStates <= config_state_clk; |
100,10 → 133,11
|
when config_state_clk => |
sigDivRst <= '1'; |
sigDivNumerator <= config_clk; |
sigDivNumerator <= config_clk; |
if baud_configured = '0' then |
-- Baud not configured yet so wait for it... |
controlStates <= idle; |
controlStates <= idle; |
done <= '1'; |
else |
-- If already configured wait for division completion... |
controlStates <= start_division; |
111,10 → 145,11
|
when config_state_baud => |
sigDivRst <= '1'; |
sigDivDividend <= config_baud; |
sigDivDividend <= config_baud; |
if clk_configured = '0' then |
-- Clock not configured yet so wait for it... |
controlStates <= idle; |
controlStates <= idle; |
done <= '1'; |
else |
-- If already configured wait for division completion... |
controlStates <= start_division; |
128,9 → 163,54
if sigDivDone = '0' then |
controlStates <= wait_division; |
else |
-- Division done, configure the Baud generator |
end if; |
|
-- Division done, get the result to put on the wait_cycles signal of the baud generator |
div_result_baud_wait := sigDivQuotient; |
controlStates <= config_state_baud_generator; |
end if; |
|
when config_state_baud_generator => |
-- Configure the wait_cycle for the desired baud rate... |
baud_wait <= div_result_baud_wait; |
controlStates <= rx_tx_state; |
done <= '1'; |
|
-- Control the serial_receiver or serial_transmitter block |
when rx_tx_state => |
controlStates <= rx_tx_state; |
if (WE = '1') and (start = '1') then |
if reg_addr = "10" then |
controlStates <= tx_state_wait; |
done <= '0'; |
end if; |
end if; |
|
if (WE = '0') and (start = '1') then |
if reg_addr = "11" then |
controlStates <= rx_state_wait; |
done <= '0'; |
end if; |
end if; |
|
|
-- Send data and wait to transmit |
when tx_state_wait => |
data_byte_tx <= byte_to_transmitt; |
if tx_data_sent = '0' then |
controlStates <= tx_state_wait; |
else |
controlStates <= rx_tx_state; |
done <= '1'; |
end if; |
|
-- Receive data and wait to receive |
when rx_state_wait => |
if rx_data_ready = '1' then |
byte_to_receive <= data_byte_rx; |
done <= '1'; |
controlStates <= rx_tx_state; |
else |
controlStates <= rx_state_wait; |
end if; |
end case; |
end if; |
end process; |
/iseProject/iseProject.gise
69,7 → 69,9
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDivisor_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDivisor_isim_beh.wdb"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testSerial_receiver_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> |
81,7 → 83,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335706001" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335706001"> |
<transform xil_pn:end_ts="1335769526" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335769526"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
95,11 → 97,11
<outfile xil_pn:name="testSerial_transmitter.vhd"/> |
<outfile xil_pn:name="uart_control.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335706001" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6042613676112735766" xil_pn:start_ts="1335706001"> |
<transform xil_pn:end_ts="1335769140" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8542187049970039926" xil_pn:start_ts="1335769140"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335706001" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4641732051429320088" xil_pn:start_ts="1335706001"> |
<transform xil_pn:end_ts="1335769140" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8521261985131728908" xil_pn:start_ts="1335769140"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
107,7 → 109,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335706001" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335706001"> |
<transform xil_pn:end_ts="1335769526" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335769526"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
121,22 → 123,24
<outfile xil_pn:name="testSerial_transmitter.vhd"/> |
<outfile xil_pn:name="uart_control.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335706004" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1599609758225969422" xil_pn:start_ts="1335706001"> |
<transform xil_pn:end_ts="1335769528" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1335769526"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testDivisor_beh.prj"/> |
<outfile xil_pn:name="testDivisor_isim_beh.exe"/> |
<outfile xil_pn:name="testSerial_receiver_beh.prj"/> |
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1335706004" xil_pn:in_ck="6966519603717532447" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4515288970544773250" xil_pn:start_ts="1335706004"> |
<transform xil_pn:end_ts="1335769528" xil_pn:in_ck="9031792592001735694" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7589868709935752726" xil_pn:start_ts="1335769528"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testDivisor_isim_beh.wdb"/> |
<outfile xil_pn:name="testSerial_receiver_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1334961610" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1334961610"> |
<status xil_pn:value="SuccessfullyRun"/> |
/iseProject/pkgDefinitions.vhd
25,7 → 25,8
type rxStates is (rx_idle, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, rx_stop); |
type rxFilterStates is (s0, s1, s2, s3); |
|
type uartControl is (idle, config_state_clk, config_state_baud, start_division, wait_division, rcv_command, wait_state); |
type uartControl is (idle, config_state_clk, config_state_baud, start_division, wait_division, config_state_baud_generator, |
rx_tx_state, tx_state_wait, rx_state_wait); |
|
end pkgDefinitions; |
|
/iseProject/testSerial_receiver_beh.prj
1,3 → 1,3
vhdl work "pkgDefinitions.vhd" |
vhdl work "serial_receiver.vhd" |
vhdl work "testSerial_receiver.vhd" |
vhdl work "pkgDefinitions.vhd" |
vhdl work "serial_receiver.vhd" |
vhdl work "testSerial_receiver.vhd" |
/iseProject/testSerial_receiver_isim_beh.wdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/iseProject/fuse.log
1,22 → 1,23
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testDivisor_beh.prj testDivisor |
ISim O.87xd (signature 0xc3576ebc) |
Number of CPUs detected in this system: 8 |
Turning on mult-threading, number of parallel sub-compilation jobs: 16 |
Determining compilation order of HDL files |
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/testDivisor.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity divisor [divisor_default] |
Compiling architecture behavior of entity testdivisor |
Time Resolution for simulation is 1ps. |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 7 VHDL Units |
Built simulation executable E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe |
Fuse Memory Usage: 33532 KB |
Fuse CPU Usage: 264 ms |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
Determining compilation order of HDL files |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 36024 KB |
Fuse CPU Usage: 1120 ms |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default] |
Compiling architecture behavior of entity testserial_receiver |
Time Resolution for simulation is 1ps. |
Compiled 6 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe |
Fuse Memory Usage: 79448 KB |
Fuse CPU Usage: 1150 ms |
GCC CPU Usage: 310 ms |
/iseProject/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/iseProject/fuse.xmsgs
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
</messages> |
|
|
/iseProject/xilinxsim.ini
1,9 → 1,9
work=isim/work |
work=isim/work |
/iseProject/isim.cmd
1,3 → 1,3
onerror {resume} |
wave add / |
run 1000 us; |
onerror {resume} |
wave add / |
run 1000 us; |
/iseProject/iseProject.xise
30,21 → 30,21
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/> |
</file> |
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/> |
</file> |
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="43"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="43"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/> |
89,7 → 89,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
287,8 → 287,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDivisor" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDivisor" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testSerial_receiver" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
304,7 → 304,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDivisor" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
353,7 → 353,7
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDivisor|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testSerial_receiver|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |