URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block/trunk/hdl
- from Rev 15 to Rev 16
- ↔ Reverse comparison
Rev 15 → Rev 16
/iseProject/isim.log
1,5 → 1,5
ISim log file |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
8,13 → 8,13
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 us |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testSerial_receiver.vhd:stim_proc |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
# exit 0 |
/iseProject/serial_receiver_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>baud_generator Project Status (05/01/2012 - 14:17:44)</B></TD></TR> |
<TD ALIGN=CENTER COLSPAN='4'><B>baud_generator Project Status (05/01/2012 - 14:33:26)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>iseProject.xise</TD> |
109,5 → 109,5
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 05/01/2012 - 14:17:44</center> |
<br><center><b>Date Generated:</b> 05/01/2012 - 14:33:26</center> |
</BODY></HTML> |
/iseProject/fuseRelaunch.cmd
1,5 → 109,5
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver" |
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
/iseProject/uart_control.vhd
33,7 → 33,7
signal sigDivRst : std_logic; |
signal sigDivDone : std_logic; |
signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0); |
signal sigDivReminder : std_logic_vector((nBitsLarge-1) downto 0); |
--signal sigDivReminder : std_logic_vector((nBitsLarge-1) downto 0); |
signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0); |
signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0); |
|
54,7 → 54,7
rst => sigDivRst, |
clk => clk, |
quotient => sigDivQuotient, |
reminder => sigDivReminder, |
reminder => open, -- Indicates that this port will not be connected to anything |
numerator => sigDivNumerator, |
divident => sigDivDividend, |
done => sigDivDone |
84,7 → 84,7
end process; |
|
-- Process that populate the uart control registers |
process (rst, clk, reg_addr,WE) |
process (rst, clk, reg_addr,WE,start) |
begin |
if rst = '1' then |
config_clk <= (others => '0'); |
/iseProject/iseProject.gise
78,12 → 78,13
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testSerial_receiver_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_wishbone_slave_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_communication_blocks.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_communication_blocks.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_communication_blocks.ngc"/> |
130,7 → 131,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335873519" xil_pn:in_ck="7038098250406169239" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335873519"> |
<transform xil_pn:end_ts="1335878101" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335878101"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
144,27 → 145,26
<outfile xil_pn:name="testSerial_transmitter.vhd"/> |
<outfile xil_pn:name="testUart_communication_block.vhd"/> |
<outfile xil_pn:name="testUart_control.vhd"/> |
<outfile xil_pn:name="testUart_wishbone_slave.vhd"/> |
<outfile xil_pn:name="uart_communication_blocks.vhd"/> |
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335871207" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8542187049970039926" xil_pn:start_ts="1335871207"> |
<transform xil_pn:end_ts="1335877111" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335877111"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335871207" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8521261985131728908" xil_pn:start_ts="1335871207"> |
<transform xil_pn:end_ts="1335877111" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335877111"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335863913" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="3554467849218202431" xil_pn:start_ts="1335863913"> |
<transform xil_pn:end_ts="1335876275" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335876275"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForProperties"/> |
</transform> |
<transform xil_pn:end_ts="1335873519" xil_pn:in_ck="7038098250406169239" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335873519"> |
<transform xil_pn:end_ts="1335878101" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335878101"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
<outfile xil_pn:name="divisor.vhd"/> |
<outfile xil_pn:name="pkgDefinitions.vhd"/> |
176,73 → 176,77
<outfile xil_pn:name="testSerial_transmitter.vhd"/> |
<outfile xil_pn:name="testUart_communication_block.vhd"/> |
<outfile xil_pn:name="testUart_control.vhd"/> |
<outfile xil_pn:name="testUart_wishbone_slave.vhd"/> |
<outfile xil_pn:name="uart_communication_blocks.vhd"/> |
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335873521" xil_pn:in_ck="7038098250406169239" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1335873519"> |
<transform xil_pn:end_ts="1335878103" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335878101"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testSerial_receiver_beh.prj"/> |
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/> |
<outfile xil_pn:name="testUart_wishbone_slave_beh.prj"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1335873521" xil_pn:in_ck="4271185753694017635" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7589868709935752726" xil_pn:start_ts="1335873521"> |
<transform xil_pn:end_ts="1335878103" xil_pn:in_ck="-5691276081812346650" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335878103"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testSerial_receiver_isim_beh.wdb"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1335863867" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335863867"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874652" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8823898246834051963" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1008586360203480345" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874652" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6954442057973343307" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874652" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874652" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1772223502880435709" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7853110446436427671" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874652" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874652" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2739977836635169173" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875592" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2852686481009242409" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335874662" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1567333096778139784" xil_pn:start_ts="1335874652"> |
<transform xil_pn:end_ts="1335875605" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8823216100926192740" xil_pn:start_ts="1335875592"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="divisor.lso"/> |
<outfile xil_pn:name="divisor.ngc"/> |
<outfile xil_pn:name="baud_generator.ngr"/> |
<outfile xil_pn:name="divisor.ngr"/> |
<outfile xil_pn:name="divisor.prj"/> |
<outfile xil_pn:name="divisor.stx"/> |
<outfile xil_pn:name="divisor.syr"/> |
<outfile xil_pn:name="divisor.xst"/> |
<outfile xil_pn:name="divisor_xst.xrpt"/> |
<outfile xil_pn:name="serial_receiver.ngr"/> |
<outfile xil_pn:name="serial_transmitter.ngr"/> |
<outfile xil_pn:name="uart_communication_blocks.ngr"/> |
<outfile xil_pn:name="uart_control.ngr"/> |
<outfile xil_pn:name="uart_wishbone_slave.lso"/> |
<outfile xil_pn:name="uart_wishbone_slave.ngc"/> |
<outfile xil_pn:name="uart_wishbone_slave.ngr"/> |
<outfile xil_pn:name="uart_wishbone_slave.prj"/> |
<outfile xil_pn:name="uart_wishbone_slave.stx"/> |
<outfile xil_pn:name="uart_wishbone_slave.syr"/> |
<outfile xil_pn:name="uart_wishbone_slave.xst"/> |
<outfile xil_pn:name="uart_wishbone_slave_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
/iseProject/fuse.log
1,23 → 1,40
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
Determining compilation order of HDL files |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work |
WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 36024 KB |
Fuse CPU Usage: 1080 ms |
Fuse Memory Usage: 37476 KB |
Fuse CPU Usage: 1100 ms |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package std_logic_unsigned |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity divisor [divisor_default] |
Compiling architecture behavioral of entity uart_control [uart_control_default] |
Compiling package numeric_std |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default] |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default] |
Compiling architecture behavior of entity testserial_receiver |
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...] |
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Time Resolution for simulation is 1ps. |
Compiled 6 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe |
Fuse Memory Usage: 79448 KB |
Fuse CPU Usage: 1110 ms |
GCC CPU Usage: 300 ms |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 21 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 90276 KB |
Fuse CPU Usage: 1280 ms |
GCC CPU Usage: 670 ms |
/iseProject/testUart_wishbone_slave.vhd
0,0 → 1,122
--! Test uart_wishbone_slave (Main test module) |
LIBRARY ieee; |
USE ieee.std_logic_1164.ALL; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
--! Use Global Definitions package |
use work.pkgDefinitions.all; |
|
ENTITY testUart_wishbone_slave IS |
END testUart_wishbone_slave; |
|
ARCHITECTURE behavior OF testUart_wishbone_slave IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT uart_wishbone_slave |
PORT( |
RST_I : IN std_logic; |
CLK_I : IN std_logic; |
ADR_I0 : IN std_logic_vector(1 downto 0); |
DAT_I0 : IN std_logic_vector(31 downto 0); |
DAT_O0 : OUT std_logic_vector(31 downto 0); |
WE_I : IN std_logic; |
STB_I : IN std_logic; |
ACK_O : OUT std_logic; |
serial_in : IN std_logic; |
serial_out : OUT std_logic |
); |
END COMPONENT; |
|
|
--Inputs |
signal RST_I : std_logic := '0'; |
signal CLK_I : std_logic := '0'; |
signal ADR_I0 : std_logic_vector(1 downto 0) := (others => '0'); |
signal DAT_I0 : std_logic_vector(31 downto 0) := (others => '0'); |
signal WE_I : std_logic := '0'; |
signal STB_I : std_logic := '0'; |
signal serial_in : std_logic := '0'; |
|
--Outputs |
signal DAT_O0 : std_logic_vector(31 downto 0); |
signal ACK_O : std_logic; |
signal serial_out : std_logic; |
|
-- Clock period definitions (1.8432MHz) |
constant CLK_I_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz) |
|
BEGIN |
|
-- Instantiate the Unit Under Test (UUT) |
uut: uart_wishbone_slave PORT MAP ( |
RST_I => RST_I, |
CLK_I => CLK_I, |
ADR_I0 => ADR_I0, |
DAT_I0 => DAT_I0, |
DAT_O0 => DAT_O0, |
WE_I => WE_I, |
STB_I => STB_I, |
ACK_O => ACK_O, |
serial_in => serial_in, |
serial_out => serial_out |
); |
|
-- Clock process definitions |
CLK_I_process :process |
begin |
CLK_I <= '0'; |
wait for CLK_I_period/2; |
CLK_I <= '1'; |
wait for CLK_I_period/2; |
end process; |
|
|
-- Stimulus process |
stim_proc: process |
begin |
-- Reset the slave |
RST_I <= '1'; |
wait for 1 ns; |
RST_I <= '0'; |
wait for CLK_I_period*3; |
|
-- Configure the clock... |
ADR_I0 <= "00"; |
WE_I <= '1'; |
STB_I <= '1'; |
DAT_I0 <= conv_std_logic_vector(50000000, (nBitsLarge)); |
wait until ACK_O = '1'; |
WE_I <= '0'; |
STB_I <= '0'; |
ADR_I0 <= (others => 'U'); |
wait for CLK_I_period; |
|
-- Configure the Baud... |
ADR_I0 <= "01"; |
WE_I <= '1'; |
STB_I <= '1'; |
DAT_I0 <= conv_std_logic_vector(115200, (nBitsLarge)); |
wait until ACK_O = '1'; |
WE_I <= '0'; |
STB_I <= '0'; |
ADR_I0 <= (others => 'U'); |
wait for CLK_I_period; |
|
-- Ask to send some data...(0xC4) |
ADR_I0 <= "10"; |
WE_I <= '1'; |
STB_I <= '1'; |
DAT_I0 <= x"000000C4"; |
wait until ACK_O = '1'; |
WE_I <= '0'; |
STB_I <= '0'; |
ADR_I0 <= (others => 'U'); |
wait for CLK_I_period; |
|
-- Stop Simulation |
assert false report "NONE. End of simulation." severity failure; |
end process; |
|
END; |
/iseProject/webtalk_pn.xml
3,7 → 3,7
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Tue May 1 14:17:33 2012"> |
<application name="pn" timeStamp="Tue May 1 14:33:13 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="0" type="project"/> |
/iseProject/serial_transmitter_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>baud_generator Project Status (05/01/2012 - 14:17:44)</B></TD></TR> |
<TD ALIGN=CENTER COLSPAN='4'><B>baud_generator Project Status (05/01/2012 - 14:33:27)</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>iseProject.xise</TD> |
109,5 → 109,5
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 05/01/2012 - 14:17:44</center> |
<br><center><b>Date Generated:</b> 05/01/2012 - 14:33:27</center> |
</BODY></HTML> |
/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work</arg> |
</msg> |
|
</messages> |
/iseProject/_xmsgs/xst.xmsgs
5,5 → 5,317
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">53</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uBaudGen</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="new" >The FF/Latch <<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>> in Unit <<arg fmt="%s" index="2">serial_receiver</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><data_ready> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uUartControl/uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_wishbone_slave</arg>>. |
</msg> |
|
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. |
</msg> |
|
</messages> |
|
/iseProject/baud_generator.vhd
39,7 → 39,7
wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, nBitsLarge); |
-- If we're at half of the cycle |
if wait_clk_cycles = half_cycle then |
genTick <= '0'; |
genTick <= '0'; |
end if; |
end if; |
|
/iseProject/fuse.xmsgs
5,5 → 5,8
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression |
</msg> |
|
</messages> |
|
/iseProject/isim.cmd
1,3 → 1,3
onerror {resume} |
wave add / |
run 1000 us; |
run 1000 ms; |
/iseProject/pepExtractor.prj
1,3 → 1,8
work "baud_generator.vhd" |
work "divisor.vhd" |
work "pkgDefinitions.vhd" |
work "serial_receiver.vhd" |
work "serial_transmitter.vhd" |
work "uart_communication_blocks.vhd" |
work "uart_control.vhd" |
work "uart_wishbone_slave.vhd" |
/iseProject/iseProject.xise
16,8 → 16,8
|
<files> |
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
30,18 → 30,18
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/> |
</file> |
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/> |
</file> |
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
50,8 → 50,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/> |
</file> |
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
60,8 → 60,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/> |
</file> |
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
70,8 → 70,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/> |
</file> |
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
80,9 → 80,15
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/> |
</file> |
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/> |
</file> |
</files> |
|
<properties> |
188,9 → 194,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|divisor|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="divisor.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave/uUartControl/uDiv" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_wishbone_slave|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_wishbone_slave.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
248,7 → 254,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="divisor" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
260,10 → 266,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="divisor_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="divisor_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="divisor_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="divisor_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_wishbone_slave_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="uart_wishbone_slave_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_wishbone_slave_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_wishbone_slave_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
283,7 → 289,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="divisor" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
307,8 → 313,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testSerial_receiver" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
316,7 → 322,7
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 us" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ms" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
324,7 → 330,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
373,7 → 379,7
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testSerial_receiver|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
/iseProject/xst/work/hdpdeps.ref
1,64 → 1,64
V3 34 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.08:42:17 O.87xd |
EN work/baud_generator 1335874507 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
EN work/baud_generator 1335875598 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \ |
PB work/pkgDefinitions 1335874657 |
AR work/baud_generator/Behavioral 1335874508 \ |
PB work/pkgDefinitions 1335875597 |
AR work/baud_generator/Behavioral 1335875599 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
EN work/baud_generator 1335874507 |
EN work/baud_generator 1335875598 |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
EN work/divisor 1335874658 \ |
EN work/divisor 1335875604 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1335874657 |
AR work/divisor/Behavioral 1335874659 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335874658 |
PB work/pkgDefinitions 1335875597 |
AR work/divisor/Behavioral 1335875605 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335875604 |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.13:49:58 O.87xd |
PH work/pkgDefinitions 1335874656 \ |
PH work/pkgDefinitions 1335875596 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1335874657 \ |
PB work/pkgDefinitions 1335875597 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PH work/pkgDefinitions 1335874656 |
PH work/pkgDefinitions 1335875596 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
EN work/serial_receiver 1335874481 \ |
EN work/serial_receiver 1335875602 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335874657 |
AR work/serial_receiver/Behavioral 1335874482 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/serial_receiver/Behavioral 1335875603 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
EN work/serial_receiver 1335874481 |
EN work/serial_receiver 1335875602 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
EN work/serial_transmitter 1335874538 \ |
EN work/serial_transmitter 1335875600 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335874657 |
AR work/serial_transmitter/Behavioral 1335874539 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/serial_transmitter/Behavioral 1335875601 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1335874538 |
EN work/serial_transmitter 1335875600 |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
EN work/uart_communication_blocks 1335802845 \ |
EN work/uart_communication_blocks 1335875608 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335874657 |
AR work/uart_communication_blocks/Behavioral 1335802846 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/uart_communication_blocks/Behavioral 1335875609 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1335802845 CP baud_generator \ |
EN work/uart_communication_blocks 1335875608 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/04/30.18:12:57 O.87xd |
EN work/uart_control 1335802843 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/01.14:32:36 O.87xd |
EN work/uart_control 1335875606 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335874657 |
AR work/uart_control/Behavioral 1335802844 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/uart_control/Behavioral 1335875607 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1335802843 CP divisor |
EN work/uart_control 1335875606 CP divisor |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
EN work/uart_wishbone_slave 1335802847 \ |
EN work/uart_wishbone_slave 1335875610 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335874657 |
AR work/uart_wishbone_slave/Behavioral 1335802848 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335875597 |
AR work/uart_wishbone_slave/Behavioral 1335875611 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1335802847 CP uart_control \ |
EN work/uart_wishbone_slave 1335875610 CP uart_control \ |
CP uart_communication_blocks |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd |
/iseProject/xst/work/hdllib.ref
1,16 → 1,16
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335802843 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335874539 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335802847 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335874508 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335874481 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335874658 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335874659 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335874538 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335802846 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335802848 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335874482 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335802845 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335874657 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335802844 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335874507 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335874656 |
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335875606 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335875601 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335875610 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335875599 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335875602 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335875604 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335875605 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335875600 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335875609 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335875611 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335875603 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335875608 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335875597 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335875607 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335875598 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335875596 |