URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block/trunk/hdl
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/iseProject/isim.log
17,3 → 17,116
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 0 fs : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 30 |
# run all |
Stopped at time : 24706500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
Stopped at time : 25249500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
Stopped at time : 25792500 ps : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
Stopped at time : 1821 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 46 |
# run all |
Stopped at time : 8765 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" Line 87 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 87 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 870 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" Line 35 |
# run all |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 9627710 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" Line 60 |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
Stopped at time : 87690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 125 |
# run all |
Stopped at time : 96330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 91 |
# run all |
Stopped at time : 105010 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 96 |
# run all |
Stopped at time : 113690 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 101 |
# run all |
Stopped at time : 122370 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 106 |
# run all |
Stopped at time : 131050 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 111 |
# run all |
Stopped at time : 139730 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 116 |
# run all |
Stopped at time : 148410 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 121 |
# run all |
Stopped at time : 157090 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 126 |
# run all |
Stopped at time : 165770 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" Line 132 |
# run all |
Stopped at time : 9633330 ns : File "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" Line 71 |
# exit 0 |
/iseProject/iseProject.gise
51,6 → 51,7
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="serial_receiver.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="serial_receiver.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="serial_receiver.ngc"/> |
130,7 → 131,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335878953" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335878953"> |
<transform xil_pn:end_ts="1335879371" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335879371"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
161,7 → 162,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335878953" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335878953"> |
<transform xil_pn:end_ts="1335879371" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335879371"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
180,19 → 181,23
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335878957" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335878953"> |
<transform xil_pn:end_ts="1335879373" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335879371"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testUart_wishbone_slave_beh.prj"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1335878957" xil_pn:in_ck="-5691276081812346650" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335878957"> |
<transform xil_pn:end_ts="1335879373" xil_pn:in_ck="-5691276081812346650" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335879373"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1335863867" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335863867"> |
/iseProject/fuse.log
1,4 → 1,4
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -relaunch -intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
16,7 → 16,7
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 37476 KB |
Fuse CPU Usage: 1100 ms |
Fuse CPU Usage: 1110 ms |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
32,9 → 32,9
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Time Resolution for simulation is 1ps. |
Waiting for 5 sub-compilation(s) to finish... |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 21 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 90148 KB |
Fuse CPU Usage: 1280 ms |
GCC CPU Usage: 4350 ms |
Fuse Memory Usage: 89256 KB |
Fuse CPU Usage: 1270 ms |
GCC CPU Usage: 150 ms |
/iseProject/testUart_wishbone_slave.vhd
45,7 → 45,7
signal serial_out : std_logic; |
|
-- Clock period definitions (1.8432MHz) |
constant CLK_I_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz) |
constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz) |
|
BEGIN |
|
78,9 → 78,9
begin |
-- Reset the slave |
RST_I <= '1'; |
wait for 1 ns; |
wait for CLK_I_period; |
RST_I <= '0'; |
wait for CLK_I_period*3; |
wait for CLK_I_period; |
|
-- Configure the clock... |
ADR_I0 <= "00"; |
114,7 → 114,12
STB_I <= '0'; |
ADR_I0 <= (others => 'U'); |
wait for CLK_I_period; |
|
|
-- Ask to send some data...(0xC4) |
ADR_I0 <= "11"; |
WE_I <= '1'; |
STB_I <= '1'; |
|
-- Receive data... |
-- Receive 0x55 value (01010101) |
serial_in <= '0'; -- Start bit |
140,6 → 145,11
-- Stop bit here |
serial_in <= '1'; |
wait for CLK_I_period*20; |
|
wait until ACK_O = '1'; |
WE_I <= '0'; |
STB_I <= '0'; |
wait for CLK_I_period; |
|
-- Stop Simulation |
assert false report "NONE. End of simulation." severity failure; |