URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block/trunk/hdl
- from Rev 25 to Rev 27
- ↔ Reverse comparison
Rev 25 → Rev 27
/iseProject/pkgDefinitions.vhd
27,6 → 27,8
|
type sendByte is (idle, prepare_byte, start_sending, wait_completion); |
|
type testMaster is (idle, config_clock, config_baud, send_byte, receive_byte, wait_cycles); |
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end pkgDefinitions; |
|
package body pkgDefinitions is |
/iseProject/iseProject.gise
22,6 → 22,66
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="iseProject.xise"/> |
|
<files xmlns="http://www.xilinx.com/XMLSchema"> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="INTERCON_P2P.bld"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="INTERCON_P2P.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="INTERCON_P2P.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P.ncd" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="INTERCON_P2P.ngc"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="INTERCON_P2P.ngd"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="INTERCON_P2P.ngr"/> |
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="INTERCON_P2P.pad"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="INTERCON_P2P.par" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="INTERCON_P2P.pcf" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="INTERCON_P2P.prj"/> |
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="INTERCON_P2P.ptwx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="INTERCON_P2P.stx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="INTERCON_P2P.syr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="INTERCON_P2P.twr" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="INTERCON_P2P.twx" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="INTERCON_P2P.unroutes" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="INTERCON_P2P.ut" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:fileType="FILE_XPI" xil_pn:name="INTERCON_P2P.xpi"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="INTERCON_P2P.xst"/> |
<file xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P_guide.ncd" xil_pn:origination="imported"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="INTERCON_P2P_map.map" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="INTERCON_P2P_map.mrp" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P_map.ncd" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="INTERCON_P2P_map.ngm" xil_pn:subbranch="Map"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_map.xrpt"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_ngdbuild.xrpt"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="INTERCON_P2P_pad.csv" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="INTERCON_P2P_pad.txt" xil_pn:subbranch="Par"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_par.xrpt"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="INTERCON_P2P_summary.xml"/> |
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="INTERCON_P2P_usage.xml"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="INTERCON_P2P_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="INTERCON_P2P_xst.xrpt"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SERIALMASTER.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SERIALMASTER.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SERIALMASTER.ngc"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SERIALMASTER.ngr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SERIALMASTER.prj"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SERIALMASTER.stx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SERIALMASTER.syr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SERIALMASTER.xst"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SERIALMASTER_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SERIALMASTER_xst.xrpt"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SYC0001a.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SYC0001a.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SYC0001a.ngc"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SYC0001a.ngr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SYC0001a.prj"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SYC0001a.stx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SYC0001a.syr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SYC0001a.xst"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SYC0001a_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SYC0001a_xst.xrpt"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="baud_generator.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="baud_generator.lso"/> |
49,6 → 109,9
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="divisor_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="divisor_xst.xrpt"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="intercon_p2p.bgn" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="intercon_p2p.bit" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="intercon_p2p.drc" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> |
122,8 → 185,11
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_wishbone_slave_summary.html"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_wishbone_slave_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_wishbone_slave_xst.xrpt"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> |
</files> |
|
135,6 → 201,11
<transform xil_pn:end_ts="1335914584" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335914584"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
<outfile xil_pn:name="divisor.vhd"/> |
<outfile xil_pn:name="pkgDefinitions.vhd"/> |
162,10 → 233,16
<transform xil_pn:end_ts="1335914584" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335914584"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForProperties"/> |
</transform> |
<transform xil_pn:end_ts="1335914584" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335914584"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
<outfile xil_pn:name="divisor.vhd"/> |
<outfile xil_pn:name="pkgDefinitions.vhd"/> |
185,7 → 262,10
<transform xil_pn:end_ts="1335914587" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335914584"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
198,6 → 278,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputChanged"/> |
207,50 → 288,123
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1008586360203480345" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5756048480961623240" xil_pn:start_ts="1336081902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1430910882053507873" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7719148281395352834" xil_pn:start_ts="1336081902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1336081902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7853110446436427671" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4641019278670948490" xil_pn:start_ts="1336081902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1336081902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2852686481009242409" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2912634102501063032" xil_pn:start_ts="1336081902"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335914580" xil_pn:in_ck="-2826982315966499730" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8823216100926192740" xil_pn:start_ts="1335914570"> |
<transform xil_pn:end_ts="1336085196" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336085185"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="INTERCON_P2P.lso"/> |
<outfile xil_pn:name="INTERCON_P2P.ngc"/> |
<outfile xil_pn:name="INTERCON_P2P.ngr"/> |
<outfile xil_pn:name="INTERCON_P2P.prj"/> |
<outfile xil_pn:name="INTERCON_P2P.stx"/> |
<outfile xil_pn:name="INTERCON_P2P.syr"/> |
<outfile xil_pn:name="INTERCON_P2P.xst"/> |
<outfile xil_pn:name="INTERCON_P2P_vhdl.prj"/> |
<outfile xil_pn:name="INTERCON_P2P_xst.xrpt"/> |
<outfile xil_pn:name="SERIALMASTER.ngr"/> |
<outfile xil_pn:name="SYC0001a.ngr"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="serial_receiver.ngr"/> |
<outfile xil_pn:name="serial_transmitter.ngr"/> |
<outfile xil_pn:name="uart_control.ngr"/> |
<outfile xil_pn:name="uart_wishbone_slave.lso"/> |
<outfile xil_pn:name="uart_wishbone_slave.ngc"/> |
<outfile xil_pn:name="uart_wishbone_slave.ngr"/> |
<outfile xil_pn:name="uart_wishbone_slave.prj"/> |
<outfile xil_pn:name="uart_wishbone_slave.stx"/> |
<outfile xil_pn:name="uart_wishbone_slave.syr"/> |
<outfile xil_pn:name="uart_wishbone_slave.xst"/> |
<outfile xil_pn:name="uart_wishbone_slave_vhdl.prj"/> |
<outfile xil_pn:name="uart_wishbone_slave_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1336084618" xil_pn:in_ck="2653651478373773795" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-7776376010671116565" xil_pn:start_ts="1336084618"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336085201" xil_pn:in_ck="-1408796339596843907" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336085196"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.bld"/> |
<outfile xil_pn:name="INTERCON_P2P.ngd"/> |
<outfile xil_pn:name="INTERCON_P2P_ngdbuild.xrpt"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336085204" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336085201"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.pcf"/> |
<outfile xil_pn:name="INTERCON_P2P_map.map"/> |
<outfile xil_pn:name="INTERCON_P2P_map.mrp"/> |
<outfile xil_pn:name="INTERCON_P2P_map.ncd"/> |
<outfile xil_pn:name="INTERCON_P2P_map.ngm"/> |
<outfile xil_pn:name="INTERCON_P2P_map.xrpt"/> |
<outfile xil_pn:name="INTERCON_P2P_summary.xml"/> |
<outfile xil_pn:name="INTERCON_P2P_usage.xml"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336085222" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336085204"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.ncd"/> |
<outfile xil_pn:name="INTERCON_P2P.pad"/> |
<outfile xil_pn:name="INTERCON_P2P.par"/> |
<outfile xil_pn:name="INTERCON_P2P.ptwx"/> |
<outfile xil_pn:name="INTERCON_P2P.unroutes"/> |
<outfile xil_pn:name="INTERCON_P2P.xpi"/> |
<outfile xil_pn:name="INTERCON_P2P_pad.csv"/> |
<outfile xil_pn:name="INTERCON_P2P_pad.txt"/> |
<outfile xil_pn:name="INTERCON_P2P_par.xrpt"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336085230" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336085222"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.ut"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<outfile xil_pn:name="intercon_p2p.bgn"/> |
<outfile xil_pn:name="intercon_p2p.bit"/> |
<outfile xil_pn:name="intercon_p2p.drc"/> |
<outfile xil_pn:name="usage_statistics_webtalk.html"/> |
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1336082874" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336082870"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="InputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1336085222" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336085220"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.twr"/> |
<outfile xil_pn:name="INTERCON_P2P.twx"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
</transform> |
</transforms> |
|
</generated_project> |
/iseProject/SERIALMASTER.vhd
0,0 → 1,117
--! Top wishbone Master to test the uart_wishbone_slave |
library ieee; |
USE ieee.std_logic_1164.ALL; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
--! Use CPU Definitions package |
use work.pkgDefinitions.all; |
|
entity SERIALMASTER is |
port( |
-- WISHBONE Signals |
ACK_I: in std_logic; |
ADR_O: out std_logic_vector( 1 downto 0 ); |
CLK_I: in std_logic; |
CYC_O: out std_logic; |
DAT_I: in std_logic_vector( 31 downto 0 ); |
DAT_O: out std_logic_vector( 31 downto 0 ); |
RST_I: in std_logic; |
SEL_O: out std_logic; |
STB_O: out std_logic; |
WE_O: out std_logic; |
|
-- NON-WISHBONE Signals |
byte_rec : out std_logic_vector(7 downto 0) |
); |
|
end SERIALMASTER; |
|
architecture Behavioral of SERIALMASTER is |
signal masterSerialStates : testMaster; |
signal byteIncome : std_logic_vector(7 downto 0); |
begin |
|
process (CLK_I) |
variable contWait : integer range 0 to 50000000; |
variable nextState: testMaster; |
begin |
if rising_edge(CLK_I) then |
if RST_I = '1' then |
masterSerialStates <= idle; |
nextState := idle; |
contWait := 0; |
byteIncome <= (others => '0'); |
else |
case masterSerialStates is |
when idle => |
masterSerialStates <= config_clock; |
nextState := idle; |
|
when config_clock => |
nextState := config_baud; |
ADR_O <= "00"; |
WE_O <= '1'; |
STB_O <= '1'; |
DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge)); -- 50Mhz |
if ACK_I = '1' then |
-- Byte received wait some cycles to continue |
masterSerialStates <= wait_cycles; |
byte_rec <= "00000001"; |
end if; |
|
when config_baud => |
nextState := send_byte; |
ADR_O <= "01"; |
WE_O <= '1'; |
STB_O <= '1'; |
DAT_O <= conv_std_logic_vector(115200, (nBitsLarge)); --115200 bps |
if ACK_I = '1' then |
-- Byte received wait some cycles to continue |
masterSerialStates <= wait_cycles; |
byte_rec <= "00000010"; |
end if; |
|
when send_byte => |
nextState := receive_byte; |
ADR_O <= "10"; |
WE_O <= '1'; |
STB_O <= '1'; |
--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@' |
DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@' |
if ACK_I = '1' then |
-- Byte received wait some cycles to continue |
masterSerialStates <= wait_cycles; |
byte_rec <= "00000100"; |
end if; |
|
when receive_byte => |
nextState := send_byte; |
ADR_O <= "11"; |
WE_O <= '0'; |
STB_O <= '1'; |
if ACK_I = '1' then |
-- Byte received wait some cycles to continue |
masterSerialStates <= wait_cycles; |
byte_rec <= DAT_I(7 downto 0); |
byteIncome <= DAT_I(7 downto 0); |
--byte_rec <= "00001000"; |
end if; |
|
when wait_cycles => |
-- wait some cycles (90) |
if contWait < 25000000 then |
contWait := contWait + 1; |
STB_O <= '0'; |
else |
contWait := 0; |
masterSerialStates <= nextState; |
end if; |
end case; |
end if; |
end if; |
end process; |
|
|
end Behavioral; |
|
/iseProject/SYC0001a.vhd
0,0 → 1,74
---------------------------------------------------------------------- |
-- Module name: SYC0001a.VHD |
-- |
-- Description: A simple WISHBONE SYSCON for FPGA. For more infor- |
-- mation, please refer to the WISHBONE Public Domain |
-- Library Technical Reference Manual. |
-- |
-- History: Project complete: SEP 20, 2001 |
-- WD Peterson |
-- Silicore Corporation |
-- |
-- Release: Notice is hereby given that this document is not |
-- copyrighted, and has been placed into the public |
-- domain. It may be freely copied and distributed |
-- by any means. |
-- |
-- Disclaimer: In no event shall Silicore Corporation be liable |
-- for incidental, consequential, indirect or special |
-- damages resulting from the use of this file. The |
-- user assumes all responsibility for its use. |
-- |
---------------------------------------------------------------------- |
|
---------------------------------------------------------------------- |
-- Load the IEEE 1164 library and make it visible. |
---------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
|
---------------------------------------------------------------------- |
-- Entity declaration. |
---------------------------------------------------------------------- |
|
entity SYC0001a is |
port( |
-- WISHBONE Interface |
|
CLK_O: out std_logic; |
RST_O: out std_logic; |
|
|
-- NON-WISHBONE Signals |
|
EXTCLK: in std_logic; |
EXTRST: in std_logic |
); |
|
end SYC0001a; |
|
|
---------------------------------------------------------------------- |
-- Architecture definition. |
---------------------------------------------------------------------- |
|
architecture SYC0001a1 of SYC0001a IS |
|
begin |
|
|
------------------------------------------------------------------ |
-- Make selected signals available to the outside world. |
------------------------------------------------------------------ |
|
MAKE_VISIBLE: process( EXTCLK, EXTRST ) |
begin |
|
CLK_O <= EXTCLK; |
RST_O <= EXTRST; |
|
end process MAKE_VISIBLE; |
|
end architecture SYC0001a1; |
/iseProject/INTERCON_P2P.vhd
0,0 → 1,111
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
entity INTERCON_P2P is |
port ( |
-- External (non-WISHBONE) inputs |
EXTCLK: in std_logic; |
EXTRST: in std_logic; |
-- External signals for simulation purposes |
byte_out: out std_logic_vector(7 downto 0); |
data_avaible : out std_logic; |
tx: out std_logic; |
rx : in std_logic |
); |
end INTERCON_P2P; |
|
architecture Behavioral of INTERCON_P2P is |
component SYC0001a |
port( |
-- WISHBONE Interface |
CLK_O: out std_logic; |
RST_O: out std_logic; |
-- NON-WISHBONE Signals |
EXTCLK: in std_logic; |
EXTRST: in std_logic |
); |
end component SYC0001a; |
|
component SERIALMASTER is |
port( |
-- WISHBONE Signals |
ACK_I: in std_logic; |
ADR_O: out std_logic_vector( 1 downto 0 ); |
CLK_I: in std_logic; |
CYC_O: out std_logic; |
DAT_I: in std_logic_vector( 31 downto 0 ); |
DAT_O: out std_logic_vector( 31 downto 0 ); |
RST_I: in std_logic; |
SEL_O: out std_logic; |
STB_O: out std_logic; |
WE_O: out std_logic; |
|
-- NON-WISHBONE Signals |
byte_rec : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component uart_wishbone_slave is |
Port ( RST_I : in STD_LOGIC; |
CLK_I : in STD_LOGIC; |
ADR_I0 : in STD_LOGIC_VECTOR (1 downto 0); |
DAT_I0 : in STD_LOGIC_VECTOR (31 downto 0); |
DAT_O0 : out STD_LOGIC_VECTOR (31 downto 0); |
WE_I : in STD_LOGIC; |
STB_I : in STD_LOGIC; |
ACK_O : out STD_LOGIC; |
serial_in : in std_logic; |
data_Avaible : out std_logic; |
serial_out : out std_logic |
); |
end component; |
signal CLK : std_logic; |
signal RST : std_logic; |
signal ACK : std_logic; |
signal WE : std_logic; |
signal STB : std_logic; |
signal ADR : std_logic_vector( 1 downto 0 ); |
signal dataI : std_logic_vector (31 downto 0); |
signal dataO : std_logic_vector (31 downto 0); |
begin |
uSysCon: component SYC0001a |
port map( |
CLK_O => CLK, |
RST_O => RST, |
EXTCLK => EXTCLK, |
EXTRST => EXTRST |
); |
|
uMasterSerial : component SERIALMASTER |
port map( |
ACK_I => ACK, |
ADR_O => ADR, |
CLK_I => CLK, |
CYC_O => open, |
DAT_I => dataI, |
DAT_O => dataO, |
RST_I => RST, |
SEL_O => open, |
STB_O => STB, |
byte_rec => byte_out, |
WE_O => WE |
); |
|
uUartWishboneSlave: component uart_wishbone_slave |
port map( |
RST_I => RST, |
CLK_I => CLK, |
ADR_I0 => ADR, |
DAT_I0 => dataO, |
DAT_O0 => dataI, |
WE_I => WE, |
STB_I => STB, |
ACK_O => ACK, |
serial_in => rx, |
data_Avaible => open, |
serial_out => tx |
); |
|
end Behavioral; |
|
/iseProject/pins_spartan3EStarterKit.ucf
0,0 → 1,19
NET "EXTCLK" LOC = "c9"| IOSTANDARD = LVCMOS33 ; |
|
NET "EXTRST" LOC = "n17"| IOSTANDARD = LVCMOS33 ; |
|
NET "byte_out<7>" LOC = "f9"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<6>" LOC = "e9"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<5>" LOC = "d11"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<4>" LOC = "c11"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<3>" LOC = "f11"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<2>" LOC = "e11"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<1>" LOC = "e12"| IOSTANDARD = LVCMOS33 ; |
NET "byte_out<0>" LOC = "f12"| IOSTANDARD = LVCMOS33 ; |
|
#NET "data_avaible" LOC = "u17"| IOSTANDARD = LVCMOS33 ; |
|
NET "tx" LOC = "m14"| IOSTANDARD = LVCMOS33 ; #m14 |
|
NET "rx" LOC = "r7"| IOSTANDARD = LVCMOS33 ; #r7 |
|
/iseProject/webtalk_pn.xml
1,47 → 1,49
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Wed May 2 17:54:07 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="0" type="project"/> |
<property name="ProjectFile" value="/home/laraujo/work/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
<section name="Project Statistics" visible="true"> |
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> |
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/> |
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
<property name="PROP_FitterReportFormat" value="HTML" type="process"/> |
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
<property name="PROP_UseSmartGuide" value="false" type="design"/> |
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/> |
<property name="PROP_DevFamily" value="Spartan3E" type="design"/> |
<property name="PROP_DevDevice" value="xc3s500e" type="design"/> |
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> |
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/> |
<property name="PROP_DevPackage" value="fg320" type="design"/> |
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_VHDL" value="15" type="source"/> |
</section> |
</application> |
</document> |
<?xml version="1.0" encoding="UTF-8" ?> |
<document> |
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Fri May 04 00:46:44 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="13" type="project"/> |
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
<section name="Project Statistics" visible="true"> |
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/> |
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/> |
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/> |
<property name="PROP_FitterReportFormat" value="HTML" type="process"/> |
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/> |
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
<property name="PROP_UseSmartGuide" value="false" type="design"/> |
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWbtProjectIteration" value="13" type="process"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_DevFamily" value="Spartan3E" type="design"/> |
<property name="PROP_DevDevice" value="xc3s500e" type="design"/> |
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/> |
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 ms" type="process"/> |
<property name="PROP_DevPackage" value="fg320" type="design"/> |
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_UCF" value="1" type="source"/> |
<property name="FILE_VHDL" value="18" type="source"/> |
</section> |
</application> |
</document> |
/iseProject/_xmsgs/pn_parser.xmsgs
1,36 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/iseProject/_xmsgs/xst.xmsgs
1,111 → 1,941
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">62</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">80</arg>: Unconnected output port '<arg fmt="%s" index="3">CYC_O</arg>' of component '<arg fmt="%s" index="4">SERIALMASTER</arg>'. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">80</arg>: Unconnected output port '<arg fmt="%s" index="3">SEL_O</arg>' of component '<arg fmt="%s" index="4">SERIALMASTER</arg>'. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd</arg>" line <arg fmt="%d" index="2">95</arg>: Unconnected output port '<arg fmt="%s" index="3">data_Avaible</arg>' of component '<arg fmt="%s" index="4">uart_wishbone_slave</arg>'. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">62</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">DAT_I<31:8></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">CYC_O</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">SEL_O</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="warning" file="Xst" num="1306" delta="old" >Output <<arg fmt="%s" index="1">data_avaible</arg>> is never assigned. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">5 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><cycle_wait_oversample_30> <half_cycle_31> <half_cycle0_31> <half_cycle0_30> <half_cycle0_29> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">uBaudGen</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_clk_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">config_baud_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uBaudGen</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uMasterSerial</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">N_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">D_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uDiv</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivDividend_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">uUartControl</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="new" >FF/Latch <<arg fmt="%s" index="1">DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">half_cycle0_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">baud_generator</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_24</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_25> <half_cycle0_23> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_7</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_8> <half_cycle0_6> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_19</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_20> <half_cycle0_18> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_20</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_21> <half_cycle0_19> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_15</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_16> <half_cycle0_14> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_0</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_30> <half_cycle0_28> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_3</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_4> <half_cycle0_2> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_27</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_28> <half_cycle0_26> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_23</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_24> <half_cycle0_22> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_8</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_9> <half_cycle0_7> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_5</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_6> <half_cycle0_4> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_18</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_19> <half_cycle0_17> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_14</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_15> <half_cycle0_13> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_28</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_29> <half_cycle0_27> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_26</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_27> <half_cycle0_25> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_1</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_2> <half_cycle0_0> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_22</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_23> <half_cycle0_21> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_17</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_18> <half_cycle0_16> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_13</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_14> <half_cycle0_12> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_9</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_10> <half_cycle0_8> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_6</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_7> <half_cycle0_5> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_11</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_12> <half_cycle0_10> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_25</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_26> <half_cycle0_24> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_21</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_22> <half_cycle0_20> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_16</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_17> <half_cycle0_15> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_2</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_3> <half_cycle0_1> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_12</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_13> <half_cycle0_11> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_10</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_11> <half_cycle0_9> </arg> |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">cycle_wait_oversample_4</arg>> in Unit <<arg fmt="%s" index="2">baud_generator</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><half_cycle_5> <half_cycle0_3> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch <<arg fmt="%s" index="1">nextState_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">current_s_FSM_FFd1</arg>> in Unit <<arg fmt="%s" index="2">serial_receiver</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><data_ready> </arg> |
</msg> |
|
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">uart_control</arg>: <arg fmt="%d" index="2">32</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_clk_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/config_baud_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivNumerator_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/sigDivDividend_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/D_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/N_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">INTERCON_P2P</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_31</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_30</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_29</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_28</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_27</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_26</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_24</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_18</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_11</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_10</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">uUartWishboneSlave/uUartControl/Mtridata_DAT_O_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">INTERCON_P2P</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<11></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<18></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<24></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<26></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<27></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<28></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<29></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<30></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<31></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="warning" file="Xst" num="638" delta="old" >in unit <arg fmt="%s" index="1">INTERCON_P2P</arg> Conflict on KEEP property on signal <arg fmt="%s" index="2">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<8></arg> and <arg fmt="%s" index="3">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> <arg fmt="%s" index="4">uUartWishboneSlave/uUartControl/Mtridata_DAT_O<10></arg> signal will be lost. |
</msg> |
|
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. |
</msg> |
|
</messages> |
|
|
/iseProject/iseProject.xise
17,7 → 17,7
<files> |
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
31,7 → 31,7
</file> |
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
41,7 → 41,7
</file> |
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
51,7 → 51,7
</file> |
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
61,7 → 61,7
</file> |
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
71,7 → 71,7
</file> |
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
81,7 → 81,7
</file> |
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
89,6 → 89,21
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/> |
</file> |
<file xil_pn:name="SYC0001a.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
</file> |
<file xil_pn:name="SERIALMASTER.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
</file> |
<file xil_pn:name="INTERCON_P2P.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="141"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
<file xil_pn:name="pins_spartan3EStarterKit.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
|
<properties> |
115,7 → 130,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
194,9 → 209,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_wishbone_slave|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_wishbone_slave.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|INTERCON_P2P|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="INTERCON_P2P.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/INTERCON_P2P" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
254,7 → 269,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="INTERCON_P2P" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
266,10 → 281,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_wishbone_slave_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="uart_wishbone_slave_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_wishbone_slave_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_wishbone_slave_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="INTERCON_P2P_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="INTERCON_P2P_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="INTERCON_P2P_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="INTERCON_P2P_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
289,7 → 304,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="INTERCON_P2P" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
339,6 → 354,7
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Target UCF File Name" xil_pn:value="pins_spartan3EStarterKit.ucf" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
394,7 → 410,9
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
<bindings> |
<binding xil_pn:location="/INTERCON_P2P" xil_pn:name="pins_spartan3EStarterKit.ucf"/> |
</bindings> |
|
<libraries/> |
|
/iseProject/xst/work/hdpdeps.ref
1,71 → 1,81
V3 39 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
EN work/baud_generator 1335938431 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \ |
PB work/pkgDefinitions 1335974051 |
AR work/baud_generator/Behavioral 1335938432 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
EN work/baud_generator 1335938431 |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
EN work/divisor 1335974052 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1335974051 |
AR work/divisor/Behavioral 1335974053 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335974052 |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/02.17:47:51 O.87xd |
PH work/pkgDefinitions 1335974050 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1335974051 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PH work/pkgDefinitions 1335974050 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
EN work/serial_receiver 1335938435 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335974051 |
AR work/serial_receiver/Behavioral 1335938436 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
EN work/serial_receiver 1335938435 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
EN work/serial_transmitter 1335938433 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335974051 |
AR work/serial_transmitter/Behavioral 1335938434 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1335938433 |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
EN work/uart_communication_blocks 1335938441 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335974051 |
AR work/uart_communication_blocks/Behavioral 1335938442 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1335938441 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.17:54:04 O.87xd |
EN work/uart_control 1335974054 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335974051 |
AR work/uart_control/Behavioral 1335974055 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1335974054 CP divisor |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
EN work/uart_wishbone_slave 1335938443 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335974051 |
AR work/uart_wishbone_slave/Behavioral 1335938444 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1335938443 CP uart_control \ |
CP uart_communication_blocks |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/01.23:44:07 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.01:14:06 O.87xd |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.23:14:46 O.87xd |
V3 51 |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.14:25:52 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/02.17:47:51 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.17:54:04 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd |
EN work/baud_generator 1336085188 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \ |
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \ |
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336085187 |
AR work/baud_generator/Behavioral 1336085189 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336085188 |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
EN work/divisor 1336085194 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1336085187 |
AR work/divisor/Behavioral 1336085195 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336085194 |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd |
EN work/INTERCON_P2P 1336085206 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/INTERCON_P2P/Behavioral 1336085207 \ |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336085206 \ |
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/03.23:01:52 O.87xd |
PH work/pkgDefinitions 1336085186 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1336085187 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336085186 |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.00:46:23 O.87xd |
EN work/SERIALMASTER 1336085202 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336085187 |
AR work/SERIALMASTER/Behavioral 1336085203 \ |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336085202 |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd |
EN work/serial_receiver 1336085192 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \ |
PB work/pkgDefinitions 1336085187 |
AR work/serial_receiver/Behavioral 1336085193 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336085192 |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
EN work/serial_transmitter 1336085190 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336085187 |
AR work/serial_transmitter/Behavioral 1336085191 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1336085190 |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd |
EN work/SYC0001a 1336085200 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/SYC0001a/SYC0001a1 1336085201 \ |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336085200 |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd |
EN work/uart_communication_blocks 1336085198 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336085187 |
AR work/uart_communication_blocks/Behavioral 1336085199 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1336085198 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_control 1336085196 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336085187 |
AR work/uart_control/Behavioral 1336085197 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336085196 \ |
CP divisor |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_wishbone_slave 1336085204 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336085187 |
AR work/uart_wishbone_slave/Behavioral 1336085205 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1336085204 CP uart_control \ |
CP uart_communication_blocks |
/iseProject/xst/work/hdllib.ref
1,16 → 1,22
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335974054 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335938434 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335938443 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335938432 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335938435 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335974052 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335974053 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335938433 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335938442 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335938444 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335938436 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335938441 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335974051 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335974055 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335938431 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335974050 |
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336085199 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336085197 |
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336085201 |
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336085206 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336085187 |
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336085192 |
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336085205 |
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336085191 |
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336085198 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336085194 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336085195 |
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336085189 |
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336085200 |
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336085202 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336085196 |
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336085207 |
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336085190 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336085186 |
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336085203 |
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336085204 |
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336085188 |
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336085193 |
/iseProject/xst/work/sub00/vhpl00.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/iseProject/xst/work/sub00/vhpl01.vho
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream