URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block/trunk/hdl
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/iseProject/iseProject.gise
42,6 → 42,8
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="INTERCON_P2P.ut" xil_pn:subbranch="FPGAConfiguration"/> |
<file xil_pn:fileType="FILE_XPI" xil_pn:name="INTERCON_P2P.xpi"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="INTERCON_P2P.xst"/> |
<file xil_pn:fileType="FILE_BLIF" xil_pn:name="INTERCON_P2P_cs.blc"/> |
<file xil_pn:fileType="FILE_NGC" xil_pn:name="INTERCON_P2P_cs.ngc"/> |
<file xil_pn:fileType="FILE_NCD" xil_pn:name="INTERCON_P2P_guide.ncd" xil_pn:origination="imported"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="INTERCON_P2P_map.map" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="INTERCON_P2P_map.mrp" xil_pn:subbranch="Map"/> |
288,31 → 290,31
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5756048480961623240" xil_pn:start_ts="1336081902"> |
<transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5756048480961623240" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7719148281395352834" xil_pn:start_ts="1336081902"> |
<transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7719148281395352834" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1336081902"> |
<transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4641019278670948490" xil_pn:start_ts="1336081902"> |
<transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4641019278670948490" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1336081902"> |
<transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336081902" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2912634102501063032" xil_pn:start_ts="1336081902"> |
<transform xil_pn:end_ts="1336089718" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2912634102501063032" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336086318" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336086306"> |
<transform xil_pn:end_ts="1336089729" xil_pn:in_ck="4673194791943474574" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-8986552465892320357" xil_pn:start_ts="1336089718"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
341,18 → 343,24
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336086322" xil_pn:in_ck="-1408796339596843907" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336086318"> |
<transform xil_pn:end_ts="1336089834" xil_pn:in_ck="4758608941402184672" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336089729"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.bld"/> |
<outfile xil_pn:name="INTERCON_P2P.ngd"/> |
<outfile xil_pn:name="INTERCON_P2P_cs.blc"/> |
<outfile xil_pn:name="INTERCON_P2P_cs.ngc"/> |
<outfile xil_pn:name="INTERCON_P2P_ngdbuild.xrpt"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336086325" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336086322"> |
<transform xil_pn:end_ts="1336089837" xil_pn:in_ck="7070038919220904605" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1336089834"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="INTERCON_P2P.pcf"/> |
<outfile xil_pn:name="INTERCON_P2P_map.map"/> |
<outfile xil_pn:name="INTERCON_P2P_map.mrp"/> |
363,7 → 371,7
<outfile xil_pn:name="INTERCON_P2P_usage.xml"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336086342" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336086325"> |
<transform xil_pn:end_ts="1336089848" xil_pn:in_ck="5901297062896623158" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1336089837"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
378,8 → 386,9
<outfile xil_pn:name="INTERCON_P2P_par.xrpt"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1336086350" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336086342"> |
<transform xil_pn:end_ts="1336089858" xil_pn:in_ck="-1437695683665201866" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1336089848"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.ut"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
390,17 → 399,17
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
</transform> |
<transform xil_pn:end_ts="1336082874" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336082870"> |
<transform xil_pn:end_ts="1336089864" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1336089862"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="InputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1336086342" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336086340"> |
<transform xil_pn:end_ts="1336089917" xil_pn:in_ck="-5263026143922103232" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7171404100274592149" xil_pn:start_ts="1336089917"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1336089848" xil_pn:in_ck="-5119142186248317927" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1336089846"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="INTERCON_P2P.twr"/> |
<outfile xil_pn:name="INTERCON_P2P.twx"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
/iseProject/debugChip.cdc
0,0 → 1,59
#ChipScope Core Inserter Project File Version 3.0 |
#Fri May 04 02:01:35 CEST 2012 |
Project.device.designInputFile=E\:\\uart_block\\hdl\\iseProject\\INTERCON_P2P_cs.ngc |
Project.device.designOutputFile=E\:\\uart_block\\hdl\\iseProject\\INTERCON_P2P_cs.ngc |
Project.device.deviceFamily=13 |
Project.device.enableRPMs=true |
Project.device.outputDirectory=E\:\\uart_block\\hdl\\iseProject\\_ngo |
Project.device.useSRL16=true |
Project.filter.dimension=8 |
Project.filter<0>= |
Project.filter<1>=*_OBUF* |
Project.filter<2>=*_OBUF |
Project.filter<3>=_OBUF |
Project.filter<4>=*DAT_* |
Project.filter<5>=*byte* |
Project.filter<6>=byte* |
Project.filter<7>=byte |
Project.icon.boundaryScanChain=1 |
Project.icon.enableExtTriggerIn=false |
Project.icon.enableExtTriggerOut=false |
Project.icon.triggerInPinName= |
Project.icon.triggerOutPinName= |
Project.unit.dimension=1 |
Project.unit<0>.clockChannel=EXTCLK_BUFGP |
Project.unit<0>.clockEdge=Rising |
Project.unit<0>.dataChannel<0>=uMasterSerial/DAT_O<0> |
Project.unit<0>.dataChannel<1>=uMasterSerial/DAT_O<1> |
Project.unit<0>.dataChannel<2>=uMasterSerial/DAT_O<2> |
Project.unit<0>.dataChannel<3>=uMasterSerial/DAT_O<3> |
Project.unit<0>.dataChannel<4>=uMasterSerial/DAT_O<4> |
Project.unit<0>.dataChannel<5>=uMasterSerial/DAT_O<5> |
Project.unit<0>.dataChannel<6>=uMasterSerial/DAT_O<6> |
Project.unit<0>.dataChannel<7>=uMasterSerial/DAT_O<7> |
Project.unit<0>.dataDepth=512 |
Project.unit<0>.dataEqualsTrigger=true |
Project.unit<0>.dataPortWidth=8 |
Project.unit<0>.enableGaps=false |
Project.unit<0>.enableStorageQualification=false |
Project.unit<0>.enableTimestamps=false |
Project.unit<0>.timestampDepth=0 |
Project.unit<0>.timestampWidth=0 |
Project.unit<0>.triggerChannel<0><0>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<0> |
Project.unit<0>.triggerChannel<0><1>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<1> |
Project.unit<0>.triggerChannel<0><2>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<2> |
Project.unit<0>.triggerChannel<0><3>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<3> |
Project.unit<0>.triggerChannel<0><4>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<4> |
Project.unit<0>.triggerChannel<0><5>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<5> |
Project.unit<0>.triggerChannel<0><6>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<6> |
Project.unit<0>.triggerChannel<0><7>=uUartWishboneSlave/uUartCommunicationBlocks/uReceiver/data_byte<7> |
Project.unit<0>.triggerConditionCountWidth=0 |
Project.unit<0>.triggerMatchCount<0>=1 |
Project.unit<0>.triggerMatchCountWidth<0><0>=0 |
Project.unit<0>.triggerMatchType<0><0>=0 |
Project.unit<0>.triggerPortCount=1 |
Project.unit<0>.triggerPortIsData<0>=true |
Project.unit<0>.triggerPortWidth<0>=8 |
Project.unit<0>.triggerSequencerLevels=16 |
Project.unit<0>.triggerSequencerType=0 |
Project.unit<0>.type=ilapro |
/iseProject/webtalk_pn.xml
3,10 → 3,10
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Fri May 04 01:05:25 2012"> |
<application name="pn" timeStamp="Fri May 04 02:03:58 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="20" type="project"/> |
<property name="ProjectIteration" value="23" type="project"/> |
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/> |
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/> |
</section> |
27,7 → 27,7
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> |
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/> |
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWbtProjectIteration" value="20" type="process"/> |
<property name="PROP_intWbtProjectIteration" value="23" type="process"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> |
42,6 → 42,7
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/> |
<property name="PROP_DevSpeed" value="-4" type="design"/> |
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/> |
<property name="FILE_CDC" value="1" type="source"/> |
<property name="FILE_UCF" value="1" type="source"/> |
<property name="FILE_VHDL" value="18" type="source"/> |
</section> |
/iseProject/_xmsgs/pn_parser.xmsgs
8,8 → 8,5
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/SERIALMASTER.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/iseProject/_xmsgs/xst.xmsgs
512,13 → 512,13
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_3</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_4</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_4</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_5</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="new" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_23</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">cycles2Wait_23</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
</msg> |
|
<msg type="warning" file="Xst" num="1896" delta="old" >Due to other FF/Latch trimming, FF/Latch <<arg fmt="%s" index="1">nextState_1</arg>> has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">SERIALMASTER</arg>>. This FF/Latch will be trimmed during the optimization process. |
/iseProject/iseProject.xise
104,6 → 104,9
<file xil_pn:name="pins_spartan3EStarterKit.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="debugChip.cdc" xil_pn:type="FILE_CDC"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
|
<properties> |
412,6 → 415,7
|
<bindings> |
<binding xil_pn:location="/INTERCON_P2P" xil_pn:name="pins_spartan3EStarterKit.ucf"/> |
<binding xil_pn:location="/INTERCON_P2P" xil_pn:name="debugChip.cdc"/> |
</bindings> |
|
<libraries/> |
/iseProject/xst/work/hdpdeps.ref
9,73 → 9,73
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd 2012/05/01.21:07:49 O.87xd |
EN work/baud_generator 1336086310 \ |
EN work/baud_generator 1336089722 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd PB ieee/std_logic_1164 1325952872 \ |
PB ieee/STD_LOGIC_UNSIGNED 1325952875 PB ieee/std_logic_arith 1325952873 \ |
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336086309 |
AR work/baud_generator/Behavioral 1336086311 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336086310 |
PB ieee/NUMERIC_STD 1325952877 PB work/pkgDefinitions 1336089721 |
AR work/baud_generator/Behavioral 1336089723 \ |
FL E:/uart_block/hdl/iseProject/baud_generator.vhd EN work/baud_generator 1336089722 |
FL E:/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.21:07:49 O.87xd |
EN work/divisor 1336086316 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
EN work/divisor 1336089728 FL E:/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1336086309 |
AR work/divisor/Behavioral 1336086317 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336086316 |
PB work/pkgDefinitions 1336089721 |
AR work/divisor/Behavioral 1336089729 \ |
FL E:/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1336089728 |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd 2012/05/04.00:27:06 O.87xd |
EN work/INTERCON_P2P 1336086328 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
EN work/INTERCON_P2P 1336089740 FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/INTERCON_P2P/Behavioral 1336086329 \ |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336086328 \ |
AR work/INTERCON_P2P/Behavioral 1336089741 \ |
FL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd EN work/INTERCON_P2P 1336089740 \ |
CP SYC0001a CP SERIALMASTER CP uart_wishbone_slave |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/03.23:01:52 O.87xd |
PH work/pkgDefinitions 1336086308 \ |
PH work/pkgDefinitions 1336089720 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1336086309 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336086308 |
PB work/pkgDefinitions 1336089721 \ |
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1336089720 |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd 2012/05/04.01:05:05 O.87xd |
EN work/SERIALMASTER 1336086324 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
EN work/SERIALMASTER 1336089736 FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336086309 |
AR work/SERIALMASTER/Behavioral 1336086325 \ |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336086324 |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336089721 |
AR work/SERIALMASTER/Behavioral 1336089737 \ |
FL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd EN work/SERIALMASTER 1336089736 |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.21:07:49 O.87xd |
EN work/serial_receiver 1336086314 \ |
EN work/serial_receiver 1336089726 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \ |
PB work/pkgDefinitions 1336086309 |
AR work/serial_receiver/Behavioral 1336086315 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336086314 |
PB work/pkgDefinitions 1336089721 |
AR work/serial_receiver/Behavioral 1336089727 \ |
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1336089726 |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd |
EN work/serial_transmitter 1336086312 \ |
EN work/serial_transmitter 1336089724 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336086309 |
AR work/serial_transmitter/Behavioral 1336086313 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336089721 |
AR work/serial_transmitter/Behavioral 1336089725 \ |
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1336086312 |
EN work/serial_transmitter 1336089724 |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd 2012/05/04.00:26:54 O.87xd |
EN work/SYC0001a 1336086322 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \ |
EN work/SYC0001a 1336089734 FL E:/uart_block/hdl/iseProject/SYC0001a.vhd \ |
PB ieee/std_logic_1164 1325952872 |
AR work/SYC0001a/SYC0001a1 1336086323 \ |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336086322 |
AR work/SYC0001a/SYC0001a1 1336089735 \ |
FL E:/uart_block/hdl/iseProject/SYC0001a.vhd EN work/SYC0001a 1336089734 |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.23:14:46 O.87xd |
EN work/uart_communication_blocks 1336086320 \ |
EN work/uart_communication_blocks 1336089732 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336086309 |
AR work/uart_communication_blocks/Behavioral 1336086321 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336089721 |
AR work/uart_communication_blocks/Behavioral 1336089733 \ |
FL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1336086320 CP baud_generator \ |
EN work/uart_communication_blocks 1336089732 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL E:/uart_block/hdl/iseProject/uart_control.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_control 1336086318 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1336089730 FL E:/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336086309 |
AR work/uart_control/Behavioral 1336086319 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336086318 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1336089721 |
AR work/uart_control/Behavioral 1336089731 \ |
FL E:/uart_block/hdl/iseProject/uart_control.vhd EN work/uart_control 1336089730 \ |
CP divisor |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/05/03.19:17:33 O.87xd |
EN work/uart_wishbone_slave 1336086326 \ |
EN work/uart_wishbone_slave 1336089738 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336086309 |
AR work/uart_wishbone_slave/Behavioral 1336086327 \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1336089721 |
AR work/uart_wishbone_slave/Behavioral 1336089739 \ |
FL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1336086326 CP uart_control \ |
EN work/uart_wishbone_slave 1336089738 CP uart_control \ |
CP uart_communication_blocks |
/iseProject/xst/work/hdllib.ref
1,22 → 1,22
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336086321 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336086319 |
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336086323 |
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336086328 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336086309 |
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336086314 |
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336086327 |
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336086313 |
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336086320 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336086316 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336086317 |
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336086311 |
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336086322 |
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336086324 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336086318 |
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336086329 |
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336086312 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336086308 |
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336086325 |
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336086326 |
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336086310 |
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336086315 |
AR uart_communication_blocks behavioral E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1336089733 |
AR uart_control behavioral E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1336089731 |
AR syc0001a syc0001a1 E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl17 1336089735 |
EN intercon_p2p NULL E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl20 1336089740 |
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1336089721 |
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1336089726 |
AR uart_wishbone_slave behavioral E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1336089739 |
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1336089725 |
EN uart_communication_blocks NULL E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1336089732 |
EN divisor NULL E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1336089728 |
AR divisor behavioral E:/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1336089729 |
AR baud_generator behavioral E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1336089723 |
EN syc0001a NULL E:/uart_block/hdl/iseProject/SYC0001a.vhd sub00/vhpl16 1336089734 |
EN serialmaster NULL E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl18 1336089736 |
EN uart_control NULL E:/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1336089730 |
AR intercon_p2p behavioral E:/uart_block/hdl/iseProject/INTERCON_P2P.vhd sub00/vhpl21 1336089741 |
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1336089724 |
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1336089720 |
AR serialmaster behavioral E:/uart_block/hdl/iseProject/SERIALMASTER.vhd sub00/vhpl19 1336089737 |
EN uart_wishbone_slave NULL E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1336089738 |
EN baud_generator NULL E:/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1336089722 |
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1336089727 |