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Rev 3 → Rev 4

/iseProject/serial_receiver.syr
120,7 → 120,7
* HDL Analysis *
=========================================================================
Analyzing Entity <serial_receiver> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/uart_block/hdl/iseProject/serial_receiver.vhd" line 76: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
WARNING:Xst:819 - "E:/uart_block/hdl/iseProject/serial_receiver.vhd" line 86: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<serial_in>
Entity <serial_receiver> analyzed. Unit <serial_receiver> generated.
 
138,7 → 138,7
| States | 10 |
| Transitions | 10 |
| Inputs | 0 |
| Outputs | 9 |
| Outputs | 10 |
| Clock | baudClk (rising_edge) |
| Reset | syncDetected (negative) |
| Reset type | asynchronous |
149,10 → 149,10
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <filterRx>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 5 |
| Inputs | 1 |
| Outputs | 3 |
| States | 4 |
| Transitions | 8 |
| Inputs | 2 |
| Outputs | 4 |
| Clock | baudOverSampleClk (rising_edge) |
| Reset | rst (positive) |
| Reset type | asynchronous |
161,18 → 161,37
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <data_byte_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 8-bit latch for signal <data_byte>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<0>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<1>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<2>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<3>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<4>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<5>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<6>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtridata_byteReceived<7>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<0>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<1>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<2>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<3>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<4>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<5>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<6>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
WARNING:Xst:736 - Found 1-bit latch for signal <Mtrien_byteReceived<7>> created at line 92. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
Found 8-bit tristate buffer for signal <byteReceived>.
Found 1-bit register for signal <syncDetected>.
Summary:
inferred 2 Finite State Machine(s).
inferred 1 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <serial_receiver> synthesized.
 
 
182,8 → 201,11
Macro Statistics
# Registers : 1
1-bit register : 1
# Latches : 8
1-bit latch : 8
# Latches : 17
1-bit latch : 16
8-bit latch : 1
# Tristates : 8
1-bit tristate buffer : 8
 
=========================================================================
 
199,6 → 221,7
s0 | 00
s1 | 01
s2 | 11
s3 | 10
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <current_s/FSM> on signal <current_s[1:10]> with one-hot encoding.
224,8 → 247,9
# FSMs : 2
# Registers : 1
Flip-Flops : 1
# Latches : 8
1-bit latch : 8
# Latches : 17
1-bit latch : 16
8-bit latch : 1
 
=========================================================================
 
232,6 → 256,7
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:2042 - Unit serial_receiver: 8 internal tristates are replaced by logic (pull-up yes): byteReceived<0>, byteReceived<1>, byteReceived<2>, byteReceived<3>, byteReceived<4>, byteReceived<5>, byteReceived<6>, byteReceived<7>.
 
Optimizing unit <serial_receiver> ...
 
275,14 → 300,19
# IOs : 13
 
Cell Usage :
# BELS : 4
# INV : 1
# LUT2 : 2
# LUT3 : 1
# FlipFlops/Latches : 21
# FDC : 12
# BELS : 39
# GND : 1
# INV : 3
# LUT2 : 12
# LUT3 : 8
# LUT4 : 14
# VCC : 1
# FlipFlops/Latches : 37
# FDC : 11
# FDCE : 1
# FDP : 1
# LD : 8
# LD : 17
# LDE : 7
# Clock Buffers : 2
# BUFGP : 2
# IO Buffers : 11
295,9 → 325,9
 
Selected Device : 3s500efg320-4
 
Number of Slices: 7 out of 4656 0%
Number of Slice Flip Flops: 13 out of 9312 0%
Number of 4 input LUTs: 4 out of 9312 0%
Number of Slices: 20 out of 4656 0%
Number of Slice Flip Flops: 29 out of 9312 0%
Number of 4 input LUTs: 37 out of 9312 0%
Number of IOs: 13
Number of bonded IOBs: 13 out of 232 5%
IOB Flip Flops: 8
321,20 → 351,26
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
baudOverSampleClk | BUFGP | 3 |
current_s_FSM_FFd2 | NONE(data_byte_7) | 1 |
current_s_FSM_FFd3 | NONE(data_byte_6) | 1 |
current_s_FSM_FFd4 | NONE(data_byte_5) | 1 |
current_s_FSM_FFd5 | NONE(data_byte_4) | 1 |
current_s_FSM_FFd6 | NONE(data_byte_3) | 1 |
current_s_FSM_FFd7 | NONE(data_byte_2) | 1 |
current_s_FSM_FFd8 | NONE(data_byte_1) | 1 |
current_s_FSM_FFd9 | NONE(data_byte_0) | 1 |
baudClk | BUFGP | 10 |
-----------------------------------+------------------------+-------+
-----------------------------------------------------------------+--------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------------------------------------+--------------------------------+-------+
baudOverSampleClk | BUFGP | 3 |
current_s_FSM_FFd8 | NONE(Mtridata_byteReceived<7>) | 7 |
Mtrien_byteReceived<7>_not0001(Mtrien_byteReceived<7>_not00011:O)| NONE(*)(Mtrien_byteReceived<7>)| 1 |
Mtrien_byteReceived<6>_not0001(Mtrien_byteReceived<6>_not0001:O) | NONE(*)(Mtrien_byteReceived<6>)| 1 |
Mtrien_byteReceived<5>_not0001(Mtrien_byteReceived<5>_not00011:O)| NONE(*)(Mtrien_byteReceived<5>)| 1 |
Mtrien_byteReceived<4>_not0001(Mtrien_byteReceived<4>_not0001:O) | NONE(*)(Mtrien_byteReceived<4>)| 1 |
Mtrien_byteReceived<3>_not0001(Mtrien_byteReceived<3>_not00011:O)| NONE(*)(Mtrien_byteReceived<3>)| 1 |
Mtrien_byteReceived<2>_not0001(Mtrien_byteReceived<2>_not00011:O)| NONE(*)(Mtrien_byteReceived<2>)| 1 |
Mtrien_byteReceived<1>_not0001(Mtrien_byteReceived<1>_not00011:O)| NONE(*)(Mtrien_byteReceived<1>)| 1 |
Mtrien_byteReceived<0>_not0001(Mtrien_byteReceived<0>_not00011:O)| NONE(*)(Mtrien_byteReceived<0>)| 1 |
current_s_FSM_FFd9 | NONE(Mtridata_byteReceived<0>) | 1 |
baudClk | BUFGP | 10 |
current_s_FSM_FFd1 | NONE(data_byte_0) | 8 |
-----------------------------------------------------------------+--------------------------------+-------+
(*) These 8 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
 
Asynchronous Control Signals Information:
351,8 → 387,8
Speed Grade: -4
 
Minimum period: 2.213ns (Maximum Frequency: 451.875MHz)
Minimum input arrival time before clock: 3.338ns
Maximum output required time after clock: 4.368ns
Minimum input arrival time before clock: 5.900ns
Maximum output required time after clock: 4.745ns
Maximum combinational path delay: No path found
 
Timing Detail:
362,15 → 398,15
=========================================================================
Timing constraint: Default period analysis for Clock 'baudOverSampleClk'
Clock period: 2.213ns (frequency: 451.875MHz)
Total number of paths / destination ports: 4 / 3
Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay: 2.213ns (Levels of Logic = 1)
Source: filterRx_FSM_FFd1 (FF)
Destination: syncDetected (FF)
Destination: filterRx_FSM_FFd2 (FF)
Source Clock: baudOverSampleClk rising
Destination Clock: baudOverSampleClk rising
 
Data Path: filterRx_FSM_FFd1 to syncDetected
Data Path: filterRx_FSM_FFd1 to filterRx_FSM_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
382,31 → 418,53
(72.4% logic, 27.6% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'current_s_FSM_FFd8'
Clock period: 2.170ns (frequency: 460.829MHz)
Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Delay: 2.170ns (Levels of Logic = 1)
Source: Mtridata_byteReceived<7> (LATCH)
Destination: Mtridata_byteReceived<7> (LATCH)
Source Clock: current_s_FSM_FFd8 rising
Destination Clock: current_s_FSM_FFd8 rising
 
Data Path: Mtridata_byteReceived<7> to Mtridata_byteReceived<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LDE:G->Q 2 0.676 0.482 Mtridata_byteReceived<7> (Mtridata_byteReceived<7>)
LUT3:I2->O 1 0.704 0.000 Mtridata_byteReceived<7>_mux00001 (Mtridata_byteReceived<7>_mux0000)
LDE:D 0.308 Mtridata_byteReceived<7>
----------------------------------------
Total 2.170ns (1.688ns logic, 0.482ns route)
(77.8% logic, 22.2% route)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'baudClk'
Clock period: 1.346ns (frequency: 742.942MHz)
Total number of paths / destination ports: 10 / 10
Clock period: 1.950ns (frequency: 512.821MHz)
Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Delay: 1.346ns (Levels of Logic = 0)
Source: current_s_FSM_FFd1 (FF)
Destination: current_s_FSM_FFd10 (FF)
Delay: 1.950ns (Levels of Logic = 0)
Source: current_s_FSM_FFd10 (FF)
Destination: current_s_FSM_FFd9 (FF)
Source Clock: baudClk rising
Destination Clock: baudClk rising
 
Data Path: current_s_FSM_FFd1 to current_s_FSM_FFd10
Data Path: current_s_FSM_FFd10 to current_s_FSM_FFd9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 0.591 0.447 current_s_FSM_FFd1 (current_s_FSM_FFd1)
FDP:D 0.308 current_s_FSM_FFd10
FDP:C->Q 17 0.591 1.051 current_s_FSM_FFd10 (current_s_FSM_FFd10)
FDC:D 0.308 current_s_FSM_FFd9
----------------------------------------
Total 1.346ns (0.899ns logic, 0.447ns route)
(66.8% logic, 33.2% route)
Total 1.950ns (0.899ns logic, 1.051ns route)
(46.1% logic, 53.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'baudOverSampleClk'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 3.338ns (Levels of Logic = 2)
Offset: 3.287ns (Levels of Logic = 2)
Source: serial_in (PAD)
Destination: syncDetected (FF)
Destination Clock: baudOverSampleClk rising
415,170 → 473,59
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 1.108 serial_in_IBUF (serial_in_IBUF)
IBUF:I->O 10 1.218 1.057 serial_in_IBUF (serial_in_IBUF)
LUT2:I0->O 1 0.704 0.000 filterRx_FSM_FFd2-In1 (filterRx_FSM_FFd2-In)
FDC:D 0.308 filterRx_FSM_FFd2
----------------------------------------
Total 3.338ns (2.230ns logic, 1.108ns route)
(66.8% logic, 33.2% route)
Total 3.287ns (2.230ns logic, 1.057ns route)
(67.8% logic, 32.2% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd2'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_7 (LATCH)
Destination Clock: current_s_FSM_FFd2 falling
 
Data Path: serial_in to data_byte_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_7
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd3'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_6 (LATCH)
Destination Clock: current_s_FSM_FFd3 falling
 
Data Path: serial_in to data_byte_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_6
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd4'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_5 (LATCH)
Destination Clock: current_s_FSM_FFd4 falling
 
Data Path: serial_in to data_byte_5
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_5
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd5'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_4 (LATCH)
Destination Clock: current_s_FSM_FFd5 falling
 
Data Path: serial_in to data_byte_4
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_4
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd6'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_3 (LATCH)
Destination Clock: current_s_FSM_FFd6 falling
 
Data Path: serial_in to data_byte_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_3
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd7'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_2 (LATCH)
Destination Clock: current_s_FSM_FFd7 falling
 
Data Path: serial_in to data_byte_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_2
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd8'
Total number of paths / destination ports: 1 / 1
Total number of paths / destination ports: 8 / 7
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Offset: 5.900ns (Levels of Logic = 4)
Source: serial_in (PAD)
Destination: data_byte_1 (LATCH)
Destination Clock: current_s_FSM_FFd8 falling
Destination: Mtridata_byteReceived<6> (LATCH)
Destination Clock: current_s_FSM_FFd8 rising
 
Data Path: serial_in to data_byte_1
Data Path: serial_in to Mtridata_byteReceived<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_1
IBUF:I->O 10 1.218 1.057 serial_in_IBUF (serial_in_IBUF)
LUT3:I0->O 3 0.704 0.610 Mtridata_byteReceived<6>_mux000021 (N8)
LUT3:I1->O 1 0.704 0.595 Mtridata_byteReceived<6>_mux0000_SW0 (N17)
LUT4:I0->O 1 0.704 0.000 Mtridata_byteReceived<6>_mux0000 (Mtridata_byteReceived<6>_mux0000)
LDE:D 0.308 Mtridata_byteReceived<6>
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
Total 5.900ns (3.638ns logic, 2.262ns route)
(61.7% logic, 38.3% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'current_s_FSM_FFd9'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.459ns (Levels of Logic = 1)
Offset: 2.408ns (Levels of Logic = 1)
Source: serial_in (PAD)
Destination: data_byte_0 (LATCH)
Destination: Mtridata_byteReceived<0> (LATCH)
Destination Clock: current_s_FSM_FFd9 falling
 
Data Path: serial_in to data_byte_0
Data Path: serial_in to Mtridata_byteReceived<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.218 0.933 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 data_byte_0
IBUF:I->O 10 1.218 0.882 serial_in_IBUF (serial_in_IBUF)
LD:D 0.308 Mtridata_byteReceived<0>
----------------------------------------
Total 2.459ns (1.526ns logic, 0.933ns route)
(62.1% logic, 37.9% route)
Total 2.408ns (1.526ns logic, 0.882ns route)
(63.4% logic, 36.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'baudClk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.310ns (Levels of Logic = 1)
Offset: 4.745ns (Levels of Logic = 1)
Source: current_s_FSM_FFd1 (FF)
Destination: data_ready (PAD)
Source Clock: baudClk rising
587,20 → 534,20
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 0.591 0.447 current_s_FSM_FFd1 (current_s_FSM_FFd1)
FDCE:C->Q 10 0.591 0.882 current_s_FSM_FFd1 (current_s_FSM_FFd1)
OBUF:I->O 3.272 data_ready_OBUF (data_ready)
----------------------------------------
Total 4.310ns (3.863ns logic, 0.447ns route)
(89.6% logic, 10.4% route)
Total 4.745ns (3.863ns logic, 0.882ns route)
(81.4% logic, 18.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd2'
Total number of paths / destination ports: 1 / 1
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd1'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_7 (LATCH)
Destination: data_byte<7> (PAD)
Source Clock: current_s_FSM_FFd2 falling
Source Clock: current_s_FSM_FFd1 falling
 
Data Path: data_byte_7 to data_byte<7>
Gate Net
613,149 → 560,16
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd3'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_6 (LATCH)
Destination: data_byte<6> (PAD)
Source Clock: current_s_FSM_FFd3 falling
 
Data Path: data_byte_6 to data_byte<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_6 (data_byte_6)
OBUF:I->O 3.272 data_byte_6_OBUF (data_byte<6>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd4'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_5 (LATCH)
Destination: data_byte<5> (PAD)
Source Clock: current_s_FSM_FFd4 falling
 
Data Path: data_byte_5 to data_byte<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_5 (data_byte_5)
OBUF:I->O 3.272 data_byte_5_OBUF (data_byte<5>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd5'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_4 (LATCH)
Destination: data_byte<4> (PAD)
Source Clock: current_s_FSM_FFd5 falling
 
Data Path: data_byte_4 to data_byte<4>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_4 (data_byte_4)
OBUF:I->O 3.272 data_byte_4_OBUF (data_byte<4>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd6'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_3 (LATCH)
Destination: data_byte<3> (PAD)
Source Clock: current_s_FSM_FFd6 falling
 
Data Path: data_byte_3 to data_byte<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_3 (data_byte_3)
OBUF:I->O 3.272 data_byte_3_OBUF (data_byte<3>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd7'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_2 (LATCH)
Destination: data_byte<2> (PAD)
Source Clock: current_s_FSM_FFd7 falling
 
Data Path: data_byte_2 to data_byte<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_2 (data_byte_2)
OBUF:I->O 3.272 data_byte_2_OBUF (data_byte<2>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd8'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_1 (LATCH)
Destination: data_byte<1> (PAD)
Source Clock: current_s_FSM_FFd8 falling
 
Data Path: data_byte_1 to data_byte<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_1 (data_byte_1)
OBUF:I->O 3.272 data_byte_1_OBUF (data_byte<1>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'current_s_FSM_FFd9'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.368ns (Levels of Logic = 1)
Source: data_byte_0 (LATCH)
Destination: data_byte<0> (PAD)
Source Clock: current_s_FSM_FFd9 falling
 
Data Path: data_byte_0 to data_byte<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD:G->Q 1 0.676 0.420 data_byte_0 (data_byte_0)
OBUF:I->O 3.272 data_byte_0_OBUF (data_byte<0>)
----------------------------------------
Total 4.368ns (3.948ns logic, 0.420ns route)
(90.4% logic, 9.6% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.17 secs
Total CPU time to Xst completion: 3.32 secs
-->
 
Total memory usage is 257012 kilobytes
Total memory usage is 258164 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 9 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
Number of warnings : 19 ( 0 filtered)
Number of infos : 9 ( 0 filtered)
 
/iseProject/isim.log
17,31 → 17,3
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
/iseProject/serial_receiver_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/21/2012 - 12:13:10)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/21/2012 - 14:22:41)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>iseProject.xise</TD>
25,7 → 25,7
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='E:/uart_block/hdl/iseProject\_xmsgs/*.xmsgs?&DataKey=Warning'>9 Warnings (8 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='E:/uart_block/hdl/iseProject\_xmsgs/*.xmsgs?&DataKey=Warning'>19 Warnings (18 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
58,17 → 58,17
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slices</TD>
<TD ALIGN=RIGHT>7</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>4656</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Flip Flops</TD>
<TD ALIGN=RIGHT>13</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>9312</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>37</TD>
<TD ALIGN=RIGHT>9312</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
94,7 → 94,7
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
 
 
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
105,9 → 105,9
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
 
 
</TABLE>
 
 
<br><center><b>Date Generated:</b> 04/21/2012 - 12:42:35</center>
<br><center><b>Date Generated:</b> 04/21/2012 - 14:22:41</center>
</BODY></HTML>
/iseProject/serial_receiver.vhd
23,7 → 23,7
 
begin
-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC
process (rst, baudOverSampleClk, serial_in)
process (rst, baudOverSampleClk, serial_in, current_s)
begin
if rst = '1' then
filterRx <= s0;
48,16 → 48,26
filterRx <= s0;
end if;
when s2 =>
when s2 =>
syncDetected <= '0';
if serial_in = '0' then
filterRx <= s3;
syncDetected <= '0';
else
filterRx <= s0;
end if;
when s3 =>
-- Real Beginning of start bit detected
if serial_in = '0' then
filterRx <= s2;
syncDetected <= '1';
else
-- Start bit end detected
--filterRx <= s2;
--syncDetected <= '1';
filterRx <= s3;
syncDetected <= '1';
end if;
-- Reset out sync detector when finished to receive a byte
if current_s = rx_stop then
filterRx <= s0;
end if;
end case;
end if;
end process;
74,58 → 84,60
-- Process to handle the serial receive
process (current_s)
variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0);
begin
case current_s is
when rx_idle =>
data_ready <= '0';
--data_byte <= (others => 'Z');
byteReceived := (others => 'Z');
next_s <= bit0;
when bit0 =>
data_ready <= '0';
data_byte(0) <= serial_in;
byteReceived(0) := serial_in;
next_s <= bit1;
when bit1 =>
data_ready <= '0';
data_byte(1) <= serial_in;
byteReceived(1) := serial_in;
next_s <= bit2;
when bit2 =>
data_ready <= '0';
data_byte(2) <= serial_in;
byteReceived(2) := serial_in;
next_s <= bit3;
when bit3 =>
data_ready <= '0';
data_byte(3) <= serial_in;
byteReceived(3) := serial_in;
next_s <= bit4;
when bit4 =>
data_ready <= '0';
data_byte(4) <= serial_in;
byteReceived(4) := serial_in;
next_s <= bit5;
when bit5 =>
data_ready <= '0';
data_byte(5) <= serial_in;
byteReceived(5) := serial_in;
next_s <= bit6;
when bit6 =>
data_ready <= '0';
data_byte(6) <= serial_in;
byteReceived(6) := serial_in;
next_s <= bit7;
when bit7 =>
data_ready <= '0';
data_byte(7) <= serial_in;
byteReceived(7) := serial_in;
next_s <= rx_stop;
when rx_stop =>
data_ready <= '1';
next_s <= rx_idle;
data_ready <= '1';
data_byte <= byteReceived;
next_s <= rx_stop;
end case;
end case;
end process;
 
end Behavioral;
/iseProject/testSerial_receiver.vhd
101,7 → 101,7
-- Stop bit here
serial_in <= '1';
wait for baudClk_period * 3;
wait for baudClk_period * 1;
-- Receive 0x55 value (01010101)
-- Start bit here
127,7 → 127,7
-- Stop bit here
serial_in <= '1';
wait for baudClk_period * 3;
wait for baudClk_period * 1;
 
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
/iseProject/serial_receiver_xst.xrpt
5,7 → 5,7
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
 
<application stringID="Xst" timeStamp="Sat Apr 21 12:13:05 2012">
<application stringID="Xst" timeStamp="Sat Apr 21 14:22:37 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
113,6 → 113,9
<item dataType="int" stringID="XST_REGISTERS" value="1">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="1"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="8">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="8"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_FSMS" value="2"/>
142,13 → 145,17
<item stringID="XST_IOS" value="13"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="4">
<item dataType="int" stringID="XST_INV" value="1"/>
<item dataType="int" stringID="XST_LUT2" value="2"/>
<item dataType="int" stringID="XST_LUT3" value="1"/>
<item dataType="int" stringID="XST_BELS" value="39">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="3"/>
<item dataType="int" stringID="XST_LUT2" value="12"/>
<item dataType="int" stringID="XST_LUT3" value="8"/>
<item dataType="int" stringID="XST_LUT4" value="14"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="21">
<item dataType="int" stringID="XST_FDC" value="12"/>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="37">
<item dataType="int" stringID="XST_FDC" value="11"/>
<item dataType="int" stringID="XST_FDCE" value="1"/>
<item dataType="int" stringID="XST_FDP" value="1"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
162,9 → 169,9
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s500efg320-4"/>
<item AVAILABLE="4656" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="7"/>
<item AVAILABLE="9312" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="13"/>
<item AVAILABLE="9312" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="4"/>
<item AVAILABLE="4656" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="20"/>
<item AVAILABLE="9312" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="29"/>
<item AVAILABLE="9312" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="37"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="13"/>
<item AVAILABLE="232" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="13"/>
<item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="2"/>
174,8 → 181,8
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="9"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="1"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="19"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="9"/>
</section>
</application>
 
/iseProject/iseProject.gise
65,7 → 65,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335004127" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335004126">
<transform xil_pn:end_ts="1335010966" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335010966">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
86,7 → 86,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335004127" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335004127">
<transform xil_pn:end_ts="1335010966" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335010966">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
95,7 → 95,7
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
</transform>
<transform xil_pn:end_ts="1335004129" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1335004127">
<transform xil_pn:end_ts="1335010969" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1335010966">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
105,7 → 105,7
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335004129" xil_pn:in_ck="-2369381387331258610" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7589868709935752726" xil_pn:start_ts="1335004129">
<transform xil_pn:end_ts="1335010969" xil_pn:in_ck="-2369381387331258610" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7589868709935752726" xil_pn:start_ts="1335010969">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
116,31 → 116,31
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335001321" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8234491708054964473" xil_pn:start_ts="1335001321">
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8234491708054964473" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335001321" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3554467849218202431" xil_pn:start_ts="1335001321">
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3554467849218202431" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335001321" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335001321">
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335001321" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5735937742822206345" xil_pn:start_ts="1335001321">
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5735937742822206345" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335001321" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335001321">
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335001321" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-56991442930515319" xil_pn:start_ts="1335001321">
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-56991442930515319" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335003190" xil_pn:in_ck="-797052197999818498" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1927650389291255036" xil_pn:start_ts="1335003184">
<transform xil_pn:end_ts="1335010961" xil_pn:in_ck="-797052197999818498" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1927650389291255036" xil_pn:start_ts="1335010956">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
/iseProject/pkgDefinitions.vhd
7,7 → 7,8
--! Wishbone slave \n
--! Calculate baudrate based on clock speed \n\n
--! Interesting links \n
--! http://opencores.org/ \n
--! http://opencores.org/ \n
--! http://www.erg.abdn.ac.uk/~gorry/course/phy-pages/async.html \n
 
--! Use standard library
 
21,7 → 22,7
 
type txStates is (tx_idle, tx_start, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, tx_stop1, tx_stop2);
type rxStates is (rx_idle, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, rx_stop);
type rxFilterStates is (s0, s1, s2);
type rxFilterStates is (s0, s1, s2, s3);
 
end pkgDefinitions;
 
/iseProject/iseconfig/serial_receiver.xreport
1,9 → 1,9
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-04-21T11:42:00</DateModified>
<DateModified>2012-04-21T14:19:58</DateModified>
<ModuleName>serial_receiver</ModuleName>
<SummaryTimeStamp>2012-04-21T11:41:51</SummaryTimeStamp>
<SummaryTimeStamp>2012-04-21T12:13:10</SummaryTimeStamp>
<SavedFilePath>E:/uart_block/hdl/iseProject/iseconfig/serial_receiver.xreport</SavedFilePath>
<ImplementationReportsDirectory>E:/uart_block/hdl/iseProject</ImplementationReportsDirectory>
<DateInitialized>2012-04-21T11:41:59</DateInitialized>
/iseProject/serial_receiver.ngc
1,3 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$7;x5>6638;04<948;MVPUSS2mkmRlvtd>4>5823K_MK]64BTQ\MK@H92I87NB]9:ALIHOS\LN<7N\JAUGG5>B53O>87KJL3:DGT4=@92C97D>=;H31?L433@H^J45FNHVPPDRB;2CEZ>5FOC08HA1<DFMBOLB;;MWW61=K]]9<7CK[WNPH5>I?3F$3;ujPL59LFP@33YKYXl5_IO]AQVOCPk1[ECQMURLBI@5<X[O:7\84SNWQG@2<\PZNo6[\ES]UMVOEDL30ZDKX_U[SA4b<P@FBBU#WDC"3*4&T\\H+<#?/ARAJM3=_[]FBN;5Wdc]J`46<PmgTAld`rWgqwlii991Sh`QBiomqR`ttafd87U}{7:`bqaEkcm1imxjLlj]AQCAW981imxj@vdpPehvkmJf`=:5matfLr`tTidzgiNbd_CWECU7f3jy~h`{_r]EWHYFkz~TJ^CPiot15>erz{oexR}PFRO\EfusWOYFSd`y1^KMRZ66:2i~~kat^q\BVKXNOn:=>5luspfjqYtWOYFSKHk1131?fsuzldS~QISL]EBa46:2i~~kat^q\BVKXNOn8=?5luspfjqYtWOYFSKHk4008gptumg~TRH\M^DE`0753jy~h`{_r]EWHYANm<:>6mzrsgmpZuXNZGTJKj8139`qwtbf}UxSK]B_GDg<44<k|xyiczPs^DPIZ@Al0i0hlzn_c{wa969k2njxlQmyug?5;e<lh~jSow{e=0=g>bf|hUiuyk33?a8`drfWksi1:1c:fbpdYeq}o793m4d`vb[gsm5<5i6jnt`]a}qc;?3:5o6jnt`]a}qc;?7h0hlzn_c{waZ6682njxlQmyug\4ZIE]Oh0hlzn_c{waZ7682njxlQmyug\5ZIE]Oh0hlzn_c{waZ4682njxlQmyug\6ZIE]Oh0hlzn_c{waZ5682njxlQmyug\7ZIE]Oh0hlzn_c{waZ2682njxlQmyug\0ZIE]Oh0hlzn_c{waZ3682njxlQmyug\1ZIE]Oh0hlzn_c{waZ0682njxlQmyug\2ZIE]Oh0hlzn_c{waZ1682njxlQmyug\3ZIE]Ok0hlzn_sgb`|`<lh~jSkndx]LFP@692lb`yk}Ry]EWHYANm;:86hflugqV}YA[DUMJi?"Io36?cok|lxYtRH\M^DE`4+Nf8;:7kgctdpQ|Z@TEVLMh??;;gkop`tUpVLXARHId3/Jj43<n`fi\w_GQN[C@c:$Ce=>5}su:8vvrXAK_M56}jrhco[lhb3zoyelbPio]JFP@a3zoyelbPrdafmscuk2yrbnJjtdawaa733zseoIk{ebvf`Zkrp9:;=<;4sxl`@`rbk}ooS`{w012251=sz|o:<6vl3r734`+3%om8>=sO@q335>FGp?91J7<51zQ:>7b=9m0:?>><6482<gdfsg8i6<5a2b85?!4f2;20q^652e82`?74;99=97?7bca8`35=83;1=v]6:3f95a<6;::8:84>8c`b?sR5<3:1=7?52`yP=?4c28n1=>=?37795=dei2.9;7?7;%3e>3><j?91<7j52781e~N5>2.9978<;[795~5=u`8n6=44i4d94?=h=>0;66g91;29?l572900c9850;&15?223g8;6=54o5694?"593>>7c<?:098k15=83.9=7::;o03>7=<g=81<7*=1;66?k472:10c9?50;&15?223g8;6954o5294?"593>>7c<?:498k6`=83.9=7::;o03>3=<g:o1<7*=1;66?k472>10n;:50;694?6|,;?1o6F=9:J12>o12900e:4?::kb>5<<g;91<75rb4794?5=83:p(?;5169K6<=O:?1/=;497:kb>5<<al0;66a=3;29?xd2;3:1?7>50z&11?703A827E<9;%35>31<ah0;66gj:188k75=831vn8?50;194?6|,;?1=:5G289K63=#9?0=;6gn:188m`<722e9?7>5;|`7b?6=;3:1<v*=5;34?M4>3A8=7)?9:758md<722cn6=44o3194?=zj=n1<7=50;2x 73=9>1C>45G279'53<1?2cj6=44id83>>i5;3:17pl;b;297?6=8r.997?8;I0:?M413-;=6;94i`83>>ob2900c?=50;9~f1?=8391<7>t$37952=O:01C>;5+17853>of2900eh4?::m17?6=3th?;7>53;294~"5=3;<7E<6;I05?!712?=0el4?::kf>5<<g;91<75rb4;94?2=83:p(?;5c:J1=>N5>2.:87>4i783>>o02900el4?::m17?6=3th>o7>54;294~"5=3i0D?74H348 42=82c=6=44i683>>of2900c?=50;9~f63=83>1<7>t$379`>N512B9:6*>4;38m3<722cj6=44i3094?=h::0;66sm3e83>1<729q/>84l;I0:?M413-;?6=5f6;29?l1=831bm7>5;n00>5<<uk9h6=4;:183!422j1C>45G279'51<73`<1<75f7;29?lg=831d>>4?::a7g<72=0;6=u+248`?M4>3A8=7)?;:19j2?6=3`=1<75fa;29?j442900qo=n:187>5<7s-8>6n5G289K63=#9=0;7d850;9j3?6=3`k1<75`2283>>{e;00;694?:1y'60<d3A827E<9;%37>5=n>3:17d950;9je?6=3f886=44}c1;>5<3290;w)<::b9K6<=O:?1/=94?;h494?=n?3:17do50;9l66<722wi?:4?:583>5}#:<0h7E<6;I05?!73291b:7>5;h594?=ni3:17b<<:188yg51290?6=4?{%06>f=O:01C>;5+1583?l0=831b;7>5;hc94?=h::0;66sm3583>1<729q/>84l;I0:?M413-;?6=5f6;29?l1=831bm7>5;n00>5<<uk<=6=4<:183!422830D?74H348 42=:2c:<7>5;h32>5<<g8i1<75rb4g94?5=83:p(?;5189K6<=O:?1/=94n;h33>5<<a8;1<75`1b83>>{e=k0;694?:1y'60<6i2B956F=6:&20?d<a8:1<75f1083>>o6:3:17b?l:188yg0729096=4?{%06>45<@;30D?84ig83>>i6k3:17pl92;296?6=8r.997?<;I0:?M413`l1<75`1b83>>{e=10;6?4?:1y'60<6m2B956F=6:ke>5<<g8i1<75rb4494?4=83:p(?;51d9K6<=O:?1bj7>5;n3`>5<<uk??6=4=:183!4228o0D?74H348mc<722e:o7>5;|`66?6=:3:1<v*=5;3f?M4>3A8=7dh50;9l5f<722wi9=4?:383>5}#:<0:i6F=9:J12>oa2900c<m50;9~f1c=8381<7>t$3795`=O:01C>;5ff;29?j7d2900qo:l:181>5<7s-8>6<k4H3;8L70<ao0;66a>c;29?xd3i3:1>7>50z&11?7b3A827E<9;hd94?=h9j0;66sm4983>7<729q/>84>e:J1=>N5>2cm6=44o0a94?=zj;l1<7<50;2x 73=<2B956F=6:ke>5<<g8i1<75rb2394?4=83:p(?;54:J1=>N5>2cm6=44o0a94?=zj:91<7<50;2x 73=9<1C>45G279jb?6=3f;h6=44}r0f>5<5sW8n70<i:g9~w7`=83hp1>;56:?0`?0<5:i1:63<b;4896g=>2785784=2:92>;4?3<01>856:?00?0<5;l1=n5rs2294?4|V::01>?5f:p74<72=q6:949;<7:>3=:=j0=70=>:0a8yv55290iw0=::308962=?278:794=2593>;403=01>757:?0e?1<5:h1;63<c;5896b=?278?7?l;|q00?6=;r7897o4=26966=:=10m7p}<5;296~;4=38870=k:`9~w60=839p18;5e:?02?44349?6l5rs2594?5|5<91i63<7;00?8512h1v>650;1x907=m27847<<;<14>d=z{:31<7=t=5d9a>;4138870=7:`9~w6g=839p19j5e:?0e?4434926l5rs2`94?5|5=h1i63<b;00?85f2h1v>m50;1x91?=m278o7<<;<1a>d=z{:n1<7=t=559a>;4l38870=l:`9~w6c=838pR>k4=5:95f=z{:l1<7<t^2d891g=9j1v9>50;0xZ16<5=i1=n5rs5394?4|V=;019k51b9~w14=838pR9<4=4295f=z{=91<7<t^518904=9j1v9:50;0xZ12<5<>1=n5rs5494?4|V=<018851b9~w11=838p1995229>0=<a3ty?57>52z?7=?4434>j6k5rs5`94?4|5=h1>>524b8e?xu3l3:1>v3;d;00?82b2o1v9h50;0x91`=::169=4i;|q65?6=:r7>=7<<;<71>c=z{<91<7<t=41966=:==0m7p}:5;296~;2=38870;9:g9~w01=838pR894=4:95f=z{<31<7:t=4;966=:=l0:=63:b;31?80128;0q~;n:18183>2h169o4>c:p1f<72;q69n4=3:?6f?763ty>h7>52z?6g?g<5<o1=n5rs4d94?4|V<l01;>5f:p25<72=q6:948;<7:>2=:=j0<708?:0a8yv062909wS8>;<41>c=z{?81<7mt=479e>;2;3k018?5a:?7b?g<5=n1m63;b;c891?=i27?;7o4=4g955=:=k0:<6392;3`?80128:0q~8;:1818032;901>=5f:p20<72;q6:94n;<45>4e<utdjh7>51zJ12>{iil0;6<uG279~jd`=83;pD?84}o`3>5<6sA8=7p`m1;295~N5>2wen?4?:0yK63=zfk91<7?tH348ykd3290:wE<9;|la1?6=9rB9:6sab783>4}O:?1vbo950;3xL70<ugh36=4>{I05?xhe13:1=vF=6:mfd<728qC>;5rnc`94?7|@;<0qcll:182M413tdih7>51zJ12>{ijl0;6<uG279~jg`=83;pD?84}oa3>5<6sA8=7p`l1;295~N5>2weo?4?:0yK63=zfj91<7?tH348yke3290:wE<9;|l`1?6=9rB9:6sac783>4}O:?1vbn950;3xL70<ugi36=4>{I05?xhd13:1=vF=6:mgd<728qC>;5rnb`94?7|@;<0qcml:182M413tdhh7>51zJ12>{ikl0;6<uG279~jf`=83;pD?84}of3>5<6sA8=7p`k1;295~N5>2weh?4?:0yK63=zfm91<7?tH348ykb3290:wE<9;|lg1?6=9rB9:6sad783>4}O:?1vqpsO@By244<0kmk>9=6r@A@x4xFGXrwKL
$e0x5>65398?7=J?00920>52;9;<754@UURVP?bf|hUiuyk37;2=0>GFIK80N5;4BTDDT==E]ZUBBKA>;B08G@5<KEX27NABMHVWAA1<K[OJXHJ>;E38A7=B<=1NJN>;;G1707=A<;1MN95IB1:0?CBD<2LOOH=4FER1?CC33OL;>95IF327?C@EI=1MJHH>;F08C@5<OGN:7D<4I108M44<A;80E>:4ICWE=>OIA]Y_MYK<;HLU7>OHJ;1GH>5CDD58HJANKHF?7A[[259OQQ533E__8<64Mupj`drfWksi_klehtf`969911Fxgkauc\f|rbZline{kk<0<14>Ksz`njxlQmyugQafcn~ln7=3Qaou2344403D~yeio{a^`zp`Tbklc}ii2>>^llp56798UBB[Q?199Npwoci}kTntzjRdafmscc4;49<6C{rhfbpdYeq}oYinkfvdf?6;Yj}q:;<=<>;LvqmagsiVhrxh\jcdkuaa:56Vg~t=>?0003?HruamkmRlvtdPfg`oqmm692R``t123571<E}xbhlzn_c{waWcdm`|nh1<1_omw45669VCEZR>>8:Owvlbf|hUiuyk]ebgjr`b;;78;7@z}iecweZd~|lXnohgyee>0:Zkrp9:;<??4Mupj`drfWksi_klehtf`959Wds<=>?10:8Iqtnlh~jSow{eSg`alpbl5>5>=5BtskgeqgXjp~n^hmjiwgg818Xe|r;<=>=4:Owvlbf|hUiuyk]ebgjr`b;<7Ufyu>?01]PS57?3D~yeio{a^`zp`Tbklc}ii2:>328Iqtnlh~jSow{eSg`alpbl5?5S`{w01235==J|{comyoPbxvfV`ebaoo0;0=0:Owvlbf|hUiuyk]ebgjr`b;>7Ufyu>?0101?HruamkmRlvtdPfg`oqmm6=2Rczx1234775<2G~djnt`]a}qcUmjobzhj36?]nq}6789UX[=<;;LvqmagsiVhrxh\jcdkuaa:16Vg~t=>?0^QT54><E}xbhlzn_c{waWcdm`|nh191219Npwoci}kTntzjRdafmscc4>4Taxv?01215>Ksz`njxlQmyugQafcn~ln7;3Qbuy234575:2G~djnt`]a}qcUmjobzhj37?]nq}6789;:>>5BtskgeqgXjp~n^hmjiwgg828Xe|r;<=>>2035?HrualdTntzjRdafmscc494:i6C{rhgm[gsm[ohidxjd=2=[kis89::=k5BtskfjZd~|lXnohgyee>3:Zhh|9:;=<?9;Lvqm`hXjp~n^hmjiwgg8486m2G~dka_c{waWcdm`|nh1?1_omw45669o1Fxgjn^`zp`Tbklc}ii2>>^llp56798;=7@z}idl\f|rbZline{kk<3<2a>Ksz`oeSow{eSg`alpbl585Sca{01225c=J|{cnbRlvtdPfg`oqmm692R``t12354473D~yeh`PbxvfV`ebaoo0?0Pnnv3457698<0Ay|feo]a}qcUmjobzhj33?3f?HrualdTntzjRdafmscc4:4Tbbz?0132b>Ksz`oeSow{eSg`alpbl595Sca{0122540<E}xbicQmyugQafcn~ln783?j;Lvqm`hXjp~n^hmjiwgg818Xff~;<=?=2:OwvlciWksi_klehtf`929Wge<=>>_RU353=J|{cnbRlvtdPfg`oqmm6>2<k4MupjakYeq}oYinkfvdf?1;Yig}:;<<?i;Lvqm`hXjp~n^hmjiwgg808Xff~;<=?>179NpwobfVhrxh\jcdkuaa:168o0Ay|feo]a}qcUmjobzhj36?]mkq6788897@z}idl\f|rbZline{kk<7<\jjr789;T_Z>>6:OwvlciWksi_klehtf`9199l1Fxgjn^`zp`Tbklc}ii28>^llp56798l0Ay|feo]a}qcUmjobzhj37?]mkq6788;97C><;O226>H6;2D:<>5A1018J4543G;>?6@>729M5=4<F>80B594NDVTKWM63F20C#68xe]O0>IE]O;0\95_ASVb?UOIWK_XEIVm;QKM[GSTFHGN?6^]E09R2>UH][IN86ZVPDa8QVCUW_CXEOBJ3:T@G<=QAL]TXT^J1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF6:ZPPIOE?2RXXRIAD69[WQYQKJ<0TilPIe33?]bjWDkacXjrrklj46<PmgTAd``rWgqwlii;2Rxx:5matf@hnb<jhoOaePBTDDT47<jhoC{k}S`osh`Ekc8=0nl{kOwgqWdkwdlIggRLZFFRe?gsm[ohidxjd=2=5<=eq}oYinkfvdf?4;Jho`i_~~z>f:`zp`Tbklc}ii2>>0;8f|rbZline{kk<0<Okbod\{y=k5myugQafcn~ln7>3?6;c{waWcdm`|nh1<1LnejgQtt|8l0ntzjRdafmscc4:4:56lvtdPfg`oqmm682AahibVqwq7a3ksi_klehtf`929901iuyk]ebgjr`b;<7Fdkdm[rrv2b>d~|lXnohgyee>6:4?<jp~n^hmjiwgg808KgnchX}{1g9a}qcUmjobzhj36?3:?gsm[ohidxjd=4=Hjank]xxx<h4bxvfV`ebaoo0:0>9:`zp`Tbklc}ii28>MmdmfRu{};:m6mzrsgmpZuXNZGTMn}{_GQN[lhq:81hy|jnu]p[CUJWHixxRH\M^kmr4YNF_U;=?5luspfjqYtWOYFSKHk1018gptumg~TRH\M^DE`466:2i~~kat^q\BVKXNOn9=?5luspfjqYtWOYFSKHk3008gptumg~TRH\M^DE`1753jy~h`{_r]EWHYANm?:>6mzrsgmpZuXNZGTJKj9139`qwtbf}UxSK]B_GDg344<k|xyiczPs^DPIZ@Al1;97n{}rdlw[vYA[DUMJi7l;ecweZd~|l6;2n5kauc\f|rb484h7io{a^`zp`:56j1omyoPbxvf868d3mkmRlvtd>7:f=ci}kTntzj<4<`?agsiVhrxh29>d9geqgXjp~n0:4?>b9geqgXjp~n0:0m;ecweZd~|lU;==5kauc\f|rbW9UDNXHm;ecweZd~|lU:==5kauc\f|rbW8UDNXHm;ecweZd~|lU9==5kauc\f|rbW;UDNXHm;ecweZd~|lU8==5kauc\f|rbW:UDNXHm;ecweZd~|lU?==5kauc\f|rbW=UDNXHm;ecweZd~|lU>==5kauc\f|rbW<UDNXHm;ecweZd~|lU===5kauc\f|rbW?UDNXHm;ecweZd~|lU<==5kauc\f|rbW>UDNXHn;ecweZtbimsm7io{a^pfeaXGK_M=<5iimvfvW~XNZGTJKj>159emirbz[rTJ^CPFGf2)Lh6=2lb`yk}Ry]EWHYANm;&Ec?>1:djhqcuZqUM_@QIFe020>`nd}oy^uQISL]EBa4*Ag;>7kgctdpQ|Z@TEVLMh?#Fn018vvr?3{ySDLZF89pawofdVcei6}jrhco[lhXAK_Mj6}jrhco[wcdm`|n~n5|yoaGaqcd|ln:86}vnbFfp`esmmUfyu>?0136?vikMoinzjd^ov|56788>0x{j119{g6u289o&8 hh332~DEv5=11KLuml:G81>4}Tm32=6:<51213733=9mn<iv`74;38j=3=>2.3?79i;|Qg>=0=?;0:?>><6482`a>73mih6=4>:0yPa?>12>81=>=?37795ab0m2|_;l4?:082>0b|[l03:79=:010460228no;h5+7d81`>"0=3n:7oml:18g>0?==mqC;n5+7c8`g>\>28q>6pg77;29?le?2900cn>50;9jgd<722c357>5;nce>5<#?>0ji6`86;28?jgc290/;:4ne:l42?7<3fkh6=4+768ba>h0>3807bom:18'32<fm2d<:7=4;ncb>5<#?>0ji6`86;68?jg>290/;:4ne:l42?3<3fk36=4+768ba>h0>3<07bo8:18'32<fm2d<:794;c:2>5<6290;w)9m:338L=6<@>i0c<h50;9~f=4=83;1<7>t$6`93a=O091C;n5`7583>>{ekm0;694?:1y'3g<6?2B3<6F8c:kb>5<<aj0;66gi:188k2?=831vn9950;694?6|,>h1>n5G819K3f=nn3:17d?i:188m76=831d;44?::a07<72=0;6=u+7c81g>N?82B<o6gi:188m4`=831b>=4?::m4=?6=3th?<7>54;294~"0j38h7E6?;I5`?l`=831b=k4?::k14?6=3f=26=44}c1g>5<3290;w)9m:3a8L=6<@>i0ek4?::k2b?6=3`8;6=44o6;94?=zj:k1<7:50;2x 2d=:j1C4=5G7b9jb?6=3`;m6=44i3294?=h?00;66sm3483>1<729q/;o4=c:J;4>N0k2cm6=44i0d94?=n:90;66a89;29?xd4:3:187>50z&4f?4d3A2;7E9l;hd94?=n9o0;66g=0;29?j1>2900qo8=:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo;i:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo;l:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo;6:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo;9:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo;=:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo:i:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo:l:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qo=>:180>5<7s-=i6?l4H928L2e<ao0;66g>f;29?j1>2900qom=:187>5<7s-=i6<94H928L2e<,;21<6gn:188mf<722cm6=44o6;94?=zjj?1<7:50;2x 2d=9>1C4=5G7b9'6=<73`k1<75fc;29?l`=831d;44?::a=`<72=0;6=u+7c82=>N?82B<o6*=8;18md<722cm6=44i6:94?=h?00;66sma783>1<729q/;o4>7:J;4>N0k2.947>4i`83>>od2900ek4?::m4=?6=3thj97>54;294~"0j3;<7E6?;I5`?!4?291bm7>5;ha94?=nn3:17b96:188ygg3290?6=4?{%5a>41<@1:0D:m4$3:94>of2900en4?::ke>5<<g>31<75rb`194?2=83:p(:l5169K<5=O?j1/>54?;hc94?=nk3:17dh50;9l3<<722wim?4?:583>5}#?k0:;6F70:J4g>"503:0el4?::k`>5<<ao0;66a89;29?xdf93:187>50z&4f?703A2;7E9l;%0;>5=ni3:17dm50;9jb?6=3f=26=44}cc3>5<3290;w)9m:058L=6<@>i0(?650:kb>5<<aj0;66gi:188k2?=831vn4h50;694?6|,>h1=:5G819K3f=#:10;7do50;9jg?6=3`l1<75`7883>>{ej90;6>4?:1y'3g<5j2B3<6F8c:&1e?b73`l1<75f1g83>>i013:17plm2;297?6=8r.<n7<m;I:3?M1d3-8j6i>4ig83>>o6n3:17b96:188ygd329086=4?{%5a>7d<@1:0D:m4$3c9`5=nn3:17d?i:188k2?=831vno850;194?6|,>h1>o5G819K3f=#:h0o<6gi:188m4`=831d;44?::af=<72:0;6=u+7c81f>N?82B<o6*=a;f3?l`=831b=k4?::m4=?6=3thim7>53;294~"0j38i7E6?;I5`?!4f2m:0ek4?::k2b?6=3f=26=44}c``>5<4290;w)9m:3`8L=6<@>i0(?o5d19jb?6=3`;m6=44o6;94?=zjko1<7=50;2x 2d=:k1C4=5G7b9'6d<c82cm6=44i0d94?=h?00;66sm9`83>6<729q/;o4=e:J;4>N0k2.947??;h00>5<<a;>1<75`7083>>{e110;6>4?:1y'3g<5m2B3<6F8c:&1<?773`886=44i3694?=h?80;66sm9783>6<729q/;o4=e:J;4>N0k2.947??;h00>5<<a;>1<75`7083>>{e1=0;6>4?:1y'3g<5m2B3<6F8c:&1<?773`886=44i3694?=h?80;66sm9383>6<729q/;o4=e:J;4>N0k2.947??;h00>5<<a;>1<75`7083>>{e190;6>4?:1y'3g<5m2B3<6F8c:&1<?773`886=44i3694?=h?80;66sm8d83>6<729q/;o4=e:J;4>N0k2.947??;h00>5<<a;>1<75`7083>>{e0j0;6>4?:1y'3g<5m2B3<6F8c:&1<?773`886=44i3694?=h?80;66sm5483>6<729q/;o4=e:J;4>N0k2.947=4i3194?=n:=0;66a81;29?xd3m3:1?7>50z&4f?4b3A2;7E9l;%0;>46<a;91<75f2583>>i093:17pl:1;290?6=8r.<n7<i;I:3?M1d3-836<:4i3194?=n:=0;66g=5;29?j162900qo:m:187>5<7s-=i6?h4H928L2e<,;21=l5f2283>>o5<3:17d<::188k27=831vn8k50;794?6|,>h1?=5G819K3f=#:10:o6g=3;29?l432900e?;50;9j63<722e<=7>5;|`6<?6==3:1<v*8b;13?M>73A=h7)<7:0a8m75=831b>94?::k11?6=3`8=6=44o6394?=zj=k1<7;50;2x 2d=;91C4=5G7b9'6=<6m2c9?7>5;h07>5<<a;?1<75f2783>>i093:17pl90;291?6=8r.<n7=?;I:3?M1d3-836<l4i3194?=n:=0;66g=5;29?l412900c:?50;9~f0g=83?1<7>t$6`975=O091C;n5+2982f>o5;3:17d<;:188m73=831b>;4?::m45?6=3thh;7>53;294~"0j38n7E6?;I5`?!4?2:1b>>4?::k10?6=3f=:6=44}cae>5<2290;w)9m:228L=6<@>i0(?652:k17?6=3`8?6=44i3794?=n:?0;66a81;29?xdd<3:197>50z&4f?573A2;7E9l;%0;>1=n::0;66g=4;29?l422900e?850;9l34<722wi844?:583>5}#?k09j6F70:J4g>"503;:7d<<:188m72=831b>84?::m45?6=3th8;7>54;294~"0j38m7E6?;I5`?!4?2>1b>>4?::k10?6=3`8>6=44o6394?=zj:i1<7;50;2x 2d=;91C4=5G7b9'6=<6>2c9?7>5;h07>5<<a;?1<75f2783>>i093:17pl;4;290?6=8r.<n7<i;I:3?M1d3-836<5f2283>>o5<3:17d<::188k27=831vn>h50;194?6|,>h1>h5G819K3f=#:10:<6g=3;29?l432900c:?50;9~f6c=83?1<7>t$6`975=O091C;n5+29826>o5;3:17d<;:188m73=831b>;4?::m45?6=3th?97>54;294~"0j38m7E6?;I5`?!4?28?0e?=50;9j61<722c997>5;n52>5<<uk>=6=4::183!1e2::0D5>4H6a8 7>=9m1b>>4?::k10?6=3`8>6=44i3494?=h?80;66sm4283>0<729q/;o4<0:J;4>N0k2.947?<;h00>5<<a;>1<75f2483>>o5>3:17b9>:188yge>29096=4?{%5a>71<@1:0D:m4i3094?=h?80;66smcc83>7<729q/;o4=7:J;4>N0k2c9>7>5;n52>5<<uki:6=4=:183!1e2>90D5>4H6a8m74=831d;<4?::afc<72;0;6=u+7c847>N?82B<o6g=2;29?j162900qolk:181>5<7s-=i6:=4H928L2e<a;81<75`7083>>{ejk0;6?4?:1y'3g<0;2B3<6F8c:k16?6=3f=:6=44}c`:>5<5290;w)9m:618L=6<@>i0e?<50;9l34<722win:4?:383>5}#?k0<?6F70:J4g>o5:3:17b9>:188ygd229096=4?{%5a>25<@1:0D:m4i3094?=h?80;66smb283>7<729q/;o483:J;4>N0k2c9>7>5;n52>5<<ukh:6=4=:183!1e2>90D5>4H6a8m74=831d;<4?::a=a<72<0;6=u+7c82<>N?82B<o6*=8;28md<722ci6=44ib83>>oa2900c:750;9~f32=83?1<7>t$6`975=O091C;n5+2985?l442900e?:50;9j60<722c9:7>5;n52>5<<uk??6=4::183!1e2::0D5>4H6a8 7>=9k1b>>4?::k10?6=3`8>6=44i3494?=h?80;66sm6083>1<729q/;o4=f:J;4>N0k2.947?n;h00>5<<a;>1<75f2483>>i093:17pl:b;290?6=8r.<n7<i;I:3?M1d3-836<o4i3194?=n:=0;66g=5;29?j162900qo:>:186>5<7s-=i6>>4H928L2e<,;21=;5f2283>>o5<3:17d<::188m70=831d;<4?::a<=<72;0;6=u+7c8;?M>73A=h7d<=:188k27=831vn5o50;094?6|,>h146F70:J4g>o5:3:17b9>:188yg?d29096=4?{%5a>7?<@1:0D:m4i3094?=h?80;66sm3883>7<729q/;o4=9:J;4>N0k2c9>7>5;n52>5<<uk9?6=4=:183!1e2;30D5>4H6a8m74=831d;<4?::p74<72;q6?<489:?;g?443ty8>7>52z?06?1>342n6?=4}r10>5<?s4><6?>4=50965=:<909<63<d;03?85f2;:01>;5219>77<58278879>;|q01?6=;r789796;<;3>75<5:=1>85rs2494?4|5:?1j63<7;52?xu403:1;v3;7;3e?82528l019>51g9>7a<6n278m7?i;<16>4`<5:31;<5rs2c94?5|5:k1;45293817>;4k38=7p}<b;296~;4i3l01>m5709~w6b=839p1>j5789>=1<5;278i7<9;|q0a?6=:r78h7h4=2g934=z{=:1<7=t=5293<=:1?09?63;1;05?xu393:1>v3;0;d8917=?81v9<50;1x914=?016554=3:?77?413ty??7>52z?76?`<5=91;<5rs5594?5|5==1;4529`817>;3138>7p};8;296~;3?3l01975709~w1e=838p19m5789><f<5<2wx8i4?:3y>0f<6n27?i79>;|q7b?6=:r7?j796;<:f>72<uz?;6=4={<6e>4`<5<;1;<5rs4094?4|5<81;45291810>{t=:0;6?u25382b>;2<3=:7p}:6;296~;2>3=2707=:368yv302909w0;9:0d890>=?81v8750;0x90?=?016594=4:p1d<72;q6944>f:?6e?163ty>o7>52z?6g?1>343=6?:4}r7g>5<5s4?h6<h4=4g934=z{<l1<7<t=4d93<=:110986s|6183>7}:=o0:j6390;52?xu1:3:1>v392;5:?8?f2;>0q~8<:18180528l01;:5709~w33=838p15?51g9>=`<a3ty=:7>53z?7e?1634>26?=4=76961=z{?=1<7<t=90931=:1m0m7p}98;297~;2=3=:70;j:31890>=:<1v;750;0x936=:<16:<481:p2d<72;q69l4=5:?6f?163ty=n7>52z?0b?16349n6?=4}r4`>5<5s4>>6:?4=51966=z{?n1<7<t=54934=:<:0996s|6d83>3}:<k0<=63:e;07?82f2;901985229>24<5=27?=7<:;|q5b?6=<r7?879>;<1f>72<5=?1>95247811>{t0>0;6?uQ869><=<5:2wx454?:cy>=`<f34k=6l52a48b?8g32h16m>4n;<c1>d=:i80j70o?:`9>=c<f343o6l5289845>{t000;6?uQ889><d<5:2wx4l4?:5y>ga<f34i96l52c48b?8>f2>;0q~6m:1818d72o164n481:p<a<72;q6n?4i;<:f>27<uz2m6=4={<`7>c=:190<=6s|9083>7}:j?0m707=:638yv?42909w0l7:g9>=1<092wx584?:3y>fd<a343=6:?4}r;4>5<5s4hh6k5299845>{t100;6?u2bd8e?8?f2>;0q~7m:18a8?a2j16m=4l;<c2>f=:i;0h70o<:b9>e1<d34k>6n52a78`?8?b2>2014j5c:?:g?163ty2h7>5bz?aa?7a34hh6<h4=cc95c=:j10:j63m6;3e?8d328l01o<51g9>f5<6n27h=7<=;<;g>2?<5j>1>>5rs8g94?75s4<96k525g8e?83d2o16944i;<75>c=:=;0m70:i:g9>0f<a343n6:74=`49b>;3m38870;>:37890c=:?16954=6:?54?4134?j6?84=76966=:==09:6s|9g83>6}:1o0<563;a;06?8?c2k1vl>50;7x9d6=?0165k4i;<6b>72<5?:1>>5242810>{ti80;65u2a084=>;f83l018k5249>0d<5>27=<7<;;<66>73<5=<1>;5240810>{ti;0;6:u2a384=>;f93l019l5229>1d<5;27?97<<;<65>72<5:o1>85rs`194?>|5h91;452a38e?82e2;?01865229>1d<5<27?87<:;<1e>75<5:i1>95rs`694?g|5h>1;452a28e?82e2;>01865259>01<5<278j7<;;<77>75<5<h1>85236810>;4k38>7p}n5;29e~;4:3;m70o::6;89d2=n27>97<;;<72>72<5?>1>;5255811>;1938?70;m:36896?=:;1vl850;`x967=9o16m;489:?b1?`<5<?1>>524d810>;29388708;:378902=:=16:<4=3:?6f?44349?6?<4}rc4>5<5sWk<70l>:638yvg?2909wSo7;<`0>27<uzk26=4={_c:?8d22>;0q~on:181[gf34h<6:?4}rca>5<5sWki70l6:638yvgd2909wSol;<`a>27<uzko6=4={_cg?8dc2>;0q~oi:181[ga34hm6:?4}r`3>5<5s4h;6:74=c3967=z{k81<7<t=c093<=:j:09>6s|b583>7}:j=0<563m5;01?xue>3:1>v3m6;5:?8d02;80q~l7:1818d?2>301o75239~wgg=838p1oo5789>fg<5:2wxnn4?:3y>ff<0127ih7<=;|qaa?6=:r7ii796;<`e>74<uzi;6=4={_a3?8e62>;0q~m=:1878e52>301n95259>g1<5>27hj7<9;|q`7?6=:r7h>7h4=b6934=z{j?1<7=t=b793<=:ko09963l4;06?xud>3:1>v3l5;d89f1=?81vn650;0xZf><5j31>?5rsb;94?2|5jn1o63l2;a89f3=k27h579>;|q`e?6=:rThm63lb;01?xudj3:1nv3<2;d8967=n27h;7<<;<ae>75<5j>1>95248810>;3<38870mm:638961=::16?n4=3:?75?443tyhh7>53z?``?1>343h6?<4=bd961=z{jo1<7<t=bf9b>;dn3=:7psa18g94?7|@>i0qc?6f;295~N0k2we=l>50;3xL2e<ug;j=7>51zJ4g>{i9h81<7?tH6a8yk7f;3:1=vF8c:m5d2=83;pD:m4}o3b1?6=9rB<o6sa1`494?7|@>i0qc?n7;295~N0k2we=l650;3xL2e<ug;j57>51zJ4g>{i9hk1<7?tH6a8yk7fj3:1=vF8c:m5de=83;pD:m4}o3b`?6=9rB<o6sa1`g94?7|@>i0qc?nf;295~N0k2we=o>50;3xL2e<ug;i=7>51zJ4g>{i9k81<7?tH6a8yk7e;3:1=vF8c:m5g2=83;pD:m4}o3a1?6=9rB<o6sa1c494?7|@>i0qc?m7;295~N0k2we=o650;3xL2e<ug;i57>51zJ4g>{i9kk1<7?tH6a8yk7ej3:1=vF8c:m5ge=83;pD:m4}o3a`?6=9rB<o6sa1cg94?7|@>i0qc?mf;295~N0k2we=n>50;3xL2e<ug;h=7>51zJ4g>{i9j81<7?tH6a8yk7d;3:1=vF8c:m5f2=83;pD:m4}o3`1?6=9rB<o6sa1b494?7|@>i0qc?l7;295~N0k2we=n650;3xL2e<ug;h57>51zJ4g>{i9jk1<7?tH6a8yk7dj3:1=vF8c:m5fe=83;pD:m4}o3``?6=9rB<o6sa1bg94?7|@>i0qc?lf;295~N0k2we=i>50;3xL2e<ug;o=7>51zJ4g>{i9m81<7?tH6a8yk7c;3:1=vF8c:m5a2=83;pD:m4}o3g1?6=9rB<o6sa1e494?7|@>i0qc?k7;295~N0k2we=i650;3xL2e<ug;o57>51zJ4g>{i9mk1<7?tH6a8yk7cj3:1=vF8c:m5ae=83;pD:m4}o3g`?6=9rB<o6sa1eg94?7|@>i0qc?kf;295~N0k2we=h>50;3xL2e<ug;n=7>51zJ4g>{i9l81<7?tH6a8yk7b;3:1=vF8c:m5`2=83;pD:m4}o3f1?6=9rB<o6sa1d494?7|@>i0qc?j7;295~N0k2we=h650;3xL2e<ug;n57>51zJ4g>{i9lk1<7?tH6a8yk7bj3:1=vF8c:m5`e=83;pD:m4}o3f`?6=9rB<o6sa1dg94?7|@>i0qc?jf;295~N0k2we=k>50;3xL2e<ug;m=7>51zJ4g>{i9o81<7?tH6a8yk7a;3:1=vF8c:m5c2=83;pD:m4}o3e1?6=9rB<o6sa1g494?7|@>i0qc?i7;295~N0k2we=k650;3xL2e<ug;m57>51zJ4g>{i9ok1<7?tH6a8yx{zHIIp>8659c:1`d??uIJIw=sO@Qy~DE
/iseProject/testSerial_receiver_isim_beh.wdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iseProject/fuse.log
1,4 → 1,4
Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver"
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
17,5 → 17,5
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 29524 KB
Fuse CPU Usage: 264 ms
Fuse Memory Usage: 29488 KB
Fuse CPU Usage: 249 ms
/iseProject/webtalk_pn.xml
3,7 → 3,7
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Apr 21 12:13:05 2012">
<application name="pn" timeStamp="Sat Apr 21 14:22:36 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
19,7 → 19,7
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testSerial_transmitter" type="process"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testSerial_receiver" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
29,17 → 29,18
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testSerial_transmitter" type="process"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testSerial_receiver" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
<property name="PROP_DevDevice" value="xc3s500e" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 us" type="process"/>
<property name="PROP_DevPackage" value="fg320" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="4" type="source"/>
<property name="FILE_VHDL" value="5" type="source"/>
</section>
</application>
</document>
/iseProject/serial_receiver.ngr
1,3 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$97x5>6638n0?~;?0ddd776*<8=047AZTQWW>agsiVhrxh28:1<24>>=lh~jSow{e=594;2<IGN9:6OAD3@2<>Gd{}UM_@m4Abqw[CUJW`d}=h5Ncrv\BVKXag|Te`~PAbqw[CUJW`d}=55MUR]JJCI63J90OA\6;BMNILRSMM=0O_KNTDF0?Fjl?2IggRH\M09G75=B2&j~yQmlnah+mbk'`yn\aeebv,w`tnieUyinkfvdp-rmb43ONH?6HKP59EBa703OLo= Ga8:DE`4+Nf830JKj>-Hl25==ANm;&Ec<m;GDg5(OiW`g{96HId027?C@c:>1MJi<"Io37?C@c:$CeSdc_GDg6(Oi9=1MJi=;;GDg01=ANm??7KHk659EBa133OLo495IFe;0?CUJk2LXAR>"p`pfjqe<NZGT= ~nrdlw5>A33Nki<5F2:K36>O6<2CEEY=4IOT0?Lh7m2ANI]QGIDPBVFN^:2FO;6B@GHABHg=KXDUGMYMG_038K==H&1=shRB<;NP11>IU:K;?7B{{059Lqq733F>95@uu17?Jss<=1Dyy;;;Nww21=H}}=?7B{{859SEWRf3YCESO[\IEZa?UOIWK_XBLCJ3:RQA4=V;2X_@>5]su`8WLAE]ZUBBKAn;RKD[GSTAMRi7^GH_CWPJDKB<2^R\H74VHGT[Q_WM8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENA?1S_YBFB0g8\VRXADZGI@KAT@VJKKYDGGY_^LGATR33?]USW[^GS]\@PDPW]3=_lkUBh<>4Xeo\Idlhz_oydaa119[`hYJageyZh||inl0?]us12RxxJC`ddn4?ggrlJf`=<5matfLr`tTidzgiNbd9:avvwci|Vy:86mzrsgmpZuXkdzTi|>?0137?fsuzldS~Qlmq]fu56798>0ox|}eov\wZejxVoz<=>=159`qwtbf}UxSnc_ds34556<2i~~kat^q\ghvXmx:;<9?;;bwqv`hsWzUha}Qjq123142<k|xyiczPs^antZcv89:==95luspfjqYtWjg{Sh?015`?agsiVhrxh2?>b9geqgXjp~n0<0l;ecweZd~|l692n5kauc\f|rb4:4h7io{a^`zp`:36j1omyoPbxvf808d3mkmRlvtd>5:`=ci}kTntzj<683:f=ci}kTntzj<6<a?agsiVhrxhQ?b:fbpdYeq}oT=o5kauc\f|rbW;h0hlzn_c{waZ5e3mkmRlvtd]7f>bf|hUiuykP5c9geqgXjp~nS;l4d`vb[gsmV=j7io{a^pfea?3ocgxh|]x018bljsm{XsSnc_ds345423ekoe64pnn\cdrb12zd~yQkauc:?uiu|Vmjxh84pnpw[t5<zz~37zc_u{sa<=tm{cj`Rgaf:qfvlgkW{ohidxjrg9pkptdmVlb`h`nmdf8wjsuklUgeckabb9p}keCm}ohxhj>4:qzjfBb|liiiQbuy23444b3zseoIk{ebvf`Zkrp9:;=Rgbp^qzjfBb|liiiQbuy23447682rh?~;?0d/7)ca4:9wKL}?:3:BC|00=N381=v]j:47973<6;::8:84>8c`bk34281e9949;%71>1c<uZn1984<6;307551=3;3nom4d6g94?7=9rYn68;537827664><0:4oln;wD73?6=93;1<v]j:47973<6;::8:84>8c`b?!2c2:90(9<52:`4a?6=l3i1=5uC5182!2521>0qA;>:0y'3c<6:2w/8n48e:Xb>4}42tP?57?t4;j12<722c<n7>5;n50>5<<a>n1<75f5983>>i1i3:1(9:5689m06<732e=47>5$5692<=i<:0:76a97;29 12=>01e8>4=;:m52?6=,=>1:45a4280?>i1=3:1(9:5689m06<332e=87>5$5692<=i<:0>76a93;29 12=>01e8>49;:m56?6=,=>1:45a4284?>d213:1n7?5bzN64?7|@:;0qA;>:3y'3c<6:2d3<7::;|&7g?403`l1<75f4983>>i413:17b=n:188k6d=831d?n4?::m0`?6=3f9n6=44o2d94?=h<90;66a;1;29?g41290i6o4k{M73>4}O;81v(9m5589j55<722c<6=44o2;94?=h;h0;66a<b;29?j5d2900c>j50;9l7`<722e8j7>5;n63>5<<g=;1<75m1c83>1<729q/8n4>4:J7b>J283;p(?k51:jf?6=3`;:6=44i5794?=h<?0;66sm2483>1<729q/8n4>3:J7b>J283;p(?k50:jf?6=3`i1<75f1083>>i3>3:17pl=4;290?6=8r.?o7?<;I6e?I3728q/>h4?;|ka>5<<aj0;66g>1;29?j212900qo<<:187>5<7s->h6<=4H5d8H06=9r.9i7>4}h`94?=nk3:17d?>:188k10=831vn?<50;694?6|,=i1=>5G4g9O15<6s-8n6=5ric83>>od2900e<?50;9l03<722wi><4?:583>5}#<j0:?6F;f:N64?7|,;o1<6sfb;29?le=831b=<4?::m72?6=3th9<7>54;294~"3k3;87E:i;M73>4}#:l0;7pgm:188mf<722c:=7>5;n65>5<<uk;m6=4;:183!2d2890D9h4L4295~"5m3:0qdl50;9jg?6=3`;:6=44o5494?=zj8i1<7:50;2x 1e=9:1C8k5C5182!4b291veo4?::k`>5<<a8;1<75`4783>>{e9<0;694?:1y'0f<6;2B?j6B:0;3x 7c=82wbn7>5;ha94?=n980;66a;6;29?xd>29096=4?{%6`>7`<@=l0e?l50;9l70<722wx=o4?:3y>5g<3>27997?>;|q24?6=jrT:<63>b;`8973=j27987l4=319f>;5:3h01??5b:?14?d<58l1n63>c;`8943=j2wx;7>52z\4?8?=:k1v>750;1xZ6?<5;?18;5225825>{t;h0;6>uQ3`9>61<3>279?7?>;|q0f?6=;rT8n63=3;65?84528;0q~=l:180[5d34896984=33954=z{:n1<7=t^2f8977=<?16>=4>1:p7`<72:qU?h5221872>;6n3;:7p}<f;297~X4n27:j7:9;<3`>47<uz>;6=4<{_63?87d2=<01<;5109~w17=839pR9?4=0`954=:9<0?:6s|8;29f~;6j3>>70?::b9>5f<d34;m6n52218`?8462j16>?4l;<00>f=::=0h70<::b9>=?523twxj7>52z\e?84128:0q~:7:181[2?348=6:5rs2;94?4|V:301?85389~w6g=838pR>o4=3497d=z{:h1<7<t^2`8970=;k1v>m50;0xZ6e<5;<1?n5rs2f94?4|V:n01?853e9~w6c=838pR>k4=3497`=z{:l1<7<t^2d8970=;o1v9>50;0xZ16<5;<18=5rs5394?4|V=;01?85409~yg13290=6<49{M73>4}O;81v@8?52z&4b?753g2;6<j4}%6`>7><ao0;66g;8;29?j5>2900c>o50;9l7g<722c8<7>5;c05>5<12=0<wA;?:0yK74=z,=i1;95f3183>>o683:17d950;9l7<<722e8m7>5;n1a>5<<j8?1<7:50;2x 1e=9:1C8k5C5182!4b291veo4?::k`>5<<a8;1<75`4783>>{e9j0;694?:1y'0f<6;2B?j6B:0;3x 7c=82wbn7>5;ha94?=n980;66a;6;29?xd6i3:187<55z&7g?7f3`9;6=44i0a94?=n;k0;66a>6;29?g7>29086=4?{%6`>3=O<o1b>n4?::k1`?6=3f9>6=44}c3;>5<4290;w):l:258L1`<a;i1<75f2e83>>i4=3:17p}<0;296~X4827:57<l;|q2g?6=:rT:o63>9;0g?xu4j3:1>vP<b:?2<?4d3ty::7>52z\22>;6039>7p}>7;296~;6139>70?7:3f8yxd6m3:1?7>50z&7g?5?3A>m7d<l:188m7b=831d?84?::p5f<72;q6=n4;6:?2e?7d3ty8<7>53z\04>;6i39;70?j:3a8yv772908wS??;<36>g=:9j0i7p}8:180[1<58?1o63>c;a8yv5e290?wS=m;<36>10<58k1?o521d81`>{t9?0;6?u214825>;6i3;=7p}>d;296~;6k3;:70?j:278yxua2909wSh4=34955=z{=21<7<t^5:8970=?2wx?44?:3y]7<=::?0856s|3`83>7}Y;h16>;4<a:p7g<72;qU?o522780f>{t;90;6?uQ319>63<482wvn;l50;195?5|D<:1=vF<1:O14<0sg2;6884$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn;m50;195?5|D<:1=vF<1:O14<0sg2;68l4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn;j50;195?5|D<:1=vF<1:O14<0sg2;6;>4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn;k50;195?5|D<:1=vF<1:O14<0sg2;6;;4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn;h50;195?5|D<:1=vF<1:O14<0sg2;6;o4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn:>50;195?5|D<:1=vF<1:O14<0sg2;6;h4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn:?50;195?5|D<:1=vF<1:O14<0sg2;6::4$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn:<50;195?5|D<:1=vF<1:O14<0sg2;6:74$6a933=#?10:=6*8a;65?!1>2;k0b:951:&4b?753t.?o7=;;h32>5<<g=<1<75f2`83>>d729086=4?{%6`>64<@=l0e<?50;9j6<<722e?:7>5;|q25?6=:rT:=63?:038yv212909wS:9;<2903=z{;k1<7<t^3c895<512wvn5?50;694?6|,=i1=>5G4g9O14<5s-=m6<<4n9295`=zak0;66gl:188m47=831d8;4?::a<6<72:0;6=u+4b86?M2a3`8h6=44i3f94?=h;<0;66s|5683>7}Y=>16944i;|q4f?6=;rT<n6384;6;?8>62j1v:=50;0xZ25<5<318<5rs6f94?d|V>n01::5319>2g<6927=o7?>;<4g>47<5?o1=<526g825>;083;:709>:038924=98164>4=d:p1=<72:qU9552758e?8>62k1v8o50;0x90?=;016:o4=a:p1g<72;q6944<a:?5g?4f3ty>o7>52z?6=?5e34<o6?o4}r7g>5<5s4?26>m4=7g96d=z{<o1<7<t=4;97a=:>o09m6s|5g83>7}:=008i6380;0b?xu183:1>v3:9;1e?8162;k0q~8>:18183>2=:01:<52`9~w=4=838p15?5109><6<4=2wx;84?:3y>31<4j273?7<l;|q;5?6=:r7>57:7;<:2>10<uz<j6=4={_4b?8152=<0(9l5689m0d<73ty=47>52z\5<>;093>=7):m:7;8j1g=92wx::4?:3y]22=:?90?:6*;b;4:?k2f2;1v;850;0xZ30<5?l18;5+4c85=>h3i390q~8::181[0234<n6984$5`92<=i<h0?7p}94;296~X1<27=h7:9;%6a>3?<f=k196s|6283>7}Y>:16:n4;6:&7f?0>3g>j6;5rs7094?4|V?801;l5479'0g<112d?m794}|~yEFDs8?869;6530;4xFGJr:vLM^t}AB
$0;f4=792;:7??43e90w067mom8>=#;1:62?07<>81<4665D=594;c<03CE\XZ5D=594;`<03E^X][[:P>4>586?221CXZ_UU8geqgXjp~n0:4?>99;>T:0294:?665bxvfV`ebaoo0:4?>028<?bf|hUiuyk37;2=0>GIL;<0MCJ=B048EKB5J;<0MCJ<B3:8EfusWOYFo6Olsu]EWHYnf;n7Lm|t^DPIZoi~Vcf|ROlsu]EWHYnf;?7L{{o59AQCR?3K_XSD@IO09@7>EKZ01HC@CFTUGG3>EUMH^NH>5Llj58GimXNZG:7I:4D=2=0>B;97>0H1<14:F?7;2<L5>586J35?68@909>2N7;7>14:F?3;573L0$yl|{_cnlgn)ole%bh^}okg`p*ubz`kgSklehtfv+pol:1MHN=4FER7?C@c9>1MJi?"Io:8BCb6%@d:56HId0/Jj47>3OLo= Ga20:8BCb6%@d8n6HId0/JjZojx8>0JKj>-Hl\mhvXNOn:!D`>5:DE`46?3OLo==#Fn59EBa403OLo> Ga159EBa4*AgUba}QIFe0.Mk733OLo?95IFe67?C@c==1MJi8;;GDg31=ANm2?7KHk929EWHe<NZGT< ~nrdlwg>@TEV;&|l|jnu38C7=@M:1LBI:4G`vf2>Af|lOe=6G=;H21?L753@8?7D@FT29JJS5<AFH87D`?3:Km5`=LMLZTDDK]ASAK]7=KL:1GHH94LNEJGDJe3EZFSAO[CI]2f>JWEVFJXNFP2c9OTHYKI]ICS>?7;LvqmagsiVhrxh\jcdkuaa:76820Ay|fd`vb[gsm[ohidxjd=3=65=J|{comyoPbxvfV`ebaoo0<0Pnnv34573>2G~djnt`]a}qcUmjobzhj31?]mkq6788Uba}QBtskgeqgXjp~n^hmjiwgg848Xff~;<=?>199Npwoci}kTntzjRdafmscc4;49<6C{rhfbpdYeq}oYinkfvdf?6;Yj}q:;<=<>;LvqmagsiVhrxh\jcdkuaa:56Vg~t=>?0001?HruamkmRlvtdPfg`oqmm692Rczx1234475:2G~djnt`]a}qcUmjobzhj32?]nq}67898:><5BtskgeqgXjp~n^hmjiwgg878Xe|r;<=><259Npwoci}kTntzjRdafmscc4;4Taxv?012\mhv582G~djnt`]a}qcUmjobzhj32?]mkq6788>=7@z}iecweZd~|lXnohgyee>1:Zhh|9:;=Rgbp^Owvlbf|hUiuyk]ebgjr`b;:7Uecy>?0032<>Ksz`njxlQmyugQafcn~ln7?3<?;LvqmagsiVhrxh\jcdkuaa:46Vg~t=>?0338Iqtnlh~jSow{eSg`alpbl595S`{w0123574<E}xbhlzn_c{waWcdm`|nh1=1_lw{4567988:7@z}iecweZd~|lXnohgyee>0:Zkrp9:;<?<=;LvqmagsiVhrxh\jcdkuaa:46Vg~t=>?03316>Ksz`njxlQmyugQafcn~ln7?3Qbuy234556:;1Fxgkauc\f|rbZline{kk<2<\ip~789:?=?<4Mupj`drfWksi_klehtf`959Wds<=>?5002?HruamkmRlvtdPfg`oqmm682Rczx12343433D~yeio{a^`zp`Tbklc}ii2<>^ov|5678Vcf|<64Mupj`drfWksi_klehtf`929:91Fxgkauc\f|rbZline{kk<5<\ip~789:9=6C{rhfbpdYeq}oYinkfvdf?0;Yj}q:;<=?=2:Owvlbf|hUiuyk]ebgjr`b;<7Ufyu>?013264=J|{comyoPbxvfV`ebaoo090Pmtz34565:;1Fxgkauc\f|rbZline{kk<5<\ip~789:9=??4Mupj`drfWksi_klehtf`929Wds<=>?3308Iqtnlh~jSow{eSg`alpbl5>5S`{w012374453D~yeio{a^`zp`Tbklc}ii2;>^ov|5678=;9>6C{rhfbpdYeq}oYinkfvdf?0;Yj}q:;<=;>239Npwoci}kTntzjRdafmscc4=4Taxv?0125574<E}xbhlzn_c{waWcdm`|nh1:1_lw{4567?8897@z}iecweZd~|lXnohgyee>7:Zkrp9:;<5?=1:Owvlbf|hUiuyk]ebgjr`b;<7Ufyu>?01;10>Ksz`njxlQmyugQafcn~ln783Qbuy2345Yney;37@z}iecweZd~|lXnohgyee>6:76<E}xbhlzn_c{waWcdm`|nh1;1_lw{4567:81Fxgkauc\f|rbZline{kk<4<\ip~789::>>5BtskgeqgXjp~n^hmjiwgg808Xe|r;<=>>0001?HruamkmRlvtdPfg`oqmm6>2Rczx1234475;2G~djnt`]a}qcUmjobzhj35?]nq}6789;:=?<4Mupj`drfWksi_klehtf`939Wds<=>?1301?HruamkmRlvtdPfg`oqmm6>2Rczx123445592G~djnt`]a}qcUmjobzhj35?]nq}678989>6C{rhfbpdYeq}oYinkfvdf?1;Yj}q:;<=<>209Npwoci}kTntzjRdafmscc4<4Taxv?012067=J|{comyoPbxvfV`ebaoo080Pmtz345649;;0Ay|fd`vb[gsm[ohidxjd=7=[hs89:;8?<4Mupj`drfWksi_klehtf`939Wds<=>?4001?HruamkmRlvtdPfg`oqmm6>2Rczx1234075:2G~djnt`]a}qcUmjobzhj35?]nq}6789<:>?5BtskgeqgXjp~n^hmjiwgg808Xe|r;<=>81308Iqtnlh~jSow{eSg`alpbl5?5S`{w0123<4453D~yeio{a^`zp`Tbklc}ii2:>^ov|56780;986C{rhfbpdYeq}oYinkfvdf?1;Yj}q:;<=Qfmq3;?HruamkmRlvtdPfg`oqmm6=2?>4Mupj`drfWksi_klehtf`909Wds<=>?209Npwoci}kTntzjRdafmscc4?4Taxv?012266=J|{comyoPbxvfV`ebaoo0;0Pmtz3456688897@z}iecweZd~|lXnohgyee>5:Zkrp9:;<<?=3:Owvlbf|hUiuyk]ebgjr`b;>7Ufyu>?0132575<E}xbhlzn_c{waWcdm`|nh181_lw{45679;;9?6C{rhfbpdYeq}oYinkfvdf?2;Yj}q:;<=?<1318Iqtnlh~jSow{eSg`alpbl5<5S`{w01235175:2G~djnt`]a}qcUmjobzhj36?]nq}6789;>>?5BtskgeqgXjp~n^hmjiwgg838Xe|r;<=>>6338Iqtnlh~jSow{eSg`alpbl5<5S`{w0123674<E}xbhlzn_c{waWcdm`|nh181_lw{4567:88:7@z}iecweZd~|lXnohgyee>5:Zkrp9:;<><=;LvqmagsiVhrxh\jcdkuaa:16Vg~t=>?02315>Ksz`njxlQmyugQafcn~ln7:3Qbuy234525:2G~djnt`]a}qcUmjobzhj36?]nq}6789>:><5BtskgeqgXjp~n^hmjiwgg838Xe|r;<=>:239Npwoci}kTntzjRdafmscc4?4Taxv?0126574<E}xbhlzn_c{waWcdm`|nh181_lw{4567>8897@z}iecweZd~|lXnohgyee>5:Zkrp9:;<:?=2:Owvlbf|hUiuyk]ebgjr`b;>7Ufyu>?01:267=J|{comyoPbxvfV`ebaoo0;0Pmtz3456>9;>0Ay|fd`vb[gsm[ohidxjd=4=[hs89:;Sdc199Npwoci}kTntzjRdafmscc4>49<6C{rhfbpdYeq}oYinkfvdf?3;Yj}q:;<=<>;LvqmagsiVhrxh\jcdkuaa:06Vg~t=>?0000?HruamkmRlvtdPfg`oqmm6<2Rczx1234466:;1Fxgkauc\f|rbZline{kk<6<\ip~789::=?=4Mupj`drfWksi_klehtf`919Wds<=>?10317>Ksz`njxlQmyugQafcn~ln7;3Qbuy2345759;90Ay|fd`vb[gsm[ohidxjd=5=[hs89:;=>?=3:Owvlbf|hUiuyk]ebgjr`b;?7Ufyu>?0137575<E}xbhlzn_c{waWcdm`|nh191_lw{45679<;9?6C{rhfbpdYeq}oYinkfvdf?3;Yj}q:;<=?91318Iqtnlh~jSow{eSg`alpbl5=5S`{w01235275:2G~djnt`]a}qcUmjobzhj37?]nq}6789;3>?5BtskgeqgXjp~n^hmjiwgg828Xe|r;<=>>9338Iqtnlh~jSow{eSg`alpbl5=5S`{w0123674<E}xbhlzn_c{waWcdm`|nh191_lw{4567:88:7@z}iecweZd~|lXnohgyee>4:Zkrp9:;<><=;LvqmagsiVhrxh\jcdkuaa:06Vg~t=>?02315>Ksz`njxlQmyugQafcn~ln7;3Qbuy234525:2G~djnt`]a}qcUmjobzhj37?]nq}6789>:><5BtskgeqgXjp~n^hmjiwgg828Xe|r;<=>:239Npwoci}kTntzjRdafmscc4>4Taxv?0126577<E}xbhlzn_c{waWcdm`|nh191_lw{4567>;80Ay|fd`vb[gsm[ohidxjd=5=[hs89:;:<<=;LvqmagsiVhrxh\jcdkuaa:06Vg~t=>?06316>Ksz`njxlQmyugQafcn~ln7;3Qbuy2345>6:;1Fxgkauc\f|rbZline{kk<6<\ip~789:2=?:4Mupj`drfWksi_klehtf`919Wds<=>?_hos53=J|{cnbRlvtdPfg`oqmm6;2<k4MupjakYeq}oYinkfvdf?4;Yffm:;<=:=;Lvqm`hXjp~n^hmjiwgg858Xign;<=>Pilr\IqtnmgUiuyk]ebgjr`b;87Ujbi>?0132a>Ksz`oeSow{eSg`alpbl5:5Sca{012207=J|{cnbRlvtdPfg`oqmm6;2R``t1235ZojxVG~dka_c{waWcdm`|nh1>1_omw456698<0Ay|feo]a}qcUmjobzhj31?3f?HrualdTntzjRdafmscc484Tmcj?01276>Ksz`oeSow{eSg`alpbl5;5Sl`k0123[lkwWD~yeh`PbxvfV`ebaoo0<0Paof345669l1Fxgjn^`zp`Tbklc}ii2>>^llp5679=80Ay|feo]a}qcUmjobzhj31?]mkq6788Uba}QBtskfjZd~|lXnohgyee>2:Zhh|9:;=<?k;Lvqm`hXjp~n^hmjiwgg848Xg{:;<=:?;Lvqm`hXjp~n^hmjiwgg848Xg{:;<=Qfmq]NpwobfVhrxh\jcdkuaa:66Vey<=>?1048IqtnmgUiuyk]ebgjr`b;:7;n7@z}idl\f|rbZline{kk<3<\ekb789:?>6C{rhgm[gsm[ohidxjd=0=[dhc89:;Sdc_Lvqm`hXjp~n^hmjiwgg878Xign;<=>>1d9NpwobfVhrxh\jcdkuaa:56Vddx=>?1508IqtnmgUiuyk]ebgjr`b;:7Uecy>?00]jiuYJ|{cnbRlvtdPfg`oqmm692R``t123547c3D~yeh`PbxvfV`ebaoo0?0Pos2345273D~yeh`PbxvfV`ebaoo0?0Pos2345YneyUFxgjn^`zp`Tbklc}ii2=>^mq456798n0Ay|feo]a}qcUmjobzhj32?]lv5679=:0Ay|feo]a}qcUmjobzhj32?]lv5679Vcf|RC{rhgm[gsm[ohidxjd=0=[jt789;:=;5BtskfjZd~|lXnohgyee>0:4c<E}xbicQmyugQafcn~ln7?3Qnne2345253D~yeh`PbxvfV`ebaoo0>0Paof3456XadzTAy|feo]a}qcUmjobzhj33?]bja6789;:i6C{rhgm[gsm[ohidxjd=1=[kis89::8?5BtskfjZd~|lXnohgyee>0:Zhh|9:;=Rgbp^OwvlciWksi_klehtf`959Wge<=>>10f8IqtnmgUiuyk]ebgjr`b;;7Ud~=>?0528IqtnmgUiuyk]ebgjr`b;;7Ud~=>?0^kntZKsz`oeSow{eSg`alpbl595Sb|?01225a=J|{cnbRlvtdPfg`oqmm682Ra}012205=J|{cnbRlvtdPfg`oqmm682Ra}0122[lkwWD~yeh`PbxvfV`ebaoo0>0Pos234476l2G~dka_c{waWcdm`|nh1=1_np3454382G~dka_c{waWcdm`|nh1=1_np3454XadzTAy|feo]a}qcUmjobzhj33?]lv567:8;=7@z}idl\f|rbZline{kk<5<2a>Ksz`oeSow{eSg`alpbl5>5Sl`k012307=J|{cnbRlvtdPfg`oqmm6?2Road1234ZojxVG~dka_c{waWcdm`|nh1:1_`lg456798o0Ay|feo]a}qcUmjobzhj34?]mkq6788>97@z}idl\f|rbZline{kk<5<\jjr789;Te`~PMupjakYeq}oYinkfvdf?0;Yig}:;<<?>d:OwvlciWksi_klehtf`929Wfx;<=>;0:OwvlciWksi_klehtf`929Wfx;<=>Pilr\IqtnmgUiuyk]ebgjr`b;<7Ud~=>?003g?HrualdTntzjRdafmscc4=4Tc>?0063?HrualdTntzjRdafmscc4=4Tc>?00]jiuYJ|{cnbRlvtdPfg`oqmm6?2Ra}012254b<E}xbicQmyugQafcn~ln783Q`r123616<E}xbicQmyugQafcn~ln783Q`r1236ZojxVG~dka_c{waWcdm`|nh1:1_np345469m1Fxgjn^`zp`Tbklc}ii2;>^mq4564<91Fxgjn^`zp`Tbklc}ii2;>^mq4564W`g{S@z}idl\f|rbZline{kk<5<\kw678:;::6C{rhgm[gsm[ohidxjd=7=5`=J|{cnbRlvtdPfg`oqmm6>2Road123414<E}xbicQmyugQafcn~ln793Qnne2345YneyUFxgjn^`zp`Tbklc}ii2:>^cm`56788;n7@z}idl\f|rbZline{kk<4<\jjr789;?>6C{rhgm[gsm[ohidxjd=7=[kis89::Sdc_Lvqm`hXjp~n^hmjiwgg808Xff~;<=?>1e9NpwobfVhrxh\jcdkuaa:26Vey<=>?419NpwobfVhrxh\jcdkuaa:26Vey<=>?_hos[HrualdTntzjRdafmscc4<4Tc>?0132`>Ksz`oeSow{eSg`alpbl5?5Sb|?01374>Ksz`oeSow{eSg`alpbl5?5Sb|?013\mhvXE}xbicQmyugQafcn~ln793Q`r123547c3D~yeh`PbxvfV`ebaoo080Pos2347273D~yeh`PbxvfV`ebaoo080Pos2347YneyUFxgjn^`zp`Tbklc}ii2:>^mq456598n0Ay|feo]a}qcUmjobzhj35?]lv567;=:0Ay|feo]a}qcUmjobzhj35?]lv567;Vcf|RC{rhgm[gsm[ohidxjd=7=[jt7899:=i5BtskfjZd~|lXnohgyee>6:Ziu89:?8=5BtskfjZd~|lXnohgyee>6:Ziu89:?Sdc_Lvqm`hXjp~n^hmjiwgg808Xg{:;<9?>6:OwvlciWksi_klehtf`9099l1Fxgjn^`zp`Tbklc}ii29>^cm`5678=80Ay|feo]a}qcUmjobzhj36?]bja6789Uba}QBtskfjZd~|lXnohgyee>5:Zgil9:;<<?j;Lvqm`hXjp~n^hmjiwgg838Xff~;<=?;2:OwvlciWksi_klehtf`909Wge<=>>_hos[HrualdTntzjRdafmscc4?4Tbbz?01325a=J|{cnbRlvtdPfg`oqmm6=2Ra}012305=J|{cnbRlvtdPfg`oqmm6=2Ra}0123[lkwWD~yeh`PbxvfV`ebaoo0;0Pos234576l2G~dka_c{waWcdm`|nh181_np3457382G~dka_c{waWcdm`|nh181_np3457XadzTAy|feo]a}qcUmjobzhj36?]lv56798;o7@z}idl\f|rbZline{kk<7<\kw678;>;7@z}idl\f|rbZline{kk<7<\kw678;Uba}QBtskfjZd~|lXnohgyee>5:Ziu89:9=<j4MupjakYeq}oYinkfvdf?2;Yhz9:;?9>4MupjakYeq}oYinkfvdf?2;Yhz9:;?Rgbp^OwvlciWksi_klehtf`909Wfx;<==>1e9NpwobfVhrxh\jcdkuaa:16Vey<=>;419NpwobfVhrxh\jcdkuaa:16Vey<=>;_hos[HrualdTntzjRdafmscc4?4Tc>?0532`>Ksz`oeSow{eSg`alpbl5<5Sb|?01774>Ksz`oeSow{eSg`alpbl5<5Sb|?017\mhvXE}xbicQmyugQafcn~ln7:3Q`r12314713D~yeh`PbxvfV`ebaoo0:0>e:OwvlciWksi_klehtf`919Whdo<=>?439NpwobfVhrxh\jcdkuaa:06Vkeh=>?0^kntZKsz`oeSow{eSg`alpbl5=5Sl`k012354c<E}xbicQmyugQafcn~ln7;3Qaou2344253D~yeh`PbxvfV`ebaoo0:0Pnnv3457XadzTAy|feo]a}qcUmjobzhj37?]mkq6788;:h6C{rhgm[gsm[ohidxjd=5=[jt789:?<6C{rhgm[gsm[ohidxjd=5=[jt789:Te`~PMupjakYeq}oYinkfvdf?3;Yhz9:;<<?k;Lvqm`hXjp~n^hmjiwgg828Xg{:;<<:?;Lvqm`hXjp~n^hmjiwgg828Xg{:;<<Qfmq]NpwobfVhrxh\jcdkuaa:06Vey<=>>10f8IqtnmgUiuyk]ebgjr`b;?7Ud~=>?2528IqtnmgUiuyk]ebgjr`b;?7Ud~=>?2^kntZKsz`oeSow{eSg`alpbl5=5Sb|?01025a=J|{cnbRlvtdPfg`oqmm6<2Ra}012005=J|{cnbRlvtdPfg`oqmm6<2Ra}0120[lkwWD~yeh`PbxvfV`ebaoo0:0Pos234676l2G~dka_c{waWcdm`|nh191_np3452382G~dka_c{waWcdm`|nh191_np3452XadzTAy|feo]a}qcUmjobzhj37?]lv567<8;o7@z}idl\f|rbZline{kk<6<\kw678<>;7@z}idl\f|rbZline{kk<6<\kw678<Uba}QBtskfjZd~|lXnohgyee>4:Ziu89:>=<j4MupjakYeq}oYinkfvdf?3;Yhz9:;:9>4MupjakYeq}oYinkfvdf?3;Yhz9:;:Rgbp^OwvlciWksi_klehtf`919Wfx;<=8>2:L36>H6:2D9>6@<2:L76>H2:2D=>6@82:L;6>H>92E37B 77yf\H6=HZ;?0C_<M159Lqq633F=95@uu07?Jss;l1Dyy=Pilr\Kpr49=1Dyy:;;Nww11=H}}<?7B{{759Lqq>33F595_ASVb?UOIWK_XEIVm;QKM[GSTFHGN?6^]E09R0>W;87>0]1?14:S?6;2<Y59586_34?68U939<2[7:384Q=594;2<Y5=5?6\[L29Qwqd<[@MIY^QFNGMb?VO@WK_XEIVm;RKD[GSTFHGN=6Z;;U[SA<=QAL]TXT^J1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF6:ZPPIOE?2RXXRIAD0g8\VRXADZGI@KAT@VJKKYDGGY_^LGATR33?]USW[^GS]\@PDPW]3=_lkUBh<>4Xeo\Idlhz_oydaa119[`hYJageyZh||inl0?]us12RxxJC`ddn4?ggrlJf`=<5matfLr`tTidzgiNbdf:`zp`Tbklc}ii2?>3:8f|rbZline{kk<1<\Iqtnlh~jSow{eSg`alpbl5:5j6lvtdPfg`oqmm6:2?64bxvfV`ebaoo0<0PMupj`drfWksi_klehtf`979n2hrxh\jcdkuaa:56;20ntzjRdafmscc4;4TAy|fd`vb[gsm[ohidxjd=0=b>d~|lXnohgyee>0:7><jp~n^hmjiwgg868XE}xbhlzn_c{waWcdm`|nh1=1f:`zp`Tbklc}ii2;>3:8f|rbZline{kk<5<\Iqtnlh~jSow{eSg`alpbl5>5j6lvtdPfg`oqmm6>2?64bxvfV`ebaoo080PMupj`drfWksi_klehtf`939n2hrxh\jcdkuaa:16;20ntzjRdafmscc4?4TAy|fd`vb[gsm[ohidxjd=4=54=eq}oYinkfvdf?3?69n2hrxh\jcdkuaa:06;20ntzjRdafmscc4>4TAy|fd`vb[gsm[ohidxjd=5==>erz{oexR}>4:avvwci|VyTo`~Pep2344733jy~h`{_r]`iuYby9:;><:4ctpqakrX{Vif|Rk~012051=d}{xnbyQ|_bos[`w789>:86mzrsgmpZuXkdzTi|>?0437?fsuzldS~Qlmq]fu567>8>0ox|}eov\wZejxVoz<=>8159`qwtbf}UxSnc_ds345>6<2i~~kat^q\ghvXmx:;<474d`vb[gsmj1omyoPbxvf858d3mkmRlvtd>2:f=ci}kTntzj<3<`?agsiVhrxh2<>b9geqgXjp~n090l;ecweZd~|l6>2n5kauc\f|rb4?4n7io{a^`zp`:0294h7io{a^`zp`:06h1omyoPrdcg}==aae~n~_v>3:djhqcuZqUha}Qjq12370=ki}ic46~`l^ebp`?<xfxSio{a89skwrXoh~n:6~`ru]r7>tt|11yxaQ{yqg:?vcuahfTech4sdpjeiYumjobzh|i;rmvvfcXn`fnblcjd:qlqwebWeceicll;r{mgAcsmj~nh<:4sxl`@`rbk}ooS`{w012350=tqgiOiykltdf\ip~789::=;5|yoaGaqcd|lnTaxv?0122540<{pdhHhzjcugg[hs89:;><?:;r{mgAcsmj~nhRczx123467?3zseoIk{ebvf`Zkrp9:;<Rgbp028|f5t=9:n!9#ig203yEFw=:h0LMv>618E>7<6sZ;o6<;i:010>4548:<>6<jk7dym50b=92d:9h49;%36g?72?2wX=n4>5g8276<6;::8:84>de:3?a7>;3:1=7?tS0f950`=9:91=>=?37795ab0m2|M=9h50;395?6|[8n1=8h512195657;??1=ij8e:&213<2=2.:8<4;;c3:7?6=l3?:6;;tL07b>4}#9=;1=4j4}M36f?7|,83?6?o4}%361?7>;2P:57?tc;Y507=:rl1i7sf17394?=n90:1<75`19:94?=n9081<75f17094?=h91=1<7*>4282<3=i9=81<65`19794?"6<:0:4;5a15095>=h91>1<7*>4282<3=i9=81>65`19194?"6<:0:4;5a15097>=h9181<7*>4282<3=i9=81865`19394?"6<:0:4;5a15091>=h91:1<7*>4282<3=i9=81:65`16d94?"6<:0:4;5a15093>=e9>>1<7m51;axH43f28qC9?5rL07a>7}#90>1>l5a18790c=z,8?>69<4i0g94?=n9<:1<75`12494?=h9:=1<75`12:94?=h9:31<75`12`94?=h9:i1<75`12f94?=h9:o1<75`12d94?=h9=:1<75m4083>f<c2oqG=8o51zJ66>{#9<?1=::4i0d94?=n9=0;66a>3783>>i6;>0;66a>3983>>i6;00;66a>3c83>>i6;j0;66a>3e83>>i6;l0;66a>3g83>>i6<90;66l>5883>4<729q/=8;5479K50><g=>1<75rb3f94?2=83:p(<;::3`8L43?3E;>m7?t$5f94>{n9h0;66g>b;29?l472900c<:::188yg52290?6=4?{%361?4d3A;>46B>5`82!2c281ve<o50;9j65<722c:894?::m200<722wi8=4?:583>5}#9<?1>o5G14:8H43f28q/8i4?;|k2e?6=3`;i6=44i3294?=h9=?1<75rb2d94?2=83:p(<;::3`8L43?3E;>m7?t$5f94>{n9h0;66g>b;29?l472900c<:::188yg5b290?6=4?{%361?4e3A;>46B>5`82!2c291ve<o50;9j5g<722c9<7>5;n371?6=3th8h7>54;294~"6=<09n6F>599O50g=9r.?h7>4}h3b>5<<a8h1<75f2183>>i6<<0;66sm3b83>1<729q/=8;52c9K50><D8?j6<u+4e83?xo6i3:17d?m:188m76=831d=9;50;9~f6d=83>1<7>t$076>7d<@8?37A?:a;3x 1b=82wb=l4?::k2f?6=3`8;6=44o066>5<<uk9j6=4;:183!72=38i7E?:8:N21d<6s->o6=5ri0c94?=n9k0;66g=0;29?j73=3:17pl<7;290?6=8r.:984=b:J21==K9<k1=v*;d;28yl7f2900e<l50;9j65<722e:884?::a71<72:0;6=u+1479562<@8?37d:n:188m1d=831d=><50;9~f40=8381<7>t$076>1c<@8?37d:6:188k4552900q~?i:18a[7a348o6<o4=2795d=:<90:m63<f;3b?85b28k01>j51`9>7f<6i278n7?n;<1b>4g<5:=1=l5rs0694?4|V8>01<85489~w4512908wS?<6:?1`?73=27887:n;|q272<72:qU=>94=529513<5:l1>=5rs01;>5<4sW;8463<f;371>;4m38;7p}>3883>6}Y9:301>k5157896b=:91v<=m:180[74j278h7?;5:?0g?473ty:?n4?:2y]56e<5:i1=9;4=2`965=z{89o6=4<{_30`>;4j3;?963<a;03?xu6;l0;6>uQ12g896g=9=?01>95219~w45a2908wS?<f:?03?73=27887:m;|q205<72:qU=9>4=279513<5=:1>=5rs3g94?4|5;n1>=52358277=z{:<1<7<t=07:>12<5:?1>=5rs0794?d|5;n1=o523682f>;4i3;i70=m:0`896e=9k16?i4>b:?0a?7e349m6<l4=5295g=:;<0:8952178277=zuz;n6=4={_3f?82628l0q~?:0;296~X6=9168<4>4:p560=838pR<=9;<62>4513ty:?:4?:3y]561<5=;1=>94}r30<?6=:rT:?55240827==z{8926=4={_30=>;393;856s|12`94?4|V89i70:>:01a?xu6;j0;6?uQ12a8917=9:i0q~?<d;296~X6;m168<4>3e9~w45b2909wS?<e:?75?74m2wx=>h50;0xZ45a34>:6<=i;|q205<72;qU=9>4=539516<uth:444?:982>=}K9<k1=vF:2:O50d=:r.:594=a:l2=0<6l2w/=8;5429j5`<722c:9=4?::m273<722e:?:4?::m27=<722e:?44?::k64?6=3`?:6=44b5394?>==33p@<;n:0yK17=z,8?>6<66;h73>5<<a<;1<75f1g83>>o6<3:17b?<6;29?j74?3:17b?<8;29?j7413:17o<k:187>5<7s-;>97<m;I36<>J6=h0:w):k:19~m4g=831b=o4?::k14?6=3f;?97>5;|`03?6=<3:1<v*>5481f>N6=11G=8o51z&7`?6<u`;j6=44i0`94?=n:90;66a>4483>>{e;:0;684<:6y'503=;:1b?:4?::k64?6=3`?:6=44i3f94?=h:l0;66l<2;290?6=8r.:984>3:J21==n<h0;66g;b;29?l2d2900c<==:188yg5729086=4?{%361?763A;>46g;a;29?l2e2900c<==:188yg5629086=4?{%361?74<2B:955f4`83>>o3j3:17b?<2;29?xu4?3:1?vP<7:?06?2f349;69l4}r73>5<5sW?;70=?:5c8yv362909wS;>;<11>1d<uz8o6=4={_0g?8552=i0q~<j:181[4b349:6<==;|q1b?6=:r78>7?<2:?05?2f3ty8<7>52z?04?74:278=7:m;|a7<<72:0;6=u+147957=O9<20e9o50;9j0g<722e:??4?::a56g=8391<7>t$076>47<@8?37d:n:188m1d=831d=><50;9~w7b=83>p1?j51578965=:m16?44;b:?27d<3j2wx?:4?:2y>72<6<<16?>4<7:?27d<3i2wx9=4?:2y]15=:;:0><63<9;6b?xu293:1>vP:1:?07?363ty:j7>53z\2b>;5l3;j70=8:0c8yv732908wS?;;<0g>4d<5:=1=o5rs01:>5<5sW;8563>3`8277=z{;o1<7<t=3f965=:;:09i6s|3983>7}:;>09<63<9;306>{z{8o1<7<t^0g8917=9o1v<;?:181[72827?=7?;;|q273<72;qU=>84=539560<uz;8;7>52z\272=:<80:?:5rs01;>5<5sW;8463;1;30<>{t9:31<7<t^01:?82628927p}:0;296~X2827?=7;?;|q65?6=:rT>=63;1;72?x{e9>o1<7?>:9825~J6=h0:wE;=;|N21g<0sg;29766;%3:5?7?j2.:4i4=0:&2<c<6<<1/=5k5469m5=e=92.:594=a:'503==?1Q=44={c8b>x\6=809wi46:|k73?6=3f;?i7>5$060>42c3g;?>7>4;n37g?6=,8>86<:k;o376?7<3f;?n7>5$060>42c3g;?>7<4;n37e?6=,8>86<:k;o376?5<3f;?57>5$060>42c3g;?>7:4;n37<?6=,8>86<:k;o376?3<3f;?;7>5$060>42c3g;?>784;n372?6=,8>86<:k;o376?1<3`826=4+15196==i9=81<65f2683>!73;3837c?;2;38?l41290/=9=5299m514=:21b>84?:%377?4?3g;?>7=4;h07>5<#9=91>55a15090>=n::0;6)?;3;0;?k73:3?07d<=:18'515=:11e=9<56:9j64<72-;??7<7;o376?1<3k:1<7=51;1xH43f28qC9?5rL07a>0}#90;1=5l4$0:g>76<,82m6<::;%3;a?203g;3o7?4}%361?303`8;6=44o066>5<<a==1<75m0;297?6=8r.:984:3:J21==n:90;66g;4;29?j73=3:17p}=0;296~X5827;6?>4}r371?6=:rT:88520;371>{t<>0;6?uQ469>4?233twi=7>53;397~J6=h0:wE;=;|N21g<2s-;2=7?7b:&2<a<582.:4k4>449'5=c=<>1e=5m51:'503==>1b>=4?::m200<722c?;7>5;c294?5=83:p(<;::418L43?3`8;6=44i5694?=h9=?1<75rs3294?4|V;:01=4=0:p513=838pR<::;<29513<uz><6=4={_64?86=<=1vqo<50;195?5|D8?j6<uG539~H43e2<q/=4?519`8 4>c2;:0(<6i:066?!7?m3><7c?7c;38y!72=3?<7d<?:188k4222900e9950;9a4?6=;3:1<v*>54867>N6=11b>=4?::k70?6=3f;?97>5;|q14?6=:rT9<63?:328yv73=3:1>vP>449>4?73=2wx8:4?:3y]02=:83>?7psm3;297?7=;rF:9l4>{I71?xJ6=k0>w)?61;3;f>"60m09<6*>8g8200=#91o18:5a19a95>{#9<?19:5f2183>>i6<<0;66g;7;29?g6=8391<7>t$076>05<@8?37d<?:188m12=831d=9;50;9~w76=838pR?>4=1814>{t9=?1<7<t^066?86=9=?0q~:8:181[2034:1895r}c794?5=939p@<;n:0yK17=zD8?i68u+18395=d<,82o6?>4$0:e>4223-;3i7:8;o3;g?7<u-;>97;8;h03>5<<g8>>6=44i5594?=e83:1?7>50z&210<2;2B:955f2183>>o3<3:17b?;5;29?xu583:1>vP=0:?3>76<uz;?97>52z\200=:83;?96s|4683>7}Y<>16<7:;;|a2?6=;3;1?vB>5`82M353tF:9o4:{%3:5?7?j2.:4i4=0:&2<c<6<<1/=5k5469m5=e=92w/=8;5569j65<722e:884?::k73?6=3k:1<7=50;2x 4322<90D<;7;h03>5<<a=>1<75`15794?=z{;:1<7<t^32895<582wx=9;50;0xZ42234:1=9;4}r64>5<5sW><70>5459~yg1=8391=7=tL07b>4}O=;1v@<;m:4y'5<7=91h0(<6k:328 4>a28>>7)?7e;64?k7?k3;0q)?:5;74?l472900c<:::188m11=831i<7>53;294~"6=<0>?6F>599j65<722c?87>5;n371?6=3ty9<7>52z\14>;72;:0q~?;5;296~X6<<16<7?;5:p02<72;qU8:520;67?x{e03:1?7?53zN21d<6sA?97pB>5c86!7>93;3n6*>8e814>"60o0:885+19g902=i91i1=6s+147912=n:90;66a>4483>>o3?3:17o>50;194?6|,8?>68=4H07;?l472900e9:50;9l513=831v?>50;0xZ76<5909<6s|15794?4|V8>>70>51578yv202909wS:8;<2901=zuz><6=46{_64?86=<>16=7:8;<0902=:;3><70;5469>2?2034=18:528;64?xu6<l0;6?uQ15g89=<6<<1/=8=515f8j435291v<:l:181[73k27<6<::;%367?73l2d:9?4>;|q20g<72;qU=9l4=78200=#9<91=9j4n071>7=z{8>j6=4={_37e>;228>>7)?:3;37`>h6=;087p}>4883>7}Y9=301>4>449'505=9=n0b<;=:59~w42?2909wS?;8:?1>4223-;>?7?;d:l217<23ty:8:4?:3y]511<580:885+141951b<f8?96;5rs065>5<5sW;?:63?:066?!72;3;?h6`>5384?xu513:1>vP=9:?;>76<,8?86?64n071>5=z{;=1<7<t^35892<582.:9>4=8:l217<63ty9:7>52z\12>;12;:0(<;<:3:8j4352;1v?;50;0xZ73<5<09<6*>5281<>h6=;087p}=4;296~X5<2786?>4$070>7><f8?9695rs3194?4|V;901?4=0:&216<502d:9?4:;|q16?6=:rT9>63>:328 4342;20b<;=:79~w77=838pR??4=1814>"6=:0946`>5384?x{e=00;6>4>:2yO50g=9rB>>6sC14`93~h61<0>o6*>9082<g=#91n1>=5+19d9513<,82n6994n0:`>4=#90>1>l5r$076>01<a;:1<75`15794?=n<>0;66l?:180>5<7s-;>97;<;I36<>o583:17d:;:188k4222900q~<?:181[4734:1>=5rs066>5<5sW;?963?:066?xu3?3:1>vP;7:?3>12<uth>m7>54;390~J6=h0:wE;=;|N21g<0sg;297;l;%3:5?7?j2.:4i4=0:&2<c<6<<1/=5k5469m5=e=92.:594=a:'503==11b>=4?::m200<722c?47>5;h64>5<<j90;694?:1y'503===1C=864i3294?=n<=0;66g;5;29?j73=3:17p}=0;296~X5827;6?>4}r371?6=:rT:88520;371>{t<10;6?uQ499>4?223ty?;7>52z\73>;72=>0qpl:d;290?7=<rF:9l4>{I71?xJ6=k0<wc?65;7`?!7>93;3n6*>8e814>"60o0:885+19g902=i91i1=6*>9581e>{#9<?1955f2183>>i6<<0;66g;8;29?l202900n=4?:583>5}#9<?1995G14:8m76=831b894?::k71?6=3f;?97>5;|q14?6=:rT9<63?:328yv73=3:1>vP>449>4?73=2wx854?:3y]0==:83>>7p};7;296~X3?27;69:4}|`52?6=<3;18vB>5`82M353tF:9o48{o3:1?3d3-;2=7?7b:&2<a<582.:4k4>449'5=c=<>1e=5m51:&2=1<5i2w/=8;5599j65<722e:884?::k7<?6=3`><6=44b183>1<729q/=8;5559K50><a;:1<75f4583>>o3=3:17b?;5;29?xu583:1>vP=0:?3>76<uz;?97>52z\200=:83;?96s|4983>7}Y<116<7::;|q73?6=:rT?;63?:568yxd093:187?54zN21d<6sA?97pB>5c84k7>=3?h7)?61;3;f>"60m09<6*>8g8200=#91o18:5a19a95>"61=09m6s+14791==n:90;66a>4483>>o303:17d:8:188f5<72=0;6=u+147911=O9<20e?>50;9j01<722c?97>5;n371?6=3ty9<7>52z\14>;72;:0q~?;5;296~X6<<16<7?;5:p0=<72;qU85520;66?xu3?3:1>vP;7:?3>12<uth3<7>54;390~J6=h0:wE;=;|N21g<0sg;297;l;%3:5?7?j2.:4i4=0:&2<c<6<<1/=5k5469m5=e=92.:594=a:'503==11b>=4?::m200<722c?47>5;h64>5<<j90;694?:1y'503===1C=864i3294?=n<=0;66g;5;29?j73=3:17p}=0;296~X5827;6?>4}r371?6=:rT:88520;371>{t<10;6?uQ499>4?223ty?;7>52z\73>;72=>0qpl64;290?7=<rF:9l4>{I71?xJ6=k0<wc?65;7`?!7>93;3n6*>8e814>"60o0:885+19g902=i91i1=6*>9581e>{#9<?1955f2183>>i6<<0;66g;8;29?l202900n=4?:583>5}#9<?1995G14:8m76=831b894?::k71?6=3f;?97>5;|q14?6=:rT9<63?:328yv73=3:1>vP>449>4?73=2wx854?:3y]0==:83>>7p};7;296~X3?27;69:4}|`bg?6=<3;18vB>5`82M353tF:9o48{o3:1?3d3-;2=7?7b:&2<a<582.:4k4>449'5=c=<>1e=5m51:&2=1<5i2w/=8;5599j65<722e:884?::k7<?6=3`><6=44b183>1<729q/=8;5559K50><a;:1<75f4583>>o3=3:17b?;5;29?xu583:1>vP=0:?3>76<uz;?97>52z\200=:83;?96s|4983>7}Y<116<7::;|q73?6=:rT?;63?:568yxdd03:1?7?53zN21d<6sA?97pB>5c84k7>=3?h7)?61;3;f>"60m09<6*>8g8200=#91o18:5a19a95>"61=09m6s+147912=n:90;66a>4483>>o3?3:17o>50;194?6|,8?>68=4H07;?l472900e9:50;9l513=831v?>50;0xZ76<5909<6s|15794?4|V8>>70>51578yv202909wS:8;<2901=zukio6=4<:080I72i3;pD8<4}M36f?1|f83>68m4$0;2>4>e3-;3h7<?;%3;b?73=2.:4h4;7:l2<f<63-;287<n;|&210<2?2c9<7>5;n371?6=3`><6=44b183>6<729q/=8;5529K50><a;:1<75f4583>>i6<<0;66s|2183>7}Y:916<7<?;|q200<72;qU=9;4=18200=z{==1<7<t^55895<3<2wvni:50;195?5|D8?j6<uG539~H43e2>qe=4;55b9'5<7=91h0(<6k:328 4>a28>>7)?7e;64?k7?k3;0(<7;:3c8y!72=3?<7d<?:188k4222900e9950;9a4?6=;3:1<v*>54867>N6=11b>=4?::k70?6=3f;?97>5;|q14?6=:rT9<63?:328yv73=3:1>vP>449>4?73=2wx8:4?:3y]02=:83>?7psmde83>6<62:qG=8o51zJ66>{K9<h1;v`>9486g>"6180:4o5+19f965=#91l1=9;4$0:f>11<f82h6<5+18696d=z,8?>6894i3294?=h9=?1<75f4683>>d729086=4?{%361?343A;>46g=0;29?l232900c<:::188yv472909wS<?;<2965=z{8>>6=4={_371>;728>>7p};7;296~X3?27;69:4}|`f<?6=;3;1?vB>5`82M353tF:9o48{o3:1?3d3-;2=7?7b:&2<a<582.:4k4>449'5=c=<>1e=5m51:&2=1<5i2w/=8;5569j65<722e:884?::k73?6=3k:1<7=50;2x 4322<90D<;7;h03>5<<a=>1<75`15794?=z{;:1<7<t^32895<582wx=9;50;0xZ42234:1=9;4}r64>5<5sW><70>5459~yg`229086<4<{M36e?7|@<80qA?:b;5xj4?22<i0(<7>:0:a?!7?l38;7)?7f;371>"60l0?;6`>8b82?!7><38j7p*>54863>o583:17b?;5;29?l202900n=4?:283>5}#9<?19>5G14:8m76=831b894?::m200<722wx>=4?:3y]65=:838;7p}>4483>7}Y9=?01=4>449~w11=838pR994=1870>{zj8:?6=4<:080I72i3;pD8<4}M36f?1|f83>68m4$0;2>4>e3-;3h7<?;%3;b?73=2.:4h4;7:l2<f<63-;287<n;|&210<2?2c9<7>5;n371?6=3`><6=44b183>6<729q/=8;5529K50><a;:1<75f4583>>i6<<0;66s|2183>7}Y:916<7<?;|q200<72;qU=9;4=18200=z{==1<7<t^55895<3<2wvn<?::180>4<4sE;>m7?tH408yI72j3=pb<7::4a8 4?6282i7)?7d;03?!7?n3;?96*>8d873>h60j0:7)?64;0b?x"6=<0>;6g=0;29?j73=3:17d:8:188f5<72:0;6=u+147916=O9<20e?>50;9j01<722e:884?::p65<72;qU>=520;03?xu6<<0;6?uQ157895<6<<1v9950;0xZ11<590?86srb045>5<4290;w)?:5;3;?M7202c?57>5;h360?6=3f;8>7>5;|`2=3<72=0;6=u+14796g=O9<20@<;m:3y'5<2=:h1e=4;51d9~m4g=831b=o4?::k14?6=3f;?97>5;|`221<72:0;6=u+14795==O9<20e9750;9j502=831d=><50;9~f40?29086=4?{%361?7?3A;>46g;9;29?l72<3:17b?<2;29?xd6>h0;6>4?:1y'503=911C=864i5;94?=n9<>1<75`12094?=zj8<h6=4<:183!72=3;37E?:8:k7=?6=3`;>87>5;n306?6=3th::h4?:283>5}#9<?1=55G14:8m1?=831b=8:50;9l564=831vn<9?:180>5<7s-;>97?7;I36<>o313:17d?:4;29?j74:3:17pl>7283>6<729q/=8;5199K50><a=31<75f14694?=h9:81<75rb0;`>5<32:0=w)?:5;3:g>i61>0;66g>8`83>>o61;0;66g>9783>>d61k0;6>4?:1y'503=991C=864i5c94?=n<k0;66a>3383>>{e9031<7=50;2x 432289>7E?:8:k7e?6=3`>i6=44o011>5<<uk;2m7>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3ty:5:4?:3y]5<1<583j6<==;|q2<d<72;qU=5o4=0;b>1g<uz;2>7>53z\2=7=:90h18l5218;90d=z{83=6=4={_3:2>;61k0?n6s|18:94?4|583i6<==;<3:=?2e3ty:>54?:3y>5<?=9:801<7n:5`8yxd1;3:187=56z&210<1;2e>i7>5;h343?6=3`;2>7>5;h7g>5<<j?81<7=50;2x 43228:0D<;7;h6b>5<<a=h1<75`12094?=zj?:1<7=50;2x 43228;0D<;7;h6b>5<<a=h1<75`12094?=zj?;1<7=50;2x 432289?7E?:8:k7e?6=3`>i6=44o011>5<<uz?n6=4={_7f?80628997p}>7683>6}Y9>=01;<54`9>25<3i2wx=4<50;0xZ4?534<969l4}r7g>5<5sW?o708?:5`8yv3a2909w08=:011?8062=k0q~8?:1818072899708>:5`8yxd083:19785az&210<082e=;7>5;h343?6=3`<=6=44i05;>5<<a8396=44b7d94?5=83:p(<;::028L43?3`>j6=44i5`94?=h9:81<75rb7;94?5=83:p(<;::028L43?3`>j6=44i5`94?=h9:81<75rb7`94?5=83:p(<;::038L43?3`>j6=44i5`94?=h9:81<75rb7a94?5=83:p(<;::017?M7202c?m7>5;h6a>5<<g8996=44}c4g>5<4290;w)?:5;32?M7202c?m7>5;h6a>5<<g8996=44}c4f>5<4290;w)?:5;300>N6=11b8l4?::k7f?6=3f;8>7>5;|q53?6=:rT=;639e;306>{t9>=1<7=t^054?80a2=k01;j54`9~w30=839pR;84=7d90g=:>k0?n6s|16:94?5|V8=37086:5c893d=<h1v<7=:181[7>:27=57:m;|q5<?6=:r7=j7?<2:?5a?2f3ty=57>52z?5=?74:27=o7:n;|q5e?6=:r7=n7?<2:?5g?2e3ty:>54?:3y>2f<6;;16:i4;b:p57?=838p1;j5120893c=<k1vqo9i:185><<bs-;>979i;n51>5<<a8=<6=44i6394?=n9>21<75f16;94?=n9081<75m7d83>6<729q/=8;5119K50><a=k1<75f4c83>>i6;;0;66sm7583>6<729q/=8;5119K50><a=k1<75f4c83>>i6;;0;66sm7783>6<729q/=8;5119K50><a=k1<75f4c83>>i6;;0;66sm7983>6<729q/=8;5109K50><a=k1<75f4c83>>i6;;0;66sm7883>6<729q/=8;51268L43?3`>j6=44i5`94?=h9:81<75rb6c94?5=83:p(<;::038L43?3`>j6=44i5`94?=h9:81<75rb6`94?5=83:p(<;::017?M7202c?m7>5;h6a>5<<g8996=44}c5`>5<4290;w)?:5;32?M7202c?m7>5;h6a>5<<g8996=44}c5g>5<4290;w)?:5;300>N6=11b8l4?::k7f?6=3f;8>7>5;|q46?6=:rT<>638d;306>{t9>=1<7=t^054?81b2=k01:m54`9~w27=83>pR:?4=6g90g=:?=0?n6388;6a?xu6?10;6>uQ16:8922=<h16;l4;a:p52?=839pR<96;<55>1g<5>218l5rs0;1>5<5sW;2>6386;6a?xu0;3:1>v38e;306>;0l3>j7p}84;296~;0<3;8>638b;6b?xu0=3:1>v386;306>;013>j7p}87;296~;003;8>6389;6a?xu6:10;6?u2788277=:?h0?n6s|13;94?4|5>k1=><4=6`90g=z{88j6=4={<5a>45534=h69l4}r31f?6=:r7<o7?<2:?4`?2e3twi5>4?:68`>44|,8?>64=4o9394?=n9>=1<75f8183>>o6?10;66g>7883>>o6?h0;66g>9383>>d?>3:1?7>50z&210<682B:955f4`83>>o3j3:17b?<2;29?xd??3:1?7>50z&210<682B:955f4`83>>o3j3:17b?<2;29?xd?13:1?7>50z&210<682B:955f4`83>>o3j3:17b?<2;29?xd?j3:1?7>50z&210<682B:955f4`83>>o3j3:17b?<2;29?xd?l3:1?7>50z&210<692B:955f4`83>>o3j3:17b?<2;29?xd?m3:1?7>50z&210<6;=1C=864i5c94?=n<k0;66a>3383>>{e0o0;6>4?:1y'503=981C=864i5c94?=n<k0;66a>3383>>{e190;6>4?:1y'503=9:>0D<;7;h6b>5<<a=h1<75`12094?=zj0;1<7=50;2x 43228;0D<;7;h6b>5<<a=h1<75`12094?=zj081<7=50;2x 432289?7E?:8:k7e?6=3`>i6=44o011>5<<uk286=4<:183!72=3;:7E?:8:k7e?6=3`>i6=44o011>5<<uk2>6=4<:183!72=3;886F>599j0d<722c?n7>5;n306?6=3ty3=7>52z\;5>;?=3;8>6s|16594?5|V8=<7069:5c89=5=<h1v5>50;7xZ=6<51<18o528687f>;?13>i706k:5`8yv7003:1?vP>799><2<3i272=7:n;|q23<<72:qU=:74=9;90d=:0o0?m6s|16c94?5|V8=j706m:5c89=b=<h1v<7=:181[7>:273n7:m;|q;6?6=:r73:7?<2:?;1?2f3ty387>52z?;3?74:272>7:n;|q;<?6=:r7357?<2:?:4?2f3ty3m7>52z?;f?74:273i7:n;|q;g?6=:r73h7?<2:?;a?2e3ty:>54?:3y><`<6;;164k4;b:p57?=838p15h512089<6=<k1v<<n:1818?72899707>:5`8yv75j3:1>v361;306>;>:3>i7p}>2b83>7}:1;0:??528287f>{t9;n1<7<t=919564<51?18o5r}cca>5<?2o0::v*>548bf>i>=3:17d?87;29?l?32900e<97:188m41>2900e<9n:188m41e2900e<7=:188f<b=8391<7>t$076>46<@8?37d:n:188m1d=831d=><50;9~f<c=8391<7>t$076>46<@8?37d:n:188m1d=831d=><50;9~fd6=8391<7>t$076>46<@8?37d:n:188m1d=831d=><50;9~fd4=8391<7>t$076>46<@8?37d:n:188m1d=831d=><50;9~fd2=8391<7>t$076>46<@8?37d:n:188m1d=831d=><50;9~fd0=8391<7>t$076>47<@8?37d:n:188m1d=831d=><50;9~fd1=8391<7>t$076>4533A;>46g;a;29?l2e2900c<==:188ygg?29086=4?{%361?763A;>46g;a;29?l2e2900c<==:188ygg>29086=4?{%361?74<2B:955f4`83>>o3j3:17b?<2;29?xdfi3:1?7>50z&210<692B:955f4`83>>o3j3:17b?<2;29?xd>?3:1?7>50z&210<6;=1C=864i5c94?=n<k0;66a>3383>>{e100;6>4?:1y'503=981C=864i5c94?=n<k0;66a>3383>>{e1h0;6>4?:1y'503=9:>0D<;7;h6b>5<<a=h1<75`12094?=zj0h1<7=50;2x 43228;0D<;7;h6b>5<<a=h1<75`12094?=zj0i1<7=50;2x 432289?7E?:8:k7e?6=3`>i6=44o011>5<<uz3>6=4={_;6?8?d28997p}>7683>6}Y9>=014j54`9>=g<3i2wx594?:7y]=1=:1m0?n636e;6a?8g72=h01l<54c9>e3<3j2wx=:650;1xZ41?343n69o4=8;90d=z{8=26=4<{_34=>;f83>j70on:5c8yv70i3:1?vP>7`9>e7<3i27j47:n;|q23g<72:qU=:l4=`690d=:i?0?m6s|18094?4|V83970o;:5`8yv?12909w07k:011?8?d2=k0q~77:1818?b2899707n:5c8yv?a2909w0o?:011?8?02=k0q~o>:1818g5289970o6:5c8yvg42909w0o;:011?8g02=k0q~o::1818g1289970o8:5`8yv7503:1>v3n7;306>;f03>i7p}>2883>7}:i10:??52a887f>{t9;k1<7<t=`;9564<5hk18o5rs00a>5<5s4kj6<==;<;4>1d<uz;9o7>52z?:3?74:27257:m;|q26a<72;q6544>339>=d<3j2wx=?k50;0x9<g=9:8014l54c9~w44a2909w07m:011?8?d2=h0qpll7;29=?7528kp(<;::b58kdb=831b=:950;9jef<722c:;54?::k23<<722c:;l4?::k23g<722c:;n4?::k2=7<722hi47>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3thi57>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3thin7>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3thih7>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3thij7>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3thh=7>53;294~"6=<0:<6F>599j0d<722c?n7>5;n306?6=3thh?7>53;294~"6=<0:=6F>599j0d<722c?n7>5;n306?6=3thh87>53;294~"6=<0:?95G14:8m1g=831b8o4?::m277<722wio84?:283>5}#9<?1=<5G14:8m1g=831b8o4?::m277<722wio;4?:283>5}#9<?1=>:4H07;?l2f2900e9l50;9l564=831vnlh50;194?6|,8?>6<?4H07;?l2f2900e9l50;9l564=831vno?50;194?6|,8?>6<=;;I36<>o3i3:17d:m:188k4552900qol=:180>5<7s-;>97?>;I36<>o3i3:17d:m:188k4552900qol<:180>5<7s-;>97?<4:J21==n<h0;66g;b;29?j74:3:17plm4;297?6=8r.:984>1:J21==n<h0;66g;b;29?j74:3:17plm5;297?6=8r.:984>359K50><a=k1<75f4c83>>i6;;0;66smb783>6<729q/=8;5109K50><a=k1<75f4c83>>i6;;0;66smb683>6<729q/=8;51268L43?3`>j6=44i5`94?=h9:81<75rs`f94?4|Vhn01o951208yv70?3:1?vP>769>f=<3i27i:7:n;|qbg?6=?rTjo63m8;6a?8d>2=h01ol54c9>fa<3j27ij7:m;<a0>1d<uz;<47>53z\23==:j00?m63m4;6b?xu6?00;6>uQ16;89gd=<h16n?4;a:p52g=839pR<9n;<`g>1g<5hl18l5rs05a>5<4sW;<n63mf;6b?8e22=k0q~?8c;297~X6?j16o<4;a:?`7?2f3ty:5?4?:3y]5<4<5j;18o5rs`g94?4|5k21=><4=c590d=z{k:1<7<t=c;9564<5k?18l5rscc94?4|5kh1=><4=c190d=z{ki1<7<t=cf9564<5k;18l5rscg94?4|5kl1=><4=b490d=z{j:1<7<t=b39564<5j>18l5rsb094?4|5j91=><4=b690g=z{8836=4={<a7>45534i>69l4}r31=?6=:r7h97?<2:?`2?2e3ty:>l4?:3y>g3<6;;16mk4;b:p57d=838p1lh512089g7=<k1v<<l:1818d6289970l=:5`8yv75l3:1>v3m2;306>;e;3>i7p}>2d83>7}:j:0:??52b587f>{t9;l1<7<t=c69564<5k?18o5rs013>5<5s4h>6<==;<`5>1d<uz;8=7>52z?a2?74:27i;7:m;|agd<72:0;6=u+147957=O9<20e9o50;9j0g<722e:??4?::a`6<72:0;6=u+1479563<@8?37d:n:188m1d=831d=><50;9~ff`=8391<7>t$076>47<@8?37d:n:188m1d=831d=><50;9~fag=8391<7>t$076>4523A;>46g;a;29?l2e2900c<==:188ygbd29086=4?{%361?74<2B:955f4`83>>o3j3:17b?<2;29?xdc>3:1?7>50z&210<692B:955f4`83>>o3j3:17b?<2;29?xdb;3:1?7>50z&210<6;<1C=864i5c94?=n<k0;66a>3383>>{em<0;6>4?:1y'503=9:>0D<;7;h6b>5<<a=h1<75`12094?=zjl=1<7=50;2x 432289?7E?:8:k7e?6=3`>i6=44o011>5<<uknm6=4<:183!72=3;:7E?:8:k7e?6=3`>i6=44o011>5<<ukon6=4<:183!72=3;896F>599j0d<722c?n7>5;n306?6=3thm<7>53;294~"6=<0:?95G14:8m1g=831b8o4?::m277<722wij?4?:283>5}#9<?1=>:4H07;?l2f2900e9l50;9l564=831vnk:50;194?6|,8?>6<=;;I36<>o3i3:17d:m:188k4552900qokn:180>5<7s-;>97?>;I36<>o3i3:17d:m:188k4552900qohm:180>5<7s-;>97?<5:J21==n<h0;66g;b;29?j74:3:17plid;297?6=8r.:984>359K50><a=k1<75f4c83>>i6;;0;66smfg83>6<729q/=8;51268L43?3`>j6=44i5`94?=h9:81<75rb022>5<4290;w)?:5;300>N6=11b8l4?::k7f?6=3f;8>7>5;|`246<72:0;6=u+1479562<@8?37d:n:188m1d=831d=><50;9~fc1=8391<7>t$076>47<@8?37d:n:188m1d=831d=><50;9~f46f29086=4?{%361?74=2B:955f4`83>>o3j3:17b?<2;29?xd68j0;6>4?:1y'503=9:>0D<;7;h6b>5<<a=h1<75`12094?=zj8:n6=4<:183!72=3;886F>599j0d<722c?n7>5;n306?6=3th:==4?:283>5}#9<?1=>:4H07;?l2f2900e9l50;9l564=831vn<?=:180>5<7s-;>97?<4:J21==n<h0;66g;b;29?j74:3:17pl>1583>6<729q/=8;51268L43?3`>j6=44i5`94?=h9:81<75rb025>5<4290;w)?:5;32?M7202c?m7>5;h6a>5<<g8996=44}c32f?6=;3:1<v*>548270=O9<20e9o50;9j0g<722e:??4?::a54b=8391<7>t$076>4533A;>46g;a;29?l2e2900c<==:188yg76n3:1?7>50z&210<6;=1C=864i5c94?=n<k0;66a>3383>>{e9;;1<7=50;2x 432289?7E?:8:k7e?6=3`>i6=44o011>5<<uk;9?7>53;294~"6=<0:?95G14:8m1g=831b8o4?::m277<722wi=?;50;194?6|,8?>6<=;;I36<>o3i3:17d:m:188k4552900qo?=7;297?6=8r.:984>359K50><a=k1<75f4c83>>i6;;0;66sm10594?5=83:p(<;::038L43?3`>j6=44i5`94?=h9:81<75rb4a94?4=83:p(<;::5g8L43?3`>26=44o011>5<<uk<>6=4=:183!72=3>n7E?:8:k7=?6=3f;8>7>5;|``g?6=:3:1<v*>5487a>N6=11b844?::m277<722wih<4?:383>5}#9<?18h5G14:8m1?=831d=><50;9~fa>=8381<7>t$076>1c<@8?37d:6:188k4552900qok>:181>5<7s-;>97:j;I36<>o313:17b?<2;29?xdbk3:1>7>50z&210<3m2B:955f4883>>i6;;0;66smf883>7<729q/=8;54d9K50><a=31<75`12094?=zj8:36=4=:183!72=3>n7E?:8:k7=?6=3f;8>7>5;|`25<<72;0;6=u+14790`=O9<20e9750;9l564=831v<8>:181[71927:;94>e:p5<6=839pR<7?;<3;=?72827:5;4>b:p5=>=83>pR<67;<340?74>27:444:1:?23`<3?2wx=4<50;`xZ4?534;357;?;<7:>76<5<k1>=5218a95<4<5?91=4<4=6295<4<5>l1=4<4=8195<4<5hh1=4<4=b595<4<uz;=>7>53z\227=:9131=h5218495d=z{jo1<7<t=bd9564<5m;1845rs4g94?4|5<n1>=526286a>{t=k0;65u25`87<>;2l3>37089:5:8927=<1164=4;8:?:0?2?34kh6964=4a9564<uzi36=4={<a;>42234;=87?:4:p523=83hp1<9;:014?83>2==01no54c9>`6<3j27oo7:n;<g4>1g<5o>18l5211190d=:98>18l5213590d=:=j0?56s|16494?g|58=?6<=7;<7b>11<5m918l52d`87f>;b=3>j70h=:5c894662=k01<?=:5c894422=k01;;5489~wfb=838p1nj51578940128??7p}>0483>7}:99<1=><4=02;>1?<uz;<;7>5dz?231<6;016:>4>769>35<6?>16;k4>769>=6<6?>16mo4>769>g2<6?>16hl4;a:?f7?2e34l;69o4=gd90d=:98:18l5213190d=z{8=36=4m{<340?74j27<<7?88:?4b?700272?7?88:?bf?70027h;7?88:?f7?2f34on69l4=gf90d=:99o18l5213390d=z{8=26=46{<340?74k27<j7?89:?:7?70127jn7?89:?`3?70127ni7:n;<da>1d<58:h69o4=03e>1g<uzko6=4={<c`>76<5j=1mi5rs05b>5<0s4;<87?<d:?:7?70i27jn7?8a:?`3?70i27mn7:n;<33e?2e34;:h7:n;|qf4?6=:r7oh7:8;<g2>4553ty:;o4?:4y>522=9:o01ll516`89f1=9>h01<>n:5c8947e2=h0q~j;:1818b328>>70?98;360>{t9>i1<7=t=057>45a34i<6<9l;<32f?2f3ty:;i4?:03x941328>;70m7:3289fb=:916h94=0:?g`?4734o36?>4=g7965=:99>1>=52107965=:kh0?m63lf;6b?8b12=k01ih54`9>ad<3i27m;7:n;<332?2f34;:;7:n;|q2=2<72;q6=485219>5<e=90=0q~?>a;296~;69k0:??5210f90g=z{mn1<7<t=ef9513<58<j6<;;;|q25f<72;q6=<j51208947a2=h0q~?>e;296~;69o0:??5213390g=z{88;6=4={<315?74:27:>>4;b:p574=838p1<<<:011?875=3>i7p}>2583>7}:9;?1=><4=004>1d<uzo36=4={<g;>42234;=o7?:4:p570=838p1<<8:011?876?3>i7p}>0883>7}:99k1=><4=02`>1d<uzi26=4={<ab>45534ih6974}r33f?6=:r7:<n4>339>55c=<k1v<>k:181877m3;8>63>1187f>{t99l1<7<t=033>45534;:>7:m;|qe1?6=:r7m97?;5:?22`<6==1v<?>:181876:3;8>63>1587f>{t9891<7<t=037>45534;;:7:m;|qee?6=:r7mn7?<2:?e`?2e3tymo7>52z?e`?74:27mj7:m;|q241<72;q6==:51578941728??7p}ie;296~;an3;8>63>0087f>{t99:1<7<t=022>45534;;?7:m;|q247<72;q6===512089c1=<k1v<?::181876=3;?963>728211=z{ln1<7<t=dg9564<5o:18o5rsdd94?4|5o:1=><4=g090g=z{o;1<7<t=g09564<5o>18o5rsg194?4|5o>1=><4=dc90g=z{o<1<7<t=g59564<5o31845rs8794?4|50>1>=52ac8:1>{tm;0;6?u2e28277=:m<0?n6s|e583>7}:m<0:??52e687f>{tl>0;6?u2d5873>;c03;8>6s|e783>7}:m>0:??52dg87f>{tl00;6?u2d`8277=:lj0?n6s|dc83>7}:lj0:??52d787f>{tl;0;6?u2d28277=:ko0?n6s|10:94?4|58;>6994=03:>4553tyn57>52z?fe?74:27no7:6;|q;5?6=:r73<7<?;<;0>=7<uzn;6=4={<ag>11<5m;1=><4}r7:>5<5s4?26<::;<350?2>3E;>m7?t$5d952=zuz?j6=4={<7b>42234;=:7:6;M36e?7|,=l1=:5r}r333?6=:r7:<94;7:?24=<6;;1v8j50;1x90b=9=?01<87:5;8935==m1G=8o51z&7b?703twx:;4?:2y>23<6<<16=;o5489>35<1>2F:9l4>{%6e>41<uty<=7>53z?45?73=27::n4;9:?4b?163E;>m7?t$5d952=zuznn6=4={<fe>45534o:6974}r51>5<5s4=:6?>4=6d937=z{1:1<7=t=929513<58<n6974=819<5=K9<k1=v*;f;34?x{tkk0;6?u2c9873>;dk3;8>6s|9583>6}:1=0:885216290<=:ik0286B>5`82!2a28=0qp}nc;297~;fk3;?963>7287=>;d?3kh7A?:a;3x 1`=9>1vq~h7:1818`22==01k751208yvb22909w0j9:011?8b?2=30q~88:1818012;:01:>5669~w4>f2909w0?79;30=>;61j0:4l5rs0;5>5<4s4;<87?:0:?2=3<6<<16=4m51848yv03290<w0;k:558930=<>16;<4;7:?;4?20343?6994=`a902=:><0:??5rs035>5<5s4;:;7?<2:?25<<312wxio4?:3y>a=<3?27no7?<2:p5=1=838pR<68;<34a?73m2.:9>4>879m504=82wx=5;50;0xZ4>234;<i7?;c:&216<60?1e=8<51:p5=2=838pR<6;;<34a?73j2.:9>4>879m504=:2wx=5=50;0xZ4>434;<i7?;a:&216<60?1e=8<53:p5=4=838pR<6=;<34a?7312.:9>4>879m504=<2wx=5?50;0xZ4>634;<i7?;8:&216<60?1e=8<55:p5=6=838pR<6?;<34a?73?2.:9>4>879m504=>2wx=:h50;0xZ41a34;<i7?;6:&216<60?1e=8<57:p524=838p1<9j:3;8941428997)?:3;345>h6=;0;7p}>6g83>7}:9>o1>:521629564<,8?86<9>;o366?7<uz;=h7>52z?23`<5>27::h4>339'505=9>;0b<;=:39~w40e2909w0?8e;06?871k3;8>6*>528234=i9<81?6s|17;94?4|58=n6?:4=04b>4553-;>?7?81:l217<33ty:::4?:3y>52c=::16=;651208 43428=:7c?:2;78yv71=3:1>v3>7d816>;6>?0:??5+1419527<f8?96;5rs040>5<5s4;<i7<>;<350?74:2.:9>4>709m504=?2wvqpsO@By67g<dl<?<95sO@Cy3yEFWstJK
/iseProject/serial_transmitter_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/21/2012 - 12:13:10)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/21/2012 - 14:22:41)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>iseProject.xise</TD>
105,9 → 105,9
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
 
 
</TABLE>
 
 
<br><center><b>Date Generated:</b> 04/21/2012 - 12:42:35</center>
<br><center><b>Date Generated:</b> 04/21/2012 - 14:22:41</center>
</BODY></HTML>
/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testSerial_receiver.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/serial_receiver.vhd&quot; into library work</arg>
</msg>
 
</messages>
/iseProject/_xmsgs/xst.xmsgs
5,36 → 5,89
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/serial_receiver.vhd</arg>&quot; line <arg fmt="%d" index="2">76</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/serial_receiver.vhd</arg>&quot; line <arg fmt="%d" index="2">86</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;serial_in&gt;</arg>
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_0</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_1</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_2</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_3</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_4</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_5</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_6</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte_7</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;7&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;7&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2042" delta="new" >Unit <arg fmt="%s" index="1">serial_receiver</arg>: <arg fmt="%d" index="2">8</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
 
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
</messages>
 
/iseProject/serial_receiver.cmd_log
8,3 → 8,7
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
xst -intstyle ise -ifn "E:/uart_block/hdl/iseProject/serial_receiver.xst" -ofn "E:/uart_block/hdl/iseProject/serial_receiver.syr"
/iseProject/xst/work/hdpdeps.ref
1,19 → 1,19
V3 9
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.12:02:35 O.87xd
PH work/pkgDefinitions 1335003186 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd
PH work/pkgDefinitions 1335010957 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335003187 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1335003186
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.12:13:03 O.87xd
EN work/serial_receiver 1335003188 \
PB work/pkgDefinitions 1335010958 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1335010957
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd
EN work/serial_receiver 1335010959 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1335003187
AR work/serial_receiver/Behavioral 1335003189 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1335003188
PB work/pkgDefinitions 1335010958
AR work/serial_receiver/Behavioral 1335010960 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1335010959
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1335001307 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335003187
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335010958
AR work/serial_transmitter/Behavioral 1335001308 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335001307
/iseProject/xst/work/hdllib.ref
1,6 → 1,6
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335003187
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335003188
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335010958
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335010959
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335001308
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335001307
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335003186
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335003189
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335010957
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335010960
/iseProject/xst/work/sub00/vhpl00.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iseProject/xst/work/sub00/vhpl01.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iseProject/xst/work/sub00/vhpl04.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iseProject/xst/work/sub00/vhpl05.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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