OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block/trunk/hdl
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/iseProject/isim.log
1,19 → 1,20
ISim log file
Running: E:\uart_block\hdl\iseProject\testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb
ISim O.87xd (signature 0xc3576ebc)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim log file
Running: /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 us
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testBaud_generator.vhd:stim_proc
INFO: Simulator is stopped.
# exit 0
/iseProject/serial_receiver_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/21/2012 - 14:22:41)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>serial_receiver Project Status (04/27/2012 - 15:05:36)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>iseProject.xise</TD>
19,13 → 19,12
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s500e-4fg320</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='E:/uart_block/hdl/iseProject\_xmsgs/*.xmsgs?&DataKey=Warning'>19 Warnings (18 new)</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
43,7 → 42,7
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='E:/uart_block/hdl/iseProject\serial_receiver_envsettings.html'>
<A HREF_DISABLED='/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
94,10 → 93,11
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Apr 23 13:47:40 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
105,9 → 105,9
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
 
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/laraujo/work/uart_block/hdl/iseProject/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Apr 27 15:14:48 2012</TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 04/21/2012 - 14:22:41</center>
<br><center><b>Date Generated:</b> 04/27/2012 - 15:15:20</center>
</BODY></HTML>
/iseProject/fuseRelaunch.cmd
1,9 → 105,9
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver"
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj" "work.testBaud_generator"
/iseProject/iseProject.gise
23,6 → 23,18
 
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="baud_generator.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="baud_generator.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="baud_generator.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="baud_generator.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="baud_generator.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="baud_generator.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="baud_generator.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="baud_generator_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
51,9 → 63,11
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testSerial_receiver_beh.prj"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testBaud_generator_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testBaud_generator_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
65,98 → 79,67
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010966" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335010966">
<transform xil_pn:end_ts="1335536081" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335536081">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
<outfile xil_pn:name="serial_receiver.vhd"/>
<outfile xil_pn:name="serial_transmitter.vhd"/>
<outfile xil_pn:name="testBaud_generator.vhd"/>
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
</transform>
<transform xil_pn:end_ts="1335003497" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8542187049970039926" xil_pn:start_ts="1335003497">
<transform xil_pn:end_ts="1335532465" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8005028302593154456" xil_pn:start_ts="1335532465">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335003497" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8521261985131728908" xil_pn:start_ts="1335003497">
<transform xil_pn:end_ts="1335532465" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5095109948935799194" xil_pn:start_ts="1335532465">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335003249" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="3554467849218202431" xil_pn:start_ts="1335003249">
<transform xil_pn:end_ts="1335532006" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8789037243651182739" xil_pn:start_ts="1335532006">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010966" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335010966">
<transform xil_pn:end_ts="1335536081" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335536081">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
<outfile xil_pn:name="serial_receiver.vhd"/>
<outfile xil_pn:name="serial_transmitter.vhd"/>
<outfile xil_pn:name="testBaud_generator.vhd"/>
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
</transform>
<transform xil_pn:end_ts="1335010969" xil_pn:in_ck="-7334910543821964306" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1335010966">
<transform xil_pn:end_ts="1335536082" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4428763588696016622" xil_pn:start_ts="1335536081">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_beh.prj"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<outfile xil_pn:name="testBaud_generator_beh.prj"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335010969" xil_pn:in_ck="-2369381387331258610" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7589868709935752726" xil_pn:start_ts="1335010969">
<transform xil_pn:end_ts="1335536083" xil_pn:in_ck="9031792592001735694" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7081210365766751130" xil_pn:start_ts="1335536082">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1334961610" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1334961610">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8234491708054964473" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="3554467849218202431" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5735937742822206345" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010799" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-56991442930515319" xil_pn:start_ts="1335010799">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335010961" xil_pn:in_ck="-797052197999818498" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1927650389291255036" xil_pn:start_ts="1335010956">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="serial_receiver.lso"/>
<outfile xil_pn:name="serial_receiver.ngc"/>
<outfile xil_pn:name="serial_receiver.ngr"/>
<outfile xil_pn:name="serial_receiver.prj"/>
<outfile xil_pn:name="serial_receiver.stx"/>
<outfile xil_pn:name="serial_receiver.syr"/>
<outfile xil_pn:name="serial_receiver.xst"/>
<outfile xil_pn:name="serial_receiver_vhdl.prj"/>
<outfile xil_pn:name="serial_receiver_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
</transforms>
 
</generated_project>
/iseProject/pkgDefinitions.vhd
18,7 → 18,8
package pkgDefinitions is
 
--! Declare constants, enums, functions used by the design
constant nBits : integer := 8;
constant nBits : integer := 8;
constant nBitsLarge : integer := 32;
 
type txStates is (tx_idle, tx_start, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, tx_stop1, tx_stop2);
type rxStates is (rx_idle, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, rx_stop);
/iseProject/testDivisor.vhd
99,12 → 99,22
divident <= conv_std_logic_vector(115200, 32);
wait for 20 ns;
rst <= '0';
wait until done = '1';
wait for clk_period;
rst <= '1';
numerator <= conv_std_logic_vector(40, 32);
divident <= conv_std_logic_vector(5, 32);
wait for 20 ns;
rst <= '0';
wait until done = '1';
wait for clk_period;
 
wait for clk_period*32;
 
-- insert stimulus here
 
wait;
assert false report "NONE. End of simulation." severity failure;
end process;
 
END;
/iseProject/serial_receiver_envsettings.html
15,7 → 15,7
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
22,7 → 22,7
</tr>
<tr>
<td>Path</td>
<td>e:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64;<br>e:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64;<br>E:\Xilinx\13.4\ISE_DS\PlanAhead\bin;<br>E:\Xilinx\13.4\ISE_DS\ISE\bin\nt64;<br>E:\Xilinx\13.4\ISE_DS\ISE\lib\nt64;<br>E:\Xilinx\13.4\ISE_DS\EDK\bin\nt64;<br>E:\Xilinx\13.4\ISE_DS\EDK\lib\nt64;<br>E:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>E:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>E:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin;<br>E:\Xilinx\13.4\ISE_DS\common\bin\nt64;<br>E:\Xilinx\13.4\ISE_DS\common\lib\nt64;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Intel\DMIX;<br>C:\Program Files (x86)\Windows Live\Shared;<br>C:\Program Files (x86)\Autodesk\Backburner\;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>E:\Matlab12a\runtime\win64;<br>E:\Matlab12a\bin;<br>E:\Matlab\runtime\win64;<br>E:\Matlab\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin</td>
<td>e:<br>\Xilinx\13.4\ISE_DS\ISE\\lib\nt64;e:<br>\Xilinx\13.4\ISE_DS\ISE\\bin\nt64;E:<br>\Xilinx\13.4\ISE_DS\PlanAhead\bin;E:<br>\Xilinx\13.4\ISE_DS\ISE\bin\nt64;E:<br>\Xilinx\13.4\ISE_DS\ISE\lib\nt64;E:<br>\Xilinx\13.4\ISE_DS\EDK\bin\nt64;E:<br>\Xilinx\13.4\ISE_DS\EDK\lib\nt64;E:<br>\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin;E:<br>\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;E:<br>\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin;E:<br>\Xilinx\13.4\ISE_DS\common\bin\nt64;E:<br>\Xilinx\13.4\ISE_DS\common\lib\nt64;C:<br>\Program Files\Common Files\Microsoft Shared\Windows Live;C:<br>\Program Files (x86)\Common Files\Microsoft Shared\Windows Live;C:<br>\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:<br>\Windows\system32;C:<br>\Windows;C:<br>\Windows\System32\Wbem;C:<br>\Windows\System32\WindowsPowerShell\v1.0\;C:<br>\Program Files\Intel\DMIX;C:<br>\Program Files (x86)\Windows Live\Shared;C:<br>\Program Files (x86)\Autodesk\Backburner\;C:<br>\Program Files (x86)\QuickTime\QTSystem\;E:<br>\Matlab12a\runtime\win64;E:<br>\Matlab12a\bin;E:<br>\Matlab\runtime\win64;E:<br>\Matlab\bin;C:<br>\Program Files\TortoiseSVN\bin;C:<br>\Program Files\doxygen\bin</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
29,7 → 29,7
</tr>
<tr>
<td>XILINX</td>
<td>e:\Xilinx\13.4\ISE_DS\ISE\</td>
<td>e:<br>\Xilinx\13.4\ISE_DS\ISE\</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
36,7 → 36,7
</tr>
<tr>
<td>XILINX_DSP</td>
<td>E:\Xilinx\13.4\ISE_DS\ISE</td>
<td>E:<br>\Xilinx\13.4\ISE_DS\ISE</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
43,7 → 43,7
</tr>
<tr>
<td>XILINX_EDK</td>
<td>E:\Xilinx\13.4\ISE_DS\EDK</td>
<td>E:<br>\Xilinx\13.4\ISE_DS\EDK</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
57,7 → 57,7
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>E:\Xilinx\13.4\ISE_DS\PlanAhead</td>
<td>E:<br>\Xilinx\13.4\ISE_DS\PlanAhead</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
/iseProject/iseconfig/serial_receiver.xreport
1,17 → 1,17
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-04-21T14:19:58</DateModified>
<ModuleName>serial_receiver</ModuleName>
<SummaryTimeStamp>2012-04-21T12:13:10</SummaryTimeStamp>
<SavedFilePath>E:/uart_block/hdl/iseProject/iseconfig/serial_receiver.xreport</SavedFilePath>
<ImplementationReportsDirectory>E:/uart_block/hdl/iseProject</ImplementationReportsDirectory>
<DateInitialized>2012-04-21T11:41:59</DateInitialized>
<DateModified>2012-04-27T15:15:20</DateModified>
<ModuleName>baud_generator</ModuleName>
<SummaryTimeStamp>2012-04-27T15:05:36</SummaryTimeStamp>
<SavedFilePath>/home/laraujo/work/uart_block/hdl/iseProject/iseconfig/serial_receiver.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/laraujo/work/uart_block/hdl/iseProject/</ImplementationReportsDirectory>
<DateInitialized>2012-04-27T14:55:26</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="serial_receiver_summary.html" label="Summary" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="baud_generator_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
18,16 → 18,16
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="serial_receiver_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="serial_receiver_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="serial_receiver_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="serial_receiver_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="serial_receiver.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="serial_receiver_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="serial_receiver_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="serial_receiver.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="serial_receiver_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="serial_receiver_html/tim/report.htm" label="CPLD Timing Report" />
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="baud_generator_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="baud_generator_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="baud_generator_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="baud_generator_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="baud_generator.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="baud_generator_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="baud_generator_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="baud_generator.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="baud_generator_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="baud_generator_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
38,7 → 38,7
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="serial_receiver.log" label="System Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="baud_generator.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
54,7 → 54,7
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="serial_receiver.syr" label="Synthesis Report" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="baud_generator.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
80,15 → 80,15
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="serial_receiver.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="serial_receiver.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="serial_receiver.bld" label="Translation Report" >
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="baud_generator.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="baud_generator.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="baud_generator.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="serial_receiver_map.mrp" label="Map Report" >
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="baud_generator_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
104,7 → 104,7
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="serial_receiver.par" label="Place and Route Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="baud_generator.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
113,7 → 113,7
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="serial_receiver.twr" label="Post-PAR Static Timing Report" >
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="baud_generator.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
124,22 → 124,22
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="serial_receiver.rpt" label="CPLD Fitter Report (Text)" >
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="baud_generator.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="serial_receiver.tim" label="CPLD Timing Report (Text)" >
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="baud_generator.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="serial_receiver.pwr" label="Power Report" >
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="baud_generator.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="serial_receiver.bgn" label="Bitgen Report" >
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="baud_generator.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
147,20 → 147,20
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/serial_receiver_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/baud_generator_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/serial_receiver_translate.nlf" label="Post-Translate Simulation Model Report" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/baud_generator_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="serial_receiver_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="serial_receiver_map.map" label="Map Log File" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="baud_generator_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="baud_generator_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver_preroute.twr" label="Post-Map Static Timing Report" >
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
171,43 → 171,43
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/serial_receiver_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver_map.psr" label="Physical Synthesis Report" >
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/baud_generator_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="serial_receiver_pad.txt" label="Pad Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="baud_generator_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="serial_receiver.unroutes" label="Unroutes Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="baud_generator.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver.tsi" label="Post-Place and Route Constraints Interaction Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="serial_receiver_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/serial_receiver_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="serial_receiver_sta.nlf" label="Primetime Netlist Report" >
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="baud_generator_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/baud_generator_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="baud_generator_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="serial_receiver.ibs" label="IBIS Model" >
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="baud_generator.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver.lck" label="Back-annotate Pin Report" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="serial_receiver.lpc" label="Locked Pin Constraints" >
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="baud_generator.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/serial_receiver_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/baud_generator_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
/iseProject/testSerial_receiver_isim_beh.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iseProject/fuse.log
1,21 → 1,25
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package pkgdefinitions
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavior of entity testserial_receiver
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 29488 KB
Fuse CPU Usage: 249 ms
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj work.testBaud_generator
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36644 KB
Fuse CPU Usage: 1080 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavior of entity testbaud_generator
Time Resolution for simulation is 1ps.
Compiled 8 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe
Fuse Memory Usage: 85592 KB
Fuse CPU Usage: 1160 ms
GCC CPU Usage: 260 ms
/iseProject/webtalk_pn.xml
1,46 → 1,47
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Apr 21 14:22:36 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="E:/uart_block/hdl/iseProject/iseProject.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/>
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testSerial_receiver" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/>
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testSerial_receiver" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
<property name="PROP_DevDevice" value="xc3s500e" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 us" type="process"/>
<property name="PROP_DevPackage" value="fg320" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="5" type="source"/>
</section>
</application>
</document>
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Apr 27 15:05:28 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/home/laraujo/work/uart_block/hdl/iseProject/iseProject.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2012-04-20T22:53:04" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
<property name="PROP_Board" value="Spartan-3E Starter Board" type="process"/>
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testSerial_receiver" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2012-04-20T22:53:04" type="design"/>
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testSerial_receiver" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/>
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
<property name="PROP_DevDevice" value="xc3s500e" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
<property name="PROP_ISimSimulationRunTime_behav_tb" value="1000 us" type="process"/>
<property name="PROP_DevPackage" value="fg320" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="8" type="source"/>
</section>
</application>
</document>
/iseProject/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/serial_receiver.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/iseProject/_xmsgs/xst.xmsgs
1,93 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">E:/uart_block/hdl/iseProject/serial_receiver.vhd</arg>&quot; line <arg fmt="%d" index="2">86</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;serial_in&gt;</arg>
</msg>
</messages>
 
<msg type="warning" file="Xst" num="737" delta="new" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;7&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="new" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;7&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="2042" delta="new" >Unit <arg fmt="%s" index="1">serial_receiver</arg>: <arg fmt="%d" index="2">8</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
 
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
</messages>
 
/iseProject/testBaud_generator.vhd
0,0 → 1,75
--! Test baud_generator module
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use Global Definitions package
use work.pkgDefinitions.all;
ENTITY testBaud_generator IS
END testBaud_generator;
ARCHITECTURE behavior OF testBaud_generator IS
COMPONENT baud_generator
PORT(
rst : IN std_logic;
clk : IN std_logic;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
 
--Outputs
signal baud : std_logic;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: baud_generator PORT MAP (
rst => rst,
clk => clk,
cycle_wait => cycle_wait,
baud => baud
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- Test the baud generator waiting for 10 clock cycles
rst <= '1';
cycle_wait <= conv_std_logic_vector(2, (nBitsLarge));
wait for 10 ns;
rst <= '0';
 
wait for clk_period*100;
 
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
 
wait;
end process;
 
END;
/iseProject/baud_generator.vhd
0,0 → 1,46
--! Baud generator
--! http://www.fpga4fun.com/SerialInterface.html
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity baud_generator is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud : out STD_LOGIC);
end baud_generator;
 
architecture Behavioral of baud_generator is
signal genTick : std_logic;
begin
process (rst, clk)
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
begin
if rst = '1' then
wait_clk_cycles := (others => '0');
half_cycle := '0' & cycle_wait(cycle_wait'high downto 1);
genTick <= '0';
elsif rising_edge(clk) then
if wait_clk_cycles = cycle_wait then
genTick <= '1';
wait_clk_cycles := (others => '0');
else
wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, (nBitsLarge-1));
-- If we're at half of the cycle
if wait_clk_cycles = half_cycle then
genTick <= '0';
end if;
end if;
end if;
end process;
baud <= genTick;
 
end Behavioral;
 
/iseProject/fuse.xmsgs
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
 
 
/iseProject/xilinxsim.ini
1,9 → 1,9
work=isim/work
work=isim/work
/iseProject/isim.cmd
1,3 → 1,3
onerror {resume}
wave add /
run 1000 us;
onerror {resume}
wave add /
run 1000 us;
/iseProject/pepExtractor.prj
1,2 → 1,2
work "pkgDefinitions.vhd"
work "serial_receiver.vhd"
work "baud_generator.vhd"
work "pkgDefinitions.vhd"
/iseProject/iseProject.xise
30,15 → 30,35
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/>
</file>
</files>
 
<properties>
65,7 → 85,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
144,9 → 164,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|serial_receiver|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="serial_receiver.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/serial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|baud_generator|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="baud_generator.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/baud_generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
204,7 → 224,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="serial_receiver" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="baud_generator" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
216,10 → 236,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="serial_receiver_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="serial_receiver_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="serial_receiver_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="serial_receiver_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="baud_generator_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="baud_generator_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="baud_generator_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="baud_generator_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
239,7 → 259,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="serial_receiver" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="baud_generator" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
263,8 → 283,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testBaud_generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testBaud_generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
280,7 → 300,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testBaud_generator" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
329,7 → 349,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testSerial_receiver|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testBaud_generator|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/iseProject/xst/work/hdpdeps.ref
1,19 → 1,30
V3 9
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd
PH work/pkgDefinitions 1335010957 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335010958 \
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd PH work/pkgDefinitions 1335010957
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd
EN work/serial_receiver 1335010959 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1335010958
AR work/serial_receiver/Behavioral 1335010960 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1335010959
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1335001307 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335010958
AR work/serial_transmitter/Behavioral 1335001308 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335001307
V3 13
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/04/27.15:05:22 O.87xd
EN work/baud_generator 1335531934 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335531933
AR work/baud_generator/Behavioral 1335531935 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
EN work/baud_generator 1335531934
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/23.13:47:40 O.87xd
PH work/pkgDefinitions 1335531932 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335531933 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PH work/pkgDefinitions 1335531932
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd
EN work/serial_receiver 1335010959 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1335531933
AR work/serial_receiver/Behavioral 1335010960 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1335010959
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1335001307 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335531933
AR work/serial_transmitter/Behavioral 1335001308 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335001307
/iseProject/xst/work/hdllib.ref
1,6 → 1,8
PB pkgdefinitions pkgdefinitions E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335010958
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335010959
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335001308
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335001307
PH pkgdefinitions NULL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335010957
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335010960
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335001308
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335531935
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335010959
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335001307
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335010960
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335531933
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335531934
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335531932
/iseProject/xst/work/sub00/vhpl00.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/iseProject/xst/work/sub00/vhpl01.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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