OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block/trunk/hdl
    from Rev 8 to Rev 9
    ↔ Reverse comparison
  •

Rev 8 → Rev 9

/iseProject/isim.log
1,5 → 1,5
ISim log file
Running: E:\uart_block\hdl\iseProject\testBaud_generator_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.wdb
Running: E:\uart_block\hdl\iseProject\testDivisor_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testDivisor_isim_beh.wdb
ISim O.87xd (signature 0xc3576ebc)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
14,6 → 14,6
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testBaud_generator.vhd:stim_proc
In process testDivisor.vhd:stim_proc
INFO: Simulator is stopped.
/iseProject/fuseRelaunch.cmd
1,6 → 14,6
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testBaud_generator_beh.prj" "work.testBaud_generator"
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testDivisor_beh.prj" "testDivisor"
/iseProject/uart_control.vhd
0,0 → 1,139
--! uart control unit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity uart_control is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
WE : in STD_LOGIC;
reg_addr : in STD_LOGIC_VECTOR (1 downto 0);
DAT_I : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
DAT_O : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
tx_busy : in STD_LOGIC;
rx_ready : in STD_LOGIC);
end uart_control;
 
architecture Behavioral of uart_control is
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
signal byte_out : std_logic_vector((nBitsLarge-1) downto 0);
signal byte_in : std_logic_vector((nBitsLarge-1) downto 0);
signal controlStates : uartControl;
 
signal sigDivRst : std_logic;
signal sigDivDone : std_logic;
signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivReminder : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0);
signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0);
 
-- Divisor component
component divisor is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
done : out STD_LOGIC);
end component;
 
begin
-- Instantiate block for calculate division
uDiv : divisor port map (
rst => sigDivRst,
clk => clk,
quotient => sigDivQuotient,
reminder => sigDivReminder,
numerator => sigDivNumerator,
divident => sigDivDividend,
done => sigDivDone
);
-- Process that populate/read the uart control registers
process (rst, clk, reg_addr,WE)
begin
if rst = '1' then
config_clk <= (others => '0');
config_baud <= (others => '0');
byte_out <= (others => '0');
byte_in <= (others => '0');
elsif rising_edge(clk) then
if WE = '1' then
case reg_addr is
when "00" =>
config_clk <= DAT_I;
when "01" =>
config_baud <= DAT_I;
when "10" =>
byte_out <= DAT_I((nBits-1) downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
-- Process to handle the next state logic
process (rst, clk, reg_addr, WE)
variable baud_configured : std_logic;
variable clk_configured : std_logic;
begin
if rst = '1' then
controlStates <= idle;
baud_configured <= '0';
clk_configured <= '0';
elsif rising_edge(clk) then
case controlStates is
when idle =>
-- Go to config state
if (reg_addr = "00") and (WE = '1') then
controlStates <= config_state_clk;
clk_configured <= '1';
elsif (reg_addr = "01") and (WE = '1') then
controlStates <= config_state_baud;
baud_configured <= '1';
end if;
when config_state_clk =>
sigDivRst <= '1';
sigDivNumerator <= config_clk;
if baud_configured = '0' then
-- Baud not configured yet so wait for it...
controlStates <= idle;
else
-- If already configured wait for division completion...
controlStates <= start_division;
end if;
when config_state_baud =>
sigDivRst <= '1';
sigDivDividend <= config_baud;
if clk_configured = '0' then
-- Clock not configured yet so wait for it...
controlStates <= idle;
else
-- If already configured wait for division completion...
controlStates <= start_division;
end if;
when start_division =>
sigDivRst <= '0';
controlStates <= wait_division;
when wait_division =>
if sigDivDone = '0' then
controlStates <= wait_division;
else
-- Division done, configure the Baud generator
end if;
end case;
end if;
end process;
 
end Behavioral;
 
/iseProject/iseProject.gise
64,10 → 64,11
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testBaud_generator_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testBaud_generator_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDivisor_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDivisor_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
80,7 → 81,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335696912" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335696912">
<transform xil_pn:end_ts="1335706001" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335706001">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="baud_generator.vhd"/>
92,12 → 93,13
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
</transform>
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8005028302593154456" xil_pn:start_ts="1335696912">
<transform xil_pn:end_ts="1335706001" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6042613676112735766" xil_pn:start_ts="1335706001">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5095109948935799194" xil_pn:start_ts="1335696912">
<transform xil_pn:end_ts="1335706001" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4641732051429320088" xil_pn:start_ts="1335706001">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
105,7 → 107,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335696912" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335696912">
<transform xil_pn:end_ts="1335706001" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335706001">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="baud_generator.vhd"/>
117,23 → 119,24
<outfile xil_pn:name="testDivisor.vhd"/>
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
</transform>
<transform xil_pn:end_ts="1335696915" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4428763588696016622" xil_pn:start_ts="1335696912">
<transform xil_pn:end_ts="1335706004" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="1599609758225969422" xil_pn:start_ts="1335706001">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testBaud_generator_beh.prj"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.exe"/>
<outfile xil_pn:name="testDivisor_beh.prj"/>
<outfile xil_pn:name="testDivisor_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335696915" xil_pn:in_ck="6990163578190363152" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7081210365766751130" xil_pn:start_ts="1335696915">
<transform xil_pn:end_ts="1335706004" xil_pn:in_ck="6966519603717532447" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4515288970544773250" xil_pn:start_ts="1335706004">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.wdb"/>
<outfile xil_pn:name="testDivisor_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1334961610" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1334961610">
<status xil_pn:value="SuccessfullyRun"/>
/iseProject/pkgDefinitions.vhd
25,6 → 25,8
type rxStates is (rx_idle, bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, rx_stop);
type rxFilterStates is (s0, s1, s2, s3);
 
type uartControl is (idle, config_state_clk, config_state_baud, start_division, wait_division, rcv_command, wait_state);
 
end pkgDefinitions;
 
package body pkgDefinitions is
/iseProject/divisor.vhd
2,15 → 2,18
--! http://en.wikipedia.org/wiki/Division_%28digital%29
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity divisor is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
quotient : out STD_LOGIC_VECTOR (31 downto 0);
reminder : out STD_LOGIC_VECTOR (31 downto 0);
numerator : in STD_LOGIC_VECTOR (31 downto 0);
divident : in STD_LOGIC_VECTOR (31 downto 0);
quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
done : out STD_LOGIC);
end divisor;
 
/iseProject/iseconfig/iseProject.projectmgr
1,134 → 1,134
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="iseProject" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/serial_transmitter - Behavioral E:|uart_block|hdl|iseProject|serial_transmitter.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>baud_generator - Behavioral (/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd)</SelectedItem>
</SelectedItems>
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<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001a8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001a80000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>baud_generator - Behavioral (/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
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<CurrentItem></CurrentItem>
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<ItemView guiview="File" >
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<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
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<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="iseProject" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000175000000020000000000000000000000000200000064ffffffff000000810000000300000002000001750000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>Unassigned User Library Modules</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000040100000002</SourceProcessView>
<CurrentView>Behavioral Simulation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_BODY" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
</Project>
/iseProject/fuse.log
1,23 → 1,22
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testBaud_generator_beh.prj work.testBaud_generator
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testDivisor_beh.prj testDivisor
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testDivisor.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavior of entity testbaud_generator
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavior of entity testdivisor
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe
Fuse Memory Usage: 33672 KB
Fuse CPU Usage: 280 ms
Compiled 7 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testDivisor_isim_beh.exe
Fuse Memory Usage: 33532 KB
Fuse CPU Usage: 264 ms
/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/baud_generator.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/uart_control.vhd&quot; into library work</arg>
</msg>
 
</messages>
/iseProject/testBaud_generator.vhd
33,7 → 33,7
signal baud : std_logic;
 
-- Clock period definitions (1.8432MHz)
constant clk_period : time := 5.43 us;
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
BEGIN
58,13 → 58,13
-- Stimulus process
stim_proc: process
begin
-- Test the baud generator waiting for 10 clock cycles
-- Test the baud generator waiting for 16 clock cycles for 1.8432MHz clock
rst <= '1';
cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
wait for 10 us;
wait for 2 ns;
rst <= '0';
 
wait for clk_period*100;
wait for clk_period*300;
 
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
/iseProject/iseProject.xise
40,25 → 40,29
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
</files>
 
<properties>
283,8 → 287,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testBaud_generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testBaud_generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDivisor" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDivisor" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
300,7 → 304,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testBaud_generator" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDivisor" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
349,7 → 353,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testBaud_generator|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDivisor|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

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