OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block/trunk
    from Rev 10 to Rev 11
    ↔ Reverse comparison
  •

Rev 10 → Rev 11

/hdl/iseProject/isim.log
1,5 → 1,5
ISim log file
Running: /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb
Running: /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
14,6 → 14,7
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
In process testBaud_generator.vhd:stim_proc
INFO: Simulator is stopped.
# exit 0
/hdl/iseProject/fuseRelaunch.cmd
1,6 → 14,7
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "work.testSerial_receiver"
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj" "work.testBaud_generator"
/hdl/iseProject/testSerial_transmitter_isim_beh.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/hdl/iseProject/uart_control.vhd
24,8 → 24,8
architecture Behavioral of uart_control is
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0);
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0);
signal byte_to_receive : std_logic_vector((nBitsLarge-1) downto 0);
signal byte_to_transmitt : std_logic_vector((nBitsLarge-1) downto 0);
signal byte_to_receive : std_logic_vector((nBits-1) downto 0);
signal byte_to_transmitt : std_logic_vector((nBits-1) downto 0);
signal controlStates : uartControl;
 
signal sigDivRst : std_logic;
70,10 → 70,10
DAT_O <= config_baud;
when "10" =>
-- Byte that will be transmitted
DAT_O <= "0000000000000000000000000" & byte_to_transmitt;
DAT_O <= "000000000000000000000000" & byte_to_transmitt;
when "11" =>
-- Byte that will be received
DAT_O <= "0000000000000000000000000" & byte_to_receive;
DAT_O <= "000000000000000000000000" & byte_to_receive;
when others =>
null;
end case;
87,8 → 87,7
if rst = '1' then
config_clk <= (others => '0');
config_baud <= (others => '0');
byte_to_transmitt <= (others => '0');
byte_to_receive <= (others => '0');
byte_to_transmitt <= (others => '0');
elsif rising_edge(clk) then
if (WE = '1') and (start = '1') then
case reg_addr is
114,9 → 113,9
begin
if rst = '1' then
controlStates <= idle;
baud_configured <= '0';
clk_configured <= '0';
div_result_baud_wait <= (others => '0');
baud_configured := '0';
clk_configured := '0';
div_result_baud_wait := (others => '0');
done <= '0';
elsif rising_edge(clk) then
case controlStates is
125,10 → 124,10
-- Go to config state
if (reg_addr = "00") and (WE = '1') then
controlStates <= config_state_clk;
clk_configured <= '1';
clk_configured := '1';
elsif (reg_addr = "01") and (WE = '1') then
controlStates <= config_state_baud;
baud_configured <= '1';
baud_configured := '1';
end if;
when config_state_clk =>
/hdl/iseProject/iseProject.gise
64,15 → 64,38
<file xil_pn:fileType="FILE_HTML" xil_pn:name="serial_transmitter_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="serial_transmitter_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testBaud_generator_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testBaud_generator_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDivisor_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDivisor_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testSerial_receiver_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_communication_blocks.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_communication_blocks.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_communication_blocks.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_communication_blocks.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_communication_blocks.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_communication_blocks.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_communication_blocks.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_communication_blocks.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_communication_blocks_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_communication_blocks_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_communication_blocks_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_communication_blocks_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_control.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="uart_control.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="uart_control.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="uart_control.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="uart_control.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="uart_control.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="uart_control.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="uart_control_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="uart_control_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="uart_control_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
83,9 → 106,14
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335769526" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335769526">
<transform xil_pn:end_ts="1335782876" xil_pn:in_ck="-2099838962693487701" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335782876">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
96,22 → 124,28
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_main_blocks.vhd"/>
</transform>
<transform xil_pn:end_ts="1335769140" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8542187049970039926" xil_pn:start_ts="1335769140">
<transform xil_pn:end_ts="1335782187" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8005028302593154456" xil_pn:start_ts="1335782187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335769140" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8521261985131728908" xil_pn:start_ts="1335769140">
<transform xil_pn:end_ts="1335782187" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5095109948935799194" xil_pn:start_ts="1335782187">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8789037243651182739" xil_pn:start_ts="1335696912">
<transform xil_pn:end_ts="1335782876" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-6911516643493882311" xil_pn:start_ts="1335782876">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335769526" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335769526">
<transform xil_pn:end_ts="1335782211" xil_pn:in_ck="-2099838962693487701" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335782211">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="baud_generator.vhd"/>
<outfile xil_pn:name="divisor.vhd"/>
<outfile xil_pn:name="pkgDefinitions.vhd"/>
122,30 → 156,82
<outfile xil_pn:name="testSerial_receiver.vhd"/>
<outfile xil_pn:name="testSerial_transmitter.vhd"/>
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_main_blocks.vhd"/>
</transform>
<transform xil_pn:end_ts="1335769528" xil_pn:in_ck="2762791571174539902" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1335769526">
<transform xil_pn:end_ts="1335782212" xil_pn:in_ck="-2099838962693487701" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4428763588696016622" xil_pn:start_ts="1335782211">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_beh.prj"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<outfile xil_pn:name="testBaud_generator_beh.prj"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1335769528" xil_pn:in_ck="9031792592001735694" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7589868709935752726" xil_pn:start_ts="1335769528">
<transform xil_pn:end_ts="1335782213" xil_pn:in_ck="9031792592001735694" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7081210365766751130" xil_pn:start_ts="1335782212">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<outfile xil_pn:name="testBaud_generator_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1334961610" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1334961610">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1553236666384884621" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6911516643493882311" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2973727296883449201" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782403" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="1186905421486694915" xil_pn:start_ts="1335782403">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1335782992" xil_pn:in_ck="-3698481516999820423" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1048667062462877750" xil_pn:start_ts="1335782983">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="baud_generator.ngr"/>
<outfile xil_pn:name="serial_receiver.ngr"/>
<outfile xil_pn:name="serial_transmitter.ngr"/>
<outfile xil_pn:name="uart_communication_blocks.lso"/>
<outfile xil_pn:name="uart_communication_blocks.ngc"/>
<outfile xil_pn:name="uart_communication_blocks.ngr"/>
<outfile xil_pn:name="uart_communication_blocks.prj"/>
<outfile xil_pn:name="uart_communication_blocks.stx"/>
<outfile xil_pn:name="uart_communication_blocks.syr"/>
<outfile xil_pn:name="uart_communication_blocks.xst"/>
<outfile xil_pn:name="uart_communication_blocks_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
</transforms>
 
</generated_project>
/hdl/iseProject/fuse.log
1,23 → 1,26
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_beh.prj work.testSerial_receiver
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj work.testBaud_generator
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 36024 KB
Fuse CPU Usage: 1120 ms
Fuse Memory Usage: 36516 KB
Fuse CPU Usage: 1080 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavior of entity testserial_receiver
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavior of entity testbaud_generator
Time Resolution for simulation is 1ps.
Compiled 6 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 79448 KB
Fuse CPU Usage: 1150 ms
GCC CPU Usage: 310 ms
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe
Fuse Memory Usage: 85608 KB
Fuse CPU Usage: 1160 ms
GCC CPU Usage: 290 ms
/hdl/iseProject/webtalk_pn.xml
3,7 → 3,7
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Apr 27 15:05:28 2012">
<application name="pn" timeStamp="Mon Apr 30 12:49:44 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
19,7 → 19,7
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testSerial_receiver" type="process"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/uart_communication_blocks" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
29,7 → 29,7
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testSerial_receiver" type="process"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.uart_communication_blocks" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/>
41,7 → 41,7
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-4" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="8" type="source"/>
<property name="FILE_VHDL" value="12" type="source"/>
</section>
</application>
</document>
/hdl/iseProject/testUart_communication_block.vhd
0,0 → 1,88
--! Test baud_generator module
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--! Use Global Definitions package
use work.pkgDefinitions.all;
ENTITY testUart_communication_block IS
END testUart_communication_block;
ARCHITECTURE behavior OF testUart_communication_block IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT uart_communication_blocks
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent_tx : out STD_LOGIC;
data_received_rx : out STD_LOGIC;
serial_out : out std_logic;
serial_in : in std_logic;
start_tx : in STD_LOGIC);
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal cycle_wait_baud : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
signal byte_tx : std_logic_vector((nBits-1) downto 0) := (others => '0');
signal serial_in : std_logic := '0';
signal start_tx : std_logic := '0';
 
--Outputs
signal byte_rx : std_logic_vector((nBits-1) downto 0);
signal data_sent_tx : std_logic;
signal data_received_rx : std_logic;
signal serial_out : std_logic;
 
-- Clock period definitions
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: uart_communication_blocks PORT MAP (
rst => rst,
clk => clk,
cycle_wait_baud => cycle_wait_baud,
byte_tx => byte_tx,
byte_rx => byte_rx,
data_sent_tx => data_sent_tx,
data_received_rx => data_received_rx,
serial_out => serial_out,
serial_in => serial_in,
start_tx => start_tx
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- Setup communication blocks
rst <= '1';
cycle_wait_baud <= conv_std_logic_vector(16, (nBitsLarge));
wait for 2 ns;
rst <= '0';
 
wait for clk_period*10;
 
-- insert stimulus here
 
wait;
end process;
 
END;
/hdl/iseProject/testSerial_transmitter.vhd
76,9 → 76,10
 
wait until data_sent = '1';
wait for baudClk_period*3;
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
 
-- insert stimulus here
 
wait;
end process;
 
/hdl/iseProject/uart_main_blocks.vhd
0,0 → 1,81
--! Top level for interconnection between communication blocks: serial_transmitter, serial_receiver, baud_generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
--! Use CPU Definitions package
use work.pkgDefinitions.all;
 
entity uart_communication_blocks is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait_baud : in std_logic_vector((nBitsLarge-1) downto 0);
byte_tx : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
byte_rx : out STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent_tx : out STD_LOGIC;
data_received_rx : out STD_LOGIC;
serial_out : out std_logic;
serial_in : in std_logic;
start_tx : in STD_LOGIC);
end uart_communication_blocks;
 
architecture Behavioral of uart_communication_blocks is
 
-- Declare components...
component baud_generator is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : out STD_LOGIC);
end component;
 
component serial_transmitter is
Port ( rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
data_sent : out STD_LOGIC;
serial_out : out STD_LOGIC);
end component;
 
component serial_receiver is
Port (
rst : in STD_LOGIC;
baudClk : in STD_LOGIC;
baudOverSampleClk : in STD_LOGIC;
serial_in : in STD_LOGIC;
data_ready : out STD_LOGIC;
data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
end component;
signal baud_tick : std_logic;
signal baud_tick_oversample : std_logic;
begin
-- Instantiate baud generator
uBaudGen : baud_generator port map (
rst => rst,
clk => clk,
cycle_wait => cycle_wait_baud,
baud_oversample => baud_tick_oversample,
baud => baud_tick
);
-- Instantiate serial_transmitter
uTransmitter : serial_transmitter port map (
rst => not start_tx,
baudClk => baud_tick,
data_byte => byte_tx,
data_sent => data_sent_tx,
serial_out => serial_out
);
-- Instantiate serial_receiver
uReceiver : serial_receiver port map(
rst => rst,
baudClk => baud_tick,
baudOverSampleClk => baud_tick_oversample,
serial_in => serial_in,
data_ready => data_received_rx,
data_byte => byte_rx
);
 
end Behavioral;
 
/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/uart_block/hdl/iseProject/testUart_communication_block.vhd&quot; into library work</arg>
</msg>
 
</messages>
/hdl/iseProject/_xmsgs/xst.xmsgs
5,5 → 5,235
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd</arg>&quot; line <arg fmt="%d" index="2">23</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;cycle_wait&gt;</arg>
</msg>
 
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd</arg>&quot; line <arg fmt="%d" index="2">51</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;cycle_wait&gt;</arg>
</msg>
 
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd</arg>&quot; line <arg fmt="%d" index="2">86</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;serial_in&gt;</arg>
</msg>
 
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">cycle_wait_oversample</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">half_cycle</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">32</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">half_cycle0</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="1780" delta="old" >Signal &lt;<arg fmt="%s" index="1">byteReceived&lt;7&gt;</arg>&gt; is never used or assigned. This unconnected signal will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">data_byte</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtridata_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;0&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;1&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;2&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;3&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;4&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;5&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="736" delta="old" >Found <arg fmt="%d" index="1">1</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">Mtrien_byteReceived&lt;6&gt;</arg>&gt; created at line <arg fmt="%d" index="3">92</arg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg>
 
<msg type="info" file="Xst" num="2371" delta="old" >HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">29</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">30</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">28</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">29</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">30</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">0</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">31</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_28</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_29</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_30</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="warning" file="Xst" num="1895" delta="old" >Due to other FF/Latch trimming, FF/Latch &lt;<arg fmt="%s" index="1">cycle_wait_oversample_31</arg>&gt; (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">baud_generator</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_6</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_9&gt; &lt;cycle_wait_oversample_7&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_3</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_6&gt; &lt;cycle_wait_oversample_4&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_22</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_25&gt; &lt;cycle_wait_oversample_23&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_27</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_30&gt; &lt;cycle_wait_oversample_28&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_12</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_15&gt; &lt;cycle_wait_oversample_13&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_17</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_20&gt; &lt;cycle_wait_oversample_18&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_10&gt; &lt;cycle_wait_oversample_8&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_7&gt; &lt;cycle_wait_oversample_5&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_23</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_26&gt; &lt;cycle_wait_oversample_24&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;cycle_wait_oversample_0&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_13</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_16&gt; &lt;cycle_wait_oversample_14&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_18</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_21&gt; &lt;cycle_wait_oversample_19&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_8</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_11&gt; &lt;cycle_wait_oversample_9&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_5</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_8&gt; &lt;cycle_wait_oversample_6&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_24</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_27&gt; &lt;cycle_wait_oversample_25&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_0</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_3&gt; &lt;cycle_wait_oversample_1&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_14</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_17&gt; &lt;cycle_wait_oversample_15&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_19</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_22&gt; &lt;cycle_wait_oversample_20&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_9</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_12&gt; &lt;cycle_wait_oversample_10&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_25</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_28&gt; &lt;cycle_wait_oversample_26&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_1</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_4&gt; &lt;cycle_wait_oversample_2&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_15</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_18&gt; &lt;cycle_wait_oversample_16&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_20</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_23&gt; &lt;cycle_wait_oversample_21&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_10</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_13&gt; &lt;cycle_wait_oversample_11&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_2</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_5&gt; &lt;cycle_wait_oversample_3&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_21</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_24&gt; &lt;cycle_wait_oversample_22&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_26</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_29&gt; &lt;cycle_wait_oversample_27&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_14&gt; &lt;cycle_wait_oversample_12&gt; </arg>
</msg>
 
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">half_cycle0_16</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">baud_generator</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;half_cycle_19&gt; &lt;cycle_wait_oversample_17&gt; </arg>
</msg>
 
<msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">serial_receiver</arg>: <arg fmt="%d" index="2">7</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg>
 
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
 
</messages>
 
/hdl/iseProject/baud_generator.vhd
12,11 → 12,13
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : out STD_LOGIC);
end baud_generator;
 
architecture Behavioral of baud_generator is
signal genTick : std_logic;
signal genTickOverSample : std_logic;
begin
process (rst, clk)
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
43,6 → 45,40
end process;
baud <= genTick;
baud_oversample <= genTickOverSample;
-- Process to generate the overclocked (8x) sample
process (rst, clk)
variable wait_clk_cycles : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable half_cycle : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
variable cycle_wait_oversample : STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
begin
if rst = '1' then
wait_clk_cycles := (others => '0');
-- Divide cycle_wait by 8
cycle_wait_oversample := '0' & cycle_wait(cycle_wait'high downto 1);
cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
cycle_wait_oversample := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
-- Half of cycle_wait_oversample
half_cycle := '0' & cycle_wait_oversample(cycle_wait_oversample'high downto 1);
genTickOverSample <= '0';
elsif rising_edge(clk) then
-- Just decremented the cycle_wait by one because genTick would be updated on the next cycle
-- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait)
if wait_clk_cycles = (cycle_wait_oversample - conv_std_logic_vector(1, (nBitsLarge-1))) then
genTickOverSample <= '1';
wait_clk_cycles := (others => '0');
else
wait_clk_cycles := wait_clk_cycles + conv_std_logic_vector(1, (nBitsLarge-1));
-- If we're at half of the cycle
if wait_clk_cycles = half_cycle then
genTickOverSample <= '0';
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/hdl/iseProject/testBaud_generator.vhd
11,14 → 11,13
END testBaud_generator;
ARCHITECTURE behavior OF testBaud_generator IS
COMPONENT baud_generator
PORT(
rst : IN std_logic;
clk : IN std_logic;
cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
baud_oversample : out std_logic;
baud : OUT std_logic
);
END COMPONENT;
31,6 → 30,7
 
--Outputs
signal baud : std_logic;
signal baud_oversample : std_logic;
 
-- Clock period definitions (1.8432MHz)
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
42,6 → 42,7
rst => rst,
clk => clk,
cycle_wait => cycle_wait,
baud_oversample => baud_oversample,
baud => baud
);
 
/hdl/iseProject/pepExtractor.prj
1,2 → 1,5
work "baud_generator.vhd"
work "pkgDefinitions.vhd"
work "serial_receiver.vhd"
work "serial_transmitter.vhd"
work "uart_main_blocks.vhd"
/hdl/iseProject/iseProject.xise
16,8 → 16,8
 
<files>
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
30,11 → 30,11
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
50,8 → 50,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
61,8 → 61,18
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="uart_main_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="103"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/>
</file>
</files>
 
<properties>
168,9 → 178,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|baud_generator|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="baud_generator.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/baud_generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|uart_communication_blocks|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="uart_main_blocks.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/uart_communication_blocks" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
228,7 → 238,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="baud_generator" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="uart_communication_blocks" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
240,10 → 250,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="baud_generator_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="baud_generator_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="baud_generator_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="baud_generator_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="uart_communication_blocks_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="uart_communication_blocks_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="uart_communication_blocks_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="uart_communication_blocks_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
263,7 → 273,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="baud_generator" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="uart_communication_blocks" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
287,8 → 297,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/uart_communication_blocks" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.uart_communication_blocks" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
304,7 → 314,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.uart_communication_blocks" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
353,7 → 363,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testSerial_receiver|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testBaud_generator|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/hdl/iseProject/xst/work/hdpdeps.ref
1,30 → 1,55
V3 13
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/04/27.15:05:22 O.87xd
EN work/baud_generator 1335531934 \
V3 28
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd 2012/04/30.12:36:48 O.87xd
EN work/baud_generator 1335782989 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335531933
AR work/baud_generator/Behavioral 1335531935 \
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335782988
AR work/baud_generator/Behavioral 1335782990 \
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \
EN work/baud_generator 1335531934
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/23.13:47:40 O.87xd
PH work/pkgDefinitions 1335531932 \
EN work/baud_generator 1335782989
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/04/30.07:41:35 O.87xd
EN work/divisor 1335773697 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \
PB work/pkgDefinitions 1335782988
AR work/divisor/Behavioral 1335773698 \
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335773697
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/30.08:38:25 O.87xd
PH work/pkgDefinitions 1335782987 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PB ieee/std_logic_1164 1325952872
PB work/pkgDefinitions 1335531933 \
PB work/pkgDefinitions 1335782988 \
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \
PH work/pkgDefinitions 1335531932
PH work/pkgDefinitions 1335782987
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/30.09:05:24 O.87xd
EN work/serial_receiver 1335782993 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335782988
AR work/serial_receiver/Behavioral 1335782994 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \
EN work/serial_receiver 1335782993
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd
EN work/serial_transmitter 1335782991 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335782988
AR work/serial_transmitter/Behavioral 1335782992 \
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335782991
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/04/30.10:14:50 O.87xd
EN work/uart_control 1335773699 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335782988
AR work/uart_control/Behavioral 1335773700 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \
EN work/uart_control 1335773699 CP divisor
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd
EN work/uart_communication_blocks 1335782995 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335782988
AR work/uart_communication_blocks/Behavioral 1335782996 \
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd \
EN work/uart_communication_blocks 1335782995 CP baud_generator \
CP serial_transmitter CP serial_receiver
FL E:/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/04/21.14:17:54 O.87xd
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd 2012/04/21.14:22:33 O.87xd
EN work/serial_receiver 1335010959 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd PB ieee/std_logic_1164 1325952872 \
PB work/pkgDefinitions 1335531933
AR work/serial_receiver/Behavioral 1335010960 \
FL E:/uart_block/hdl/iseProject/serial_receiver.vhd EN work/serial_receiver 1335010959
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/21.09:27:16 O.87xd
EN work/serial_transmitter 1335001307 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335531933
AR work/serial_transmitter/Behavioral 1335001308 \
FL E:/uart_block/hdl/iseProject/serial_transmitter.vhd \
EN work/serial_transmitter 1335001307
/hdl/iseProject/xst/work/hdllib.ref
1,8 → 1,14
AR serial_transmitter behavioral E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335001308
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335531935
EN serial_receiver NULL E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335010959
EN serial_transmitter NULL E:/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335001307
AR serial_receiver behavioral E:/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335010960
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335531933
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335531934
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335531932
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335773699
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335782992
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335782990
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335782993
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335773697
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335773698
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335782991
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd sub00/vhpl13 1335782996
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335782994
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd sub00/vhpl12 1335782995
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335782988
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335773700
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335782989
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335782987
/hdl/iseProject/xst/work/sub00/vhpl00.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/hdl/iseProject/xst/work/sub00/vhpl01.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/hdl/iseProject/xst/work/sub00/vhpl02.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/hdl/iseProject/xst/work/sub00/vhpl03.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/hdl/iseProject/xst/work/sub00/vhpl04.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/hdl/iseProject/xst/work/sub00/vhpl05.vho Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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