URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/trunk/hdl/iseProject/isim.log
1,5 → 1,5
ISim log file |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.wdb |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
11,10 → 11,13
# run 1000 ms |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testUart_control.vhd:stim_proc |
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
# exit 0 |
/trunk/hdl/iseProject/fuseRelaunch.cmd
1,10 → 11,13
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control_beh.prj" "work.testUart_control" |
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave" |
/trunk/hdl/iseProject/testUart_control.vhd
90,9 → 90,10
stim_proc: process |
begin |
rst <= '1'; |
wait for 1 ns; |
start <= '0'; |
wait for clk_period; |
rst <= '0'; |
wait for clk_period*3; |
wait for clk_period; |
|
-- Configure the clock... |
reg_addr <= "00"; |
122,7 → 123,19
WE <= '1'; |
start <= '1'; |
DAT_I <= x"00000055"; |
wait for clk_period*10; -- No point to use wait until because we're not connected to the comm block yet |
wait until done = '1'; |
WE <= '0'; |
start <= '0'; |
reg_addr <= (others => 'U'); |
wait for clk_period; |
|
-- Ask to read some data... |
reg_addr <= "11"; |
WE <= '0'; |
start <= '1'; |
wait until done = '1'; |
start <= '0'; |
wait for clk_period*10; |
|
-- Stop Simulation |
assert false report "NONE. End of simulation." severity failure; |
/trunk/hdl/iseProject/uart_control.vhd
1,6 → 1,8
--! uart control unit |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_1164.ALL; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
--! Use CPU Definitions package |
use work.pkgDefinitions.all; |
26,16 → 28,23
architecture Behavioral of uart_control is |
signal config_clk : std_logic_vector((nBitsLarge-1) downto 0); |
signal config_baud : std_logic_vector((nBitsLarge-1) downto 0); |
--signal byte_to_receive : std_logic_vector((nBits-1) downto 0); |
signal byte_to_transmitt : std_logic_vector((nBits-1) downto 0); |
signal controlStates : uartControl; |
signal received_byte : std_logic_vector((nBits-1) downto 0); |
signal byte_to_transmit : std_logic_vector((nBits-1) downto 0); |
|
signal sigDivRst : std_logic; |
signal sigDivDone : std_logic; |
signal sigDivQuotient : std_logic_vector((nBitsLarge-1) downto 0); |
--signal sigDivReminder : std_logic_vector((nBitsLarge-1) downto 0); |
signal sigDivNumerator : std_logic_vector((nBitsLarge-1) downto 0); |
signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0); |
signal sigDivDividend : std_logic_vector((nBitsLarge-1) downto 0); |
|
-- Signals used to control the configuration |
signal startConfigBaud : std_logic; |
signal startConfigClk : std_logic; |
signal startDataSend : std_logic; |
signal commBlocksInitiated : std_logic; |
signal finishedDataSend : std_logic; |
signal doneWriteReg : std_logic; |
signal startReadReg : std_logic; |
|
-- Divisor component |
component divisor is |
60,192 → 69,194
done => sigDivDone |
); |
|
-- Process that read uart control registers |
process (rst, reg_addr, WE, start, byte_to_transmitt, data_byte_rx, rx_data_ready, config_clk, config_baud) |
-- Process to handle the of writting the registers |
process (clk) |
begin |
if rst = '1' then |
DAT_O <= (others => 'Z'); |
else |
if (WE = '0') and (start = '1') then |
case reg_addr is |
when "00" => |
DAT_O <= config_clk; |
when "01" => |
DAT_O <= config_baud; |
when "10" => |
-- Byte that will be transmitted |
DAT_O <= "000000000000000000000000" & byte_to_transmitt; |
when "11" => |
-- Byte that will be received |
if rx_data_ready = '1' then |
DAT_O <= "000000000000000000000000" & data_byte_rx; |
--DAT_O <= "000000000000000000000000" & byte_to_receive; |
else |
DAT_O <= (others => 'Z'); |
end if; |
when others => |
DAT_O <= (others => 'Z'); |
end case; |
else |
DAT_O <= (others => 'Z'); |
end if; |
end if; |
-- On the wishbone specification we should handle the reset synchronously |
if rising_edge(clk) then |
if rst = '1' then |
config_clk <= (others => '0'); |
config_baud <= (others => '0'); |
byte_to_transmit <= (others => '0'); |
startConfigBaud <= '0'; |
startConfigClk <= '0'; |
startDataSend <= '0'; |
doneWriteReg <= '0'; |
elsif (WE and start) = '1' then |
case reg_addr is |
when "00" => |
config_clk <= DAT_I; |
startConfigClk <= '1'; |
startDataSend <= '0'; |
startConfigBaud <= '0'; |
when "01" => |
config_baud <= DAT_I; |
startConfigBaud <= '1'; |
startDataSend <= '0'; |
startConfigClk <= '0'; |
when "10" => |
-- If we have an overrun, discard the byte |
if finishedDataSend = '1' then |
byte_to_transmit <= DAT_I((nBits-1) downto 0); |
else |
byte_to_transmit <= byte_to_transmit; |
end if; |
startConfigBaud <= '0'; |
startConfigClk <= '0'; |
startDataSend <= '1'; |
when others => |
startConfigBaud <= '0'; |
startConfigClk <= '0'; |
startDataSend <= '0'; |
end case; |
end if; |
end if; |
end process; |
|
-- Process that populate the uart control registers |
process (rst, clk, reg_addr,WE,start) |
begin |
if rst = '1' then |
config_clk <= (others => '0'); |
config_baud <= (others => '0'); |
byte_to_transmitt <= (others => '0'); |
elsif rising_edge(clk) then |
if (WE = '1') and (start = '1') then |
case reg_addr is |
when "00" => |
config_clk <= DAT_I; |
when "01" => |
config_baud <= DAT_I; |
when "10" => |
-- Byte that will be transmitted |
byte_to_transmitt <= DAT_I((nBits-1) downto 0); |
when others => |
null; |
end case; |
end if; |
end if; |
end process; |
|
-- Process to handle the next state logic |
process (rst, clk, reg_addr, WE, start) |
variable baud_configured : std_logic; |
variable clk_configured : std_logic; |
variable div_result_baud_wait : std_logic_vector ((nBitsLarge-1) downto 0); |
begin |
if rst = '1' then |
controlStates <= idle; |
baud_configured := '0'; |
clk_configured := '0'; |
div_result_baud_wait := (others => '0'); |
done <= '0'; |
sigDivRst <= '1'; |
rst_comm_blocks <= '1'; |
tx_start <= '0'; |
--byte_to_receive <= (others => 'Z'); |
elsif rising_edge(clk) then |
case controlStates is |
when idle => |
done <= '0'; |
-- Go to config state |
if (reg_addr = "00") and (WE = '1') then |
controlStates <= config_state_clk; |
clk_configured := '1'; |
elsif (reg_addr = "01") and (WE = '1') then |
controlStates <= config_state_baud; |
baud_configured := '1'; |
end if; |
|
when config_state_clk => |
sigDivRst <= '1'; |
sigDivNumerator <= config_clk; |
if baud_configured = '0' then |
-- Baud not configured yet so wait for it... |
controlStates <= idle; |
done <= '1'; |
else |
-- If already configured wait for division completion... |
controlStates <= start_division; |
end if; |
|
when config_state_baud => |
sigDivRst <= '1'; |
sigDivDividend <= config_baud; |
if clk_configured = '0' then |
-- Clock not configured yet so wait for it... |
controlStates <= idle; |
done <= '1'; |
else |
-- If already configured wait for division completion... |
controlStates <= start_division; |
end if; |
|
when start_division => |
sigDivRst <= '0'; |
controlStates <= wait_division; |
|
when wait_division => |
if sigDivDone = '0' then |
controlStates <= wait_division; |
else |
-- Division done, get the result to put on the wait_cycles signal of the baud generator |
div_result_baud_wait := sigDivQuotient; |
controlStates <= config_state_baud_generator; |
end if; |
|
when config_state_baud_generator => |
-- Configure the wait_cycle for the desired baud rate... |
baud_wait <= div_result_baud_wait; |
controlStates <= rx_tx_state; |
-- Process to handle the reading of registers |
process (clk) |
begin |
-- On the wishbone specification we should handle the reset synchronously |
if rising_edge(clk) then |
if rst = '1' then |
DAT_O <= (others => 'Z'); |
startReadReg <= '0'; |
elsif ((WE = '0') and (start = '1')) then |
startReadReg <= '1'; |
case reg_addr is |
when "00" => |
DAT_O <= config_clk; |
when "01" => |
DAT_O <= config_baud; |
when "10" => |
DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & byte_to_transmit; |
when "11" => |
DAT_O <= conv_std_logic_vector(0, (nBitsLarge-nBits)) & received_byte; |
when others => |
null; |
end case; |
end if; |
end if; |
end process; |
|
-- Process that stores the data that comes from the serial receiver block |
process (rx_data_ready) |
begin |
if rising_edge(rx_data_ready) then |
received_byte <= data_byte_rx; |
else |
received_byte <= received_byte; |
end if; |
end process; |
|
-- Process to send data over the serial transmitter |
process (startDataSend, commBlocksInitiated, clk) |
variable cont_steps : integer range 0 to 3; |
begin |
if (startDataSend = '0' and commBlocksInitiated = '0') then |
data_byte_tx <= (others => '0'); |
tx_start <= '0'; |
finishedDataSend <= '1'; |
elsif rising_edge(clk) then |
if cont_steps < 3 then |
cont_steps := cont_steps + 1; |
else |
cont_steps := 3; |
end if; |
|
case cont_steps is |
when 1 => |
data_byte_tx <= byte_to_transmit; |
tx_start <= '0'; |
when 2 => |
tx_start <= '1'; |
when others => |
null; |
end case; |
|
if tx_data_sent = '1' then |
finishedDataSend <= '1'; |
else |
finishedDataSend <= '0'; |
end if; |
|
end if; |
end process; |
|
-- Process to send the ACK signal, remember that optimally this ACK should be as fast as possible |
-- to avoid locking the bus, on this case if you send a more bytes then you can transmit the ideal |
-- is to create an error flag to indicate overrun. |
-- On this case on any attempt of reading or writting on registers we will be lock on 1 cycle |
process (clk, rst, startConfigBaud, startConfigClk, startDataSend, startReadReg ) |
variable joinSignal : std_logic_vector(3 downto 0); |
variable cont_steps : integer range 0 to 3; |
begin |
if rising_edge(clk) then |
if rst = '1' then |
done <= '1'; |
cont_steps := 0; |
else |
joinSignal := startConfigBaud & startConfigClk & startDataSend & startReadReg; |
if (joinSignal = "0000") then |
done <= '1'; |
|
-- Control the serial_receiver or serial_transmitter block |
when rx_tx_state => |
rst_comm_blocks <= '0'; |
tx_start <= '0'; |
controlStates <= rx_tx_state; |
if (WE = '1') and (start = '1') then |
if reg_addr = "10" then |
controlStates <= tx_state_wait; |
done <= '0'; |
end if; |
end if; |
else |
case cont_steps is |
when 0 => |
if start = '1' then |
done <= '0'; |
end if; |
when others => |
done <= '1'; |
end case; |
|
if (WE = '0') and (start = '1') then |
case reg_addr is |
when "11" => |
controlStates <= rx_state_wait; |
|
when "10" => |
done <= '1'; |
controlStates <= rx_tx_state; |
|
when others => |
null; |
end case; |
end if; |
|
if (start = '0') then |
done <= '0'; |
end if; |
|
|
-- Send data and wait to transmit |
when tx_state_wait => |
tx_start <= '1'; |
data_byte_tx <= byte_to_transmitt; |
if tx_data_sent = '0' then |
controlStates <= tx_state_wait; |
if cont_steps < 2 then |
cont_steps := cont_steps + 1; |
else |
controlStates <= rx_tx_state; |
done <= '1'; |
cont_steps := 0; |
end if; |
|
-- Receive data and wait to receive |
when rx_state_wait => |
if rx_data_ready = '1' then |
-- Put an ack on the next cycle |
controlStates <= rx_state_ack; |
else |
controlStates <= rx_state_wait; |
done <= '0'; |
end if; |
|
-- Ack that we got a value |
when rx_state_ack => |
done <= '1'; |
controlStates <= rx_tx_state; |
end case; |
end if; |
end if; |
end if; |
end if; |
end process; |
|
-- Process to calculate the amount of cycles to wait (clock_speed / desired_baud), and initiate the board |
process (startConfigBaud,startConfigClk, clk) |
variable cont_steps : integer range 0 to 3; |
begin |
if (startConfigBaud and startConfigClk) = '0' then |
sigDivRst <= '1'; |
cont_steps := 0; |
baud_wait <= (others => '0'); |
commBlocksInitiated <= '0'; |
elsif rising_edge(clk) then |
if cont_steps < 3 then |
cont_steps := cont_steps + 1; |
else |
cont_steps := 3; |
end if; |
|
case cont_steps is |
when 1 => |
sigDivNumerator <= config_clk; |
sigDivDividend <= config_baud; |
sigDivRst <= '1'; |
when 2 => |
sigDivRst <= '0'; |
when others => |
null; |
end case; |
|
-- Enable the communication block when the baud is calculated |
if sigDivDone = '1' then |
rst_comm_blocks <= '0'; |
baud_wait <= sigDivQuotient; |
commBlocksInitiated <= '1'; |
else |
baud_wait <= (others => '0'); |
rst_comm_blocks <= '1'; |
commBlocksInitiated <= '0'; |
end if; |
end if; |
end process; |
|
end Behavioral; |
/trunk/hdl/iseProject/fuse.log
1,15 → 1,21
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_beh.prj work.testUart_control |
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
Determining compilation order of HDL files |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work |
WARNING:HDLCompiler:946 - "/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port rst is neither a static name nor a globally static expression |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 36628 KB |
Fuse Memory Usage: 37476 KB |
Fuse CPU Usage: 1100 ms |
Compiling package standard |
Compiling package std_logic_1164 |
18,11 → 24,16
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity divisor [divisor_default] |
Compiling architecture behavioral of entity uart_control [uart_control_default] |
Compiling architecture behavior of entity testuart_control |
Compiling package numeric_std |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default] |
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default] |
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...] |
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Time Resolution for simulation is 1ps. |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 10 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_control_isim_beh.exe |
Fuse Memory Usage: 85692 KB |
Fuse CPU Usage: 1180 ms |
GCC CPU Usage: 400 ms |
Compiled 21 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 91188 KB |
Fuse CPU Usage: 1280 ms |
GCC CPU Usage: 710 ms |
/trunk/hdl/iseProject/webtalk_pn.xml
3,7 → 3,7
<!--The data in this file is primarily intended for consumption by Xilinx tools. |
The structure and the elements are likely to change over the next few releases. |
This means code written to parse this file will need to be revisited each subsequent release.--> |
<application name="pn" timeStamp="Wed May 2 08:01:19 2012"> |
<application name="pn" timeStamp="Wed May 2 13:09:03 2012"> |
<section name="Project Information" visible="false"> |
<property name="ProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="project"/> |
<property name="ProjectIteration" value="0" type="project"/> |
19,7 → 19,7
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/> |
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/> |
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_wishbone_slave" type="process"/> |
<property name="PROP_SelectedInstanceHierarchicalPath" value="/testUart_control" type="process"/> |
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/> |
<property name="PROP_SynthTopFile" value="changed" type="process"/> |
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/> |
29,7 → 29,7
<property name="PROP_intWbtProjectID" value="225093D1BA50465FB2D0D99DBD16A3DC" type="design"/> |
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> |
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_wishbone_slave" type="process"/> |
<property name="PROP_selectedSimRootSourceNode_behav" value="work.testUart_control" type="process"/> |
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/> |
<property name="PROP_AutoTop" value="false" type="design"/> |
<property name="PROP_CompxlibEdkSimLib" value="true" type="process"/> |
/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
11,5 → 11,8
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testUart_control.vhd" into library work</arg> |
</msg> |
|
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/trunk/hdl/iseProject/_xmsgs/xst.xmsgs
5,110 → 5,107
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">53</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
<msg type="warning" file="Xst" num="753" delta="old" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">62</arg>: Unconnected output port '<arg fmt="%s" index="3">reminder</arg>' of component '<arg fmt="%s" index="4">divisor</arg>'. |
</msg> |
|
<msg type="info" file="Xst" num="1561" delta="old" >"<arg fmt="%s" index="1">/home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd</arg>" line <arg fmt="%d" index="2">84</arg>: Mux is complete : default of case is discarded |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_30</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_29</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_28</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_27</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_26</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_25</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_24</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_23</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_22</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_21</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_20</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_19</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_18</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_17</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_16</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_15</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_14</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_13</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/reminder_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
<msg type="warning" file="Xst" num="2677" delta="old" >Node <<arg fmt="%s" index="1">uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">uDiv/R_31</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">uart_control</arg>>. |
</msg> |
|
</messages> |
|
/trunk/hdl/iseProject/fuse.xmsgs
5,5 → 5,8
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"/home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 63: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression |
</msg> |
|
</messages> |
|
/trunk/hdl/iseProject/iseProject.xise
16,7 → 16,7
|
<files> |
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL"> |
30,7 → 30,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/> |
</file> |
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL"> |
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/> |
</file> |
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL"> |
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/> |
</file> |
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL"> |
60,7 → 60,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/> |
</file> |
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL"> |
70,21 → 70,21
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/> |
</file> |
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="117"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="117"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/> |
</file> |
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/> |
313,8 → 313,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_control" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_control" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
330,7 → 330,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_control" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
379,7 → 379,7
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_control|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
/trunk/hdl/iseProject/xst/work/hdpdeps.ref
4,28 → 4,28
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB ieee/NUMERIC_STD 1325952877 \ |
PB work/pkgDefinitions 1335938484 |
PB work/pkgDefinitions 1335956947 |
AR work/baud_generator/Behavioral 1335938432 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd \ |
EN work/baud_generator 1335938431 |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd 2012/05/01.08:01:47 O.87xd |
EN work/divisor 1335938485 \ |
EN work/divisor 1335956948 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd \ |
PB ieee/std_logic_1164 1325952872 PB ieee/std_logic_arith 1325952873 \ |
PB work/pkgDefinitions 1335938484 |
AR work/divisor/Behavioral 1335938486 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335938485 |
PB work/pkgDefinitions 1335956947 |
AR work/divisor/Behavioral 1335956949 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd EN work/divisor 1335956948 |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd 2012/05/02.07:33:56 O.87xd |
PH work/pkgDefinitions 1335938483 \ |
PH work/pkgDefinitions 1335956946 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PB ieee/std_logic_1164 1325952872 |
PB work/pkgDefinitions 1335938484 \ |
PB work/pkgDefinitions 1335956947 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd \ |
PH work/pkgDefinitions 1335938483 |
PH work/pkgDefinitions 1335956946 |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd 2012/05/01.13:58:15 O.87xd |
EN work/serial_receiver 1335938435 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484 |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335956947 |
AR work/serial_receiver/Behavioral 1335938436 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd \ |
EN work/serial_receiver 1335938435 |
32,7 → 32,7
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd 2012/04/23.13:47:40 O.87xd |
EN work/serial_transmitter 1335938433 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484 |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335956947 |
AR work/serial_transmitter/Behavioral 1335938434 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd \ |
EN work/serial_transmitter 1335938433 |
39,23 → 39,24
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd 2012/04/30.14:08:50 O.87xd |
EN work/uart_communication_blocks 1335938441 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484 |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335956947 |
AR work/uart_communication_blocks/Behavioral 1335938442 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd \ |
EN work/uart_communication_blocks 1335938441 CP baud_generator \ |
CP serial_transmitter CP serial_receiver |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.07:33:56 O.87xd |
EN work/uart_control 1335938487 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd 2012/05/02.13:07:28 O.87xd |
EN work/uart_control 1335956950 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484 |
AR work/uart_control/Behavioral 1335938488 \ |
PB ieee/std_logic_1164 1325952872 PB ieee/STD_LOGIC_UNSIGNED 1325952875 \ |
PB ieee/std_logic_arith 1325952873 PB work/pkgDefinitions 1335956947 |
AR work/uart_control/Behavioral 1335956951 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd \ |
EN work/uart_control 1335938487 CP divisor |
EN work/uart_control 1335956950 CP divisor |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_main_blocks.vhd 2012/04/30.12:49:26 O.87xd |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd 2012/04/30.18:16:53 O.87xd |
EN work/uart_wishbone_slave 1335938443 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335938484 |
PB ieee/std_logic_1164 1325952872 PB work/pkgDefinitions 1335956947 |
AR work/uart_wishbone_slave/Behavioral 1335938444 \ |
FL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd \ |
EN work/uart_wishbone_slave 1335938443 CP uart_control \ |
/trunk/hdl/iseProject/xst/work/hdllib.ref
1,16 → 1,16
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335938487 |
EN uart_control NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl10 1335956950 |
AR serial_transmitter behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl03 1335938434 |
EN uart_wishbone_slave NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl14 1335938443 |
AR baud_generator behavioral /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl07 1335938432 |
EN serial_receiver NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl04 1335938435 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335938485 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335938486 |
EN divisor NULL /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl08 1335956948 |
AR divisor behavioral /home/laraujo/work/uart_block/hdl/iseProject/divisor.vhd sub00/vhpl09 1335956949 |
EN serial_transmitter NULL /home/laraujo/work/uart_block/hdl/iseProject/serial_transmitter.vhd sub00/vhpl02 1335938433 |
AR uart_communication_blocks behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl13 1335938442 |
AR uart_wishbone_slave behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_wishbone_slave.vhd sub00/vhpl15 1335938444 |
AR serial_receiver behavioral /home/laraujo/work/uart_block/hdl/iseProject/serial_receiver.vhd sub00/vhpl05 1335938436 |
EN uart_communication_blocks NULL /home/laraujo/work/uart_block/hdl/iseProject/uart_communication_blocks.vhd sub00/vhpl12 1335938441 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335938484 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335938488 |
PB pkgdefinitions pkgdefinitions /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl01 1335956947 |
AR uart_control behavioral /home/laraujo/work/uart_block/hdl/iseProject/uart_control.vhd sub00/vhpl11 1335956951 |
EN baud_generator NULL /home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd sub00/vhpl06 1335938431 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335938483 |
PH pkgdefinitions NULL /home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd sub00/vhpl00 1335956946 |