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Rev 4 → Rev 5

/trunk/hdl/iseProject/testDivisor.vhd
0,0 → 1,110
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:35:04 04/20/2012
-- Design Name:
-- Module Name: /home/laraujo/work/uartVHDLWishBone/testDivisor.vhd
-- Project Name: uartVHDLWishBone
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: divisor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testDivisor IS
END testDivisor;
ARCHITECTURE behavior OF testDivisor IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT divisor
PORT(
rst : IN std_logic;
clk : IN std_logic;
quotient : OUT std_logic_vector(31 downto 0);
reminder : OUT std_logic_vector(31 downto 0);
numerator : IN std_logic_vector(31 downto 0);
divident : IN std_logic_vector(31 downto 0);
done : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal numerator : std_logic_vector(31 downto 0) := (others => '0');
signal divident : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal quotient : std_logic_vector(31 downto 0);
signal reminder : std_logic_vector(31 downto 0);
signal done : std_logic;
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: divisor PORT MAP (
rst => rst,
clk => clk,
quotient => quotient,
reminder => reminder,
numerator => numerator,
divident => divident,
done => done
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
numerator <= conv_std_logic_vector(50000000, 32);
divident <= conv_std_logic_vector(115200, 32);
wait for 20 ns;
rst <= '0';
 
wait for clk_period*32;
 
-- insert stimulus here
 
wait;
end process;
 
END;
/trunk/hdl/iseProject/divisor.vhd
0,0 → 1,63
--! Unsigned division circuit, based on slow division algorithm (Restoring division)
--! http://en.wikipedia.org/wiki/Division_%28digital%29
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
 
entity divisor is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
quotient : out STD_LOGIC_VECTOR (31 downto 0);
reminder : out STD_LOGIC_VECTOR (31 downto 0);
numerator : in STD_LOGIC_VECTOR (31 downto 0);
divident : in STD_LOGIC_VECTOR (31 downto 0);
done : out STD_LOGIC);
end divisor;
 
architecture Behavioral of divisor is
 
begin
-- Division algorithm Q=N/D
process (rst, clk)
variable Q : unsigned(quotient'length-1 downto 0);
variable R : unsigned(reminder'length-1 downto 0);
variable D : unsigned(reminder'length-1 downto 0);
variable N : unsigned(reminder'length-1 downto 0);
variable iteractions : integer;
begin
if (rst = '1') then
quotient <= (others => '0');
reminder <= (others => '0');
done <= '0';
-- Initialize variables
iteractions := quotient'length;
D := unsigned(divident);
N := unsigned(numerator);
-- initialize quotient and remainder to zero
Q := (others => '0');
R := (others => '0');
elsif rising_edge(clk) then
if iteractions > 0 then
iteractions := iteractions - 1;
-- left-shift R by 1 bit
R := (R((R'HIGH - 1) downto 0) & '0');
--set the least-significant bit of R equal to bit i of the numerator(dividend)
R(0) := N(iteractions);
if (R >= D) then
R := R - D;
Q(iteractions) := '1';
end if;
else
done <= '1';
quotient <= CONV_STD_LOGIC_VECTOR(Q,32);
reminder <= CONV_STD_LOGIC_VECTOR(R,32);
end if;
end if;
end process;
 
end Behavioral;
 

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