URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/uart_block
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/trunk/hdl/iseProject/isim.log
1,20 → 1,19
ISim log file |
Running: /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.wdb |
ISim O.87xd (signature 0x8ddf5b5d) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 us |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testBaud_generator.vhd:stim_proc |
|
INFO: Simulator is stopped. |
# exit 0 |
ISim log file |
Running: E:\uart_block\hdl\iseProject\testBaud_generator_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.wdb |
ISim O.87xd (signature 0xc3576ebc) |
WARNING: A WEBPACK license was found. |
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. |
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. |
This is a Lite version of ISim. |
Time resolution is 1 ps |
# onerror resume |
# wave add / |
# run 1000 us |
Simulator is doing circuit initialization process. |
Finished circuit initialization process. |
|
** Failure:NONE. End of simulation. |
User(VHDL) Code Called Simulation Stop |
In process testBaud_generator.vhd:stim_proc |
|
INFO: Simulator is stopped. |
/trunk/hdl/iseProject/fuseRelaunch.cmd
1,20 → 1,19
-intstyle "ise" -incremental -o "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe" -prj "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj" "work.testBaud_generator" |
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testBaud_generator_beh.prj" "work.testBaud_generator" |
/trunk/hdl/iseProject/iseProject.gise
32,6 → 32,7
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="baud_generator.syr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="baud_generator.xst"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_envsettings.html"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="baud_generator_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="baud_generator_summary.html"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="baud_generator_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="baud_generator_xst.xrpt"/> |
75,11 → 76,11
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1334961595" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1334961595"> |
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335536081" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335536081"> |
<transform xil_pn:end_ts="1335696912" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
92,19 → 93,19
<outfile xil_pn:name="testSerial_receiver.vhd"/> |
<outfile xil_pn:name="testSerial_transmitter.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335532465" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8005028302593154456" xil_pn:start_ts="1335532465"> |
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8005028302593154456" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335532465" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5095109948935799194" xil_pn:start_ts="1335532465"> |
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5095109948935799194" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335532006" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8789037243651182739" xil_pn:start_ts="1335532006"> |
<transform xil_pn:end_ts="1335696912" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8789037243651182739" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335536081" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335536081"> |
<transform xil_pn:end_ts="1335696912" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
117,11 → 118,9
<outfile xil_pn:name="testSerial_receiver.vhd"/> |
<outfile xil_pn:name="testSerial_transmitter.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335536082" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4428763588696016622" xil_pn:start_ts="1335536081"> |
<transform xil_pn:end_ts="1335696915" xil_pn:in_ck="-5639112701713756110" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4428763588696016622" xil_pn:start_ts="1335696912"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
129,11 → 128,9
<outfile xil_pn:name="testBaud_generator_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1335536083" xil_pn:in_ck="9031792592001735694" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7081210365766751130" xil_pn:start_ts="1335536082"> |
<transform xil_pn:end_ts="1335696915" xil_pn:in_ck="6990163578190363152" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7081210365766751130" xil_pn:start_ts="1335696915"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testBaud_generator_isim_beh.wdb"/> |
/trunk/hdl/iseProject/fuse.log
1,25 → 1,23
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -prj /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_beh.prj work.testBaud_generator |
ISim O.87xd (signature 0x8ddf5b5d) |
Number of CPUs detected in this system: 4 |
Turning on mult-threading, number of parallel sub-compilation jobs: 8 |
Determining compilation order of HDL files |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Fuse Memory Usage: 36644 KB |
Fuse CPU Usage: 1080 ms |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package std_logic_unsigned |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavior of entity testbaud_generator |
Time Resolution for simulation is 1ps. |
Compiled 8 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe |
Fuse Memory Usage: 85592 KB |
Fuse CPU Usage: 1160 ms |
GCC CPU Usage: 260 ms |
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testBaud_generator_beh.prj work.testBaud_generator |
ISim O.87xd (signature 0xc3576ebc) |
Number of CPUs detected in this system: 8 |
Turning on mult-threading, number of parallel sub-compilation jobs: 16 |
Determining compilation order of HDL files |
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work |
Parsing VHDL file "E:/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work |
Starting static elaboration |
Completed static elaboration |
Compiling package standard |
Compiling package std_logic_1164 |
Compiling package std_logic_arith |
Compiling package std_logic_unsigned |
Compiling package pkgdefinitions |
Compiling architecture behavioral of entity baud_generator [baud_generator_default] |
Compiling architecture behavior of entity testbaud_generator |
Time Resolution for simulation is 1ps. |
Waiting for 1 sub-compilation(s) to finish... |
Compiled 8 VHDL Units |
Built simulation executable E:/uart_block/hdl/iseProject/testBaud_generator_isim_beh.exe |
Fuse Memory Usage: 33672 KB |
Fuse CPU Usage: 280 ms |
/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/uart_block/hdl/iseProject/testBaud_generator.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work</arg> |
</msg> |
|
</messages> |
|
/trunk/hdl/iseProject/baud_generator.vhd
27,7 → 27,9
half_cycle := '0' & cycle_wait(cycle_wait'high downto 1); |
genTick <= '0'; |
elsif rising_edge(clk) then |
if wait_clk_cycles = cycle_wait then |
-- Just decremented the cycle_wait by one because genTick would be updated on the next cycle |
-- and we really want to bring genTick <= '1' when (wait_clk_cycles = cycle_wait) |
if wait_clk_cycles = (cycle_wait - conv_std_logic_vector(1, (nBitsLarge-1))) then |
genTick <= '1'; |
wait_clk_cycles := (others => '0'); |
else |
/trunk/hdl/iseProject/testBaud_generator.vhd
32,8 → 32,8
--Outputs |
signal baud : std_logic; |
|
-- Clock period definitions |
constant clk_period : time := 10 ns; |
-- Clock period definitions (1.8432MHz) |
constant clk_period : time := 5.43 us; |
|
BEGIN |
|
60,8 → 60,8
begin |
-- Test the baud generator waiting for 10 clock cycles |
rst <= '1'; |
cycle_wait <= conv_std_logic_vector(2, (nBitsLarge)); |
wait for 10 ns; |
cycle_wait <= conv_std_logic_vector(16, (nBitsLarge)); |
wait for 10 us; |
rst <= '0'; |
|
wait for clk_period*100; |
/trunk/hdl/iseProject/fuse.xmsgs
1,9 → 1,9
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated |
by the Xilinx ISE software. Any direct editing or |
changes made to this file may result in unpredictable |
behavior or data corruption. It is strongly advised that |
users do not edit the contents of this file. --> |
<messages> |
</messages> |
|
|
/trunk/hdl/iseProject/xilinxsim.ini
1,9 → 1,9
work=isim/work |
work=isim/work |
/trunk/hdl/iseProject/isim.cmd
1,3 → 1,3
onerror {resume} |
wave add / |
run 1000 us; |
onerror {resume} |
wave add / |
run 1000 us; |
/trunk/hdl/iseProject/iseProject.xise
85,7 → 85,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |