URL
https://opencores.org/ocsvn/uart_fiber/uart_fiber/trunk
Subversion Repositories uart_fiber
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/uart_fiber
- from Rev 12 to Rev 13
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Rev 12 → Rev 13
/trunk/Version3/spdif_to_RX.vhd
0,0 → 1,88
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library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.std_logic_unsigned.all; |
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entity spdif_to_RX is |
Port ( iCLK : in STD_LOGIC; |
optic_in : in STD_LOGIC; |
RX : out STD_LOGIC; |
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periodA : in STD_LOGIC_VECTOR(6 downto 0); |
period10 : in STD_LOGIC_VECTOR(6 downto 0) |
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); |
end spdif_to_RX; |
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architecture Behavioral of spdif_to_RX is |
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--low pass |
signal q1 : STD_LOGIC; |
signal q2 : STD_LOGIC; |
signal samp : STD_LOGIC; |
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--RX generator |
signal samp2 : STD_LOGIC; |
signal cnt : STD_LOGIC_VECTOR(7 downto 0); |
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--signal learn : STD_LOGIC; |
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signal RX2 : STD_LOGIC; |
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begin |
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input_low_pass:process (iCLK) |
begin |
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if (iCLK'event and iCLK= '1') then |
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q1<=q2; |
q2<=optic_in; |
if(q1=q2)then |
samp<=q1; |
end if; |
end if; |
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end process; |
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fiber_decoder:process (iCLK) |
begin |
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if (iCLK'event and iCLK= '1') then |
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samp2<=samp; |
if(samp2/=samp and samp='1') then |
if(cnt>period10) then |
RX<='0'; --shift 0 |
RX2<='0'; |
elsif (cnt<=periodA) then |
RX<=RX2; --shift 1 |
RX2<='1'; |
else |
RX2<='1';--shift 1 |
end if; |
cnt<=(others=>'0'); |
else |
if(cnt=periodA) then |
RX<=RX2; |
end if; |
cnt<=cnt+1; |
end if; |
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end if; |
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end process; |
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end Behavioral; |
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